1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7/ { 8 aliases { 9 mmc0 = &sdhci; 10 mmc1 = &sdmmc0; 11 mmc2 = &sdmmc1; 12 mmc3 = &sdmmc2; 13 }; 14 15 chosen: chosen { 16 bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait"; 17 }; 18 19 fiq-debugger { 20 compatible = "rockchip,fiq-debugger"; 21 rockchip,serial-id = <2>; 22 rockchip,wake-irq = <0>; 23 /* If enable uart uses irq instead of fiq */ 24 rockchip,irq-mode-enable = <1>; 25 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 26 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>; 27 pinctrl-names = "default"; 28 pinctrl-0 = <&uart2m0_xfer>; 29 status = "okay"; 30 }; 31 32 debug: debug@fd904000 { 33 compatible = "rockchip,debug"; 34 reg = <0x0 0xfd904000 0x0 0x1000>, 35 <0x0 0xfd905000 0x0 0x1000>, 36 <0x0 0xfd906000 0x0 0x1000>, 37 <0x0 0xfd907000 0x0 0x1000>; 38 }; 39 40 cspmu: cspmu@fd90c000 { 41 compatible = "rockchip,cspmu"; 42 reg = <0x0 0xfd90c000 0x0 0x1000>, 43 <0x0 0xfd90d000 0x0 0x1000>, 44 <0x0 0xfd90e000 0x0 0x1000>, 45 <0x0 0xfd90f000 0x0 0x1000>; 46 }; 47}; 48 49&reserved_memory { 50 ramoops: ramoops@110000 { 51 compatible = "ramoops"; 52 reg = <0x0 0x110000 0x0 0xf0000>; 53 record-size = <0x20000>; 54 console-size = <0x80000>; 55 ftrace-size = <0x00000>; 56 pmsg-size = <0x50000>; 57 }; 58}; 59 60&rng { 61 status = "okay"; 62}; 63 64&rockchip_suspend { 65 status = "okay"; 66}; 67 68&vop { 69 disable-win-move; 70}; 71