1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7/dts-v1/; 8 9#include "rk3568.dtsi" 10#include "rk3568-evb.dtsi" 11 12/ { 13 model = "Rockchip RK3568 EVB6 DDR3 V10 Board"; 14 compatible = "rockchip,rk3568-evb6-ddr3-v10", "rockchip,rk3568"; 15 16 rk_headset: rk-headset { 17 compatible = "rockchip_headset"; 18 headset_gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; 19 pinctrl-names = "default"; 20 pinctrl-0 = <&hp_det>; 21 }; 22 23 vcc3v3_pcie: gpio-regulator { 24 compatible = "regulator-fixed"; 25 regulator-name = "vcc3v3_pcie"; 26 regulator-min-microvolt = <3300000>; 27 regulator-max-microvolt = <3300000>; 28 enable-active-high; 29 gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; 30 startup-delay-us = <5000>; 31 vin-supply = <&dc_12v>; 32 }; 33 34 vcc_camera: vcc-camera-regulator { 35 compatible = "regulator-fixed"; 36 gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; 37 pinctrl-names = "default"; 38 pinctrl-0 = <&camera_pwr>; 39 regulator-name = "vcc_camera"; 40 enable-active-high; 41 regulator-always-on; 42 regulator-boot-on; 43 }; 44}; 45 46&bt_sound { 47 status = "disabled"; 48 simple-audio-card,cpu { 49 sound-dai = <&i2s2_2ch>; 50 }; 51}; 52 53&combphy0_us { 54 status = "okay"; 55}; 56 57&combphy1_usq { 58 rockchip,dis-u3otg1-port; 59 status = "okay"; 60}; 61 62&combphy2_psq { 63 status = "okay"; 64}; 65 66/* 67 * video_phy0 needs to be enabled 68 * when dsi0 is enabled 69 */ 70&dsi0 { 71 status = "okay"; 72}; 73 74&dsi0_in_vp0 { 75 status = "disabled"; 76}; 77 78&dsi0_in_vp1 { 79 status = "okay"; 80}; 81 82&dsi0_panel { 83 power-supply = <&vcc3v3_lcd0_n>; 84}; 85 86/* 87 * video_phy1 needs to be enabled 88 * when dsi1 is enabled 89 */ 90&dsi1 { 91 status = "disabled"; 92}; 93 94&dsi1_in_vp0 { 95 status = "disabled"; 96}; 97 98&dsi1_in_vp1 { 99 status = "disabled"; 100}; 101 102&dsi1_panel { 103 power-supply = <&vcc3v3_lcd1_n>; 104}; 105 106/* 107 * power-supply should switche to vcc3v3_lcd1_n 108 * when mipi panel is connected to dsi1. 109 */ 110>1x { 111 power-supply = <&vcc3v3_lcd0_n>; 112}; 113 114&i2c2 { 115 status = "okay"; 116 pinctrl-names = "default"; 117 pinctrl-0 = <&i2c2m1_xfer>; 118 119 mxc6655xa: mxc6655xa@15 { 120 status = "okay"; 121 compatible = "gs_mxc6655xa"; 122 pinctrl-names = "default"; 123 pinctrl-0 = <&mxc6655xa_irq_gpio>; 124 reg = <0x15>; 125 irq-gpio = <&gpio3 RK_PC1 IRQ_TYPE_LEVEL_LOW>; 126 irq_enable = <0>; 127 poll_delay_ms = <30>; 128 type = <SENSOR_TYPE_ACCEL>; 129 power-off-in-suspend = <1>; 130 layout = <4>; 131 }; 132}; 133 134&i2c4 { 135 status = "okay"; 136 os04a10: os04a10@36 { 137 compatible = "ovti,os04a10"; 138 reg = <0x36>; 139 clocks = <&cru CLK_CAM0_OUT>; 140 clock-names = "xvclk"; 141 power-domains = <&power RK3568_PD_VI>; 142 pinctrl-names = "default"; 143 pinctrl-0 = <&cam_clkout0>; 144 reset-gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_LOW>; 145 pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; 146 /* power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; */ 147 rockchip,camera-module-index = <0>; 148 rockchip,camera-module-facing = "back"; 149 rockchip,camera-module-name = "CMK-OT1607-FV1"; 150 /* rockchip,camera-module-lens-name = "M12-4IR-4MP-F16"; */ 151 rockchip,camera-module-lens-name = "M12-40IRC-4MP-F16"; 152 port { 153 ucam_out0: endpoint { 154 remote-endpoint = <&mipi_in_ucam0>; 155 data-lanes = <1 2 3 4>; 156 }; 157 }; 158 }; 159 gc8034: gc8034@37 { 160 compatible = "galaxycore,gc8034"; 161 reg = <0x37>; 162 clocks = <&cru CLK_CAM0_OUT>; 163 clock-names = "xvclk"; 164 power-domains = <&power RK3568_PD_VI>; 165 pinctrl-names = "default"; 166 pinctrl-0 = <&cam_clkout0>; 167 reset-gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_LOW>; 168 pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_LOW>; 169 rockchip,grf = <&grf>; 170 rockchip,camera-module-index = <0>; 171 rockchip,camera-module-facing = "back"; 172 rockchip,camera-module-name = "RK-CMK-8M-2-v1"; 173 rockchip,camera-module-lens-name = "CK8401"; 174 port { 175 gc8034_out: endpoint { 176 remote-endpoint = <&mipi_in_ucam1>; 177 data-lanes = <1 2 3 4>; 178 }; 179 }; 180 }; 181 ov5695: ov5695@36 { 182 status = "okay"; 183 compatible = "ovti,ov5695"; 184 reg = <0x36>; 185 clocks = <&cru CLK_CAM0_OUT>; 186 clock-names = "xvclk"; 187 power-domains = <&power RK3568_PD_VI>; 188 pinctrl-names = "default"; 189 pinctrl-0 = <&cam_clkout0>; 190 reset-gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_LOW>; 191 pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; 192 rockchip,camera-module-index = <0>; 193 rockchip,camera-module-facing = "back"; 194 rockchip,camera-module-name = "TongJu"; 195 rockchip,camera-module-lens-name = "CHT842-MD"; 196 port { 197 ov5695_out: endpoint { 198 remote-endpoint = <&mipi_in_ucam2>; 199 data-lanes = <1 2>; 200 }; 201 }; 202 }; 203}; 204 205&i2c5 { 206 status = "disabled"; 207 208 /delete-node/ mxc6655xa@15; 209}; 210 211&i2s2_2ch { 212 pinctrl-0 = <&i2s2m0_sclktx &i2s2m0_lrcktx &i2s2m0_sdi &i2s2m0_sdo>; 213 rockchip,bclk-fs = <32>; 214 status = "disabled"; 215}; 216 217&csi2_dphy_hw { 218 status = "okay"; 219}; 220 221&csi2_dphy0 { 222 status = "okay"; 223 224 ports { 225 #address-cells = <1>; 226 #size-cells = <0>; 227 port@0 { 228 reg = <0>; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 232 mipi_in_ucam0: endpoint@1 { 233 reg = <1>; 234 remote-endpoint = <&ucam_out0>; 235 data-lanes = <1 2 3 4>; 236 }; 237 mipi_in_ucam1: endpoint@2 { 238 reg = <2>; 239 remote-endpoint = <&gc8034_out>; 240 data-lanes = <1 2 3 4>; 241 }; 242 mipi_in_ucam2: endpoint@3 { 243 reg = <3>; 244 remote-endpoint = <&ov5695_out>; 245 data-lanes = <1 2>; 246 }; 247 }; 248 port@1 { 249 reg = <1>; 250 #address-cells = <1>; 251 #size-cells = <0>; 252 253 csidphy_out: endpoint@0 { 254 reg = <0>; 255 remote-endpoint = <&isp0_in>; 256 }; 257 }; 258 }; 259}; 260 261&rkisp { 262 status = "okay"; 263}; 264 265&rkisp_mmu { 266 status = "okay"; 267}; 268 269&rkisp_vir0 { 270 status = "okay"; 271 272 port { 273 #address-cells = <1>; 274 #size-cells = <0>; 275 276 isp0_in: endpoint@0 { 277 reg = <0>; 278 remote-endpoint = <&csidphy_out>; 279 }; 280 }; 281}; 282 283&video_phy0 { 284 status = "okay"; 285}; 286 287&video_phy1 { 288 status = "disabled"; 289}; 290 291&pcie30phy { 292 status = "okay"; 293}; 294 295&pcie2x1 { 296 reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; 297 vpcie3v3-supply = <&vcc3v3_pcie>; 298 status = "okay"; 299}; 300 301&pcie3x1 { 302 rockchip,bifurcation; 303 reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; 304 vpcie3v3-supply = <&vcc3v3_pcie>; 305 status = "okay"; 306}; 307 308&pcie3x2 { 309 rockchip,bifurcation; 310 reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; 311 vpcie3v3-supply = <&vcc3v3_pcie>; 312 status = "okay"; 313}; 314 315&pinctrl { 316 cam { 317 camera_pwr: camera-pwr { 318 rockchip,pins = 319 /* camera power en */ 320 <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; 321 }; 322 }; 323 324 headphone { 325 hp_det: hp-det { 326 rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; 327 }; 328 }; 329 330 sdio-pwrseq { 331 wifi_enable_h: wifi-enable-h { 332 rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 333 }; 334 335 wifi_32k: wifi-32k { 336 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; 337 }; 338 }; 339 340 wireless-wlan { 341 wifi_host_wake_irq: wifi-host-wake-irq { 342 rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; 343 }; 344 }; 345 346 wireless-bluetooth { 347 uart1_gpios: uart1-gpios { 348 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 349 }; 350 }; 351}; 352 353&route_dsi0 { 354 status = "okay"; 355 connect = <&vp1_out_dsi0>; 356}; 357 358&sdmmc1 { 359 max-frequency = <150000000>; 360 no-sd; 361 no-mmc; 362 bus-width = <4>; 363 disable-wp; 364 cap-sd-highspeed; 365 cap-sdio-irq; 366 keep-power-in-suspend; 367 mmc-pwrseq = <&sdio_pwrseq>; 368 non-removable; 369 pinctrl-names = "default"; 370 pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; 371 sd-uhs-sdr104; 372 status = "okay"; 373}; 374 375&sdmmc2 { 376 status = "disabled"; 377}; 378 379&sdio_pwrseq { 380 clocks = <&pmucru CLK_RTC_32K>; 381 pinctrl-0 = <&wifi_enable_h &wifi_32k>; 382 383 /* 384 * On the module itself this is one of these (depending 385 * on the actual card populated): 386 * - SDIO_RESET_L_WL_REG_ON 387 * - PDN (power down when low) 388 */ 389 reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; 390}; 391 392&spdif_8ch { 393 status = "disabled"; 394}; 395 396&uart1 { 397 status = "okay"; 398 pinctrl-names = "default"; 399 pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; 400}; 401 402&usbhost_dwc3 { 403 phys = <&u2phy0_host>; 404 phy-names = "usb2-phy"; 405 maximum-speed = "high-speed"; 406 status = "okay"; 407}; 408 409&vcc3v3_lcd0_n { 410 gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; 411 enable-active-high; 412}; 413 414&vcc3v3_lcd1_n { 415 gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; 416 enable-active-high; 417}; 418 419&wireless_wlan { 420 pinctrl-names = "default"; 421 pinctrl-0 = <&wifi_host_wake_irq>; 422 WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; 423 WIFI,poweren_gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; 424}; 425 426&wireless_bluetooth { 427 compatible = "bluetooth-platdata"; 428 clocks = <&pmucru CLK_RTC_32K>; 429 clock-names = "ext_clock"; 430 //wifi-bt-power-toggle; 431 uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; 432 pinctrl-names = "default", "rts_gpio"; 433 pinctrl-0 = <&uart1m0_rtsn>; 434 pinctrl-1 = <&uart1_gpios>; 435 BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; 436 BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; 437 BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; 438 status = "okay"; 439}; 440 441&gmac1 { 442 phy-mode = "rgmii"; 443 clock_in_out = "output"; 444 445 snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; 446 snps,reset-active-low; 447 /* Reset time is 20ms, 100ms for rtl8211f */ 448 snps,reset-delays-us = <0 20000 100000>; 449 450 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; 451 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; 452 assigned-clock-rates = <0>, <125000000>; 453 454 pinctrl-names = "default"; 455 pinctrl-0 = <&gmac1m0_miim 456 &gmac1m0_tx_bus2_level3 457 &gmac1m0_rx_bus2 458 &gmac1m0_rgmii_clk_level2 459 &gmac1m0_rgmii_bus_level3>; 460 461 tx_delay = <0x46>; 462 rx_delay = <0x2f>; 463 464 phy-handle = <&rgmii_phy1>; 465 status = "okay"; 466}; 467 468&mdio1 { 469 rgmii_phy1: phy@0 { 470 compatible = "ethernet-phy-ieee802.3-c22"; 471 reg = <0x0>; 472 }; 473}; 474