1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include "rk3566.dtsi" 12#include "rk3566-evb.dtsi" 13 14/ { 15 model = "Rockchip RK3566 EVB3 DDR3 V10 Board"; 16 compatible = "rockchip,rk3566-evb3-DDR3-v10", "rockchip,rk3566"; 17 18 rk_headset: rk-headset { 19 compatible = "rockchip_headset"; 20 headset_gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; 21 pinctrl-names = "default"; 22 pinctrl-0 = <&hp_det>; 23 }; 24 25 vcc3v3_vga: vcc3v3-vga { 26 compatible = "regulator-fixed"; 27 regulator-name = "vcc3v3_vga"; 28 regulator-always-on; 29 regulator-boot-on; 30 gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; 31 enable-active-high; 32 vin-supply = <&vcc3v3_sys>; 33 }; 34 35 vcc_camera: vcc-camera-regulator { 36 compatible = "regulator-fixed"; 37 gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; 38 pinctrl-names = "default"; 39 pinctrl-0 = <&camera_pwr>; 40 regulator-name = "vcc_camera"; 41 enable-active-high; 42 regulator-always-on; 43 regulator-boot-on; 44 }; 45}; 46 47&bt_sound { 48 status = "disabled"; 49 simple-audio-card,cpu { 50 sound-dai = <&i2s2_2ch>; 51 }; 52}; 53 54&combphy1_usq { 55 status = "okay"; 56}; 57 58&csi2_dphy_hw { 59 status = "okay"; 60}; 61 62&csi2_dphy0 { 63 status = "okay"; 64 65 ports { 66 #address-cells = <1>; 67 #size-cells = <0>; 68 port@0 { 69 reg = <0>; 70 #address-cells = <1>; 71 #size-cells = <0>; 72 73 mipi_in_ucam0: endpoint@1 { 74 reg = <1>; 75 remote-endpoint = <&ov5695_out>; 76 data-lanes = <1 2>; 77 }; 78 mipi_in_ucam1: endpoint@2 { 79 reg = <2>; 80 remote-endpoint = <&gc8034_out>; 81 data-lanes = <1 2 3 4>; 82 }; 83 }; 84 port@1 { 85 reg = <1>; 86 #address-cells = <1>; 87 #size-cells = <0>; 88 89 csidphy_out: endpoint@0 { 90 reg = <0>; 91 remote-endpoint = <&isp0_in>; 92 }; 93 }; 94 }; 95}; 96 97/* 98 * video_phy0 needs to be enabled 99 * when dsi0 is enabled 100 */ 101&dsi0 { 102 status = "okay"; 103}; 104 105&dsi0_in_vp0 { 106 status = "disabled"; 107}; 108 109&dsi0_in_vp1 { 110 status = "okay"; 111}; 112 113&dsi0_panel { 114 power-supply = <&vcc3v3_lcd0_n>; 115 reset-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>; 116 pinctrl-names = "default"; 117 pinctrl-0 = <&lcd0_rst_gpio>; 118}; 119 120/* 121 * video_phy1 needs to be enabled 122 * when dsi1 is enabled 123 */ 124&dsi1 { 125 status = "disabled"; 126}; 127 128&dsi1_in_vp0 { 129 status = "disabled"; 130}; 131 132&dsi1_in_vp1 { 133 status = "disabled"; 134}; 135 136&dsi1_panel { 137 power-supply = <&vcc3v3_lcd1_n>; 138 reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; 139 pinctrl-names = "default"; 140 pinctrl-0 = <&lcd1_rst_gpio>; 141}; 142 143&edp { 144 hpd-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; 145 status = "okay"; 146}; 147 148&edp_phy { 149 status = "okay"; 150}; 151 152&edp_in_vp0 { 153 status = "okay"; 154}; 155 156&edp_in_vp1 { 157 status = "disabled"; 158}; 159 160&gmac1 { 161 phy-mode = "rgmii"; 162 clock_in_out = "output"; 163 164 snps,reset-gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; 165 snps,reset-active-low; 166 /* Reset time is 20ms, 100ms for rtl8211f */ 167 snps,reset-delays-us = <0 20000 100000>; 168 169 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; 170 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; 171 assigned-clock-rates = <0>, <125000000>; 172 173 pinctrl-names = "default"; 174 pinctrl-0 = <&gmac1m0_miim 175 &gmac1m0_tx_bus2_level3 176 &gmac1m0_rx_bus2 177 &gmac1m0_rgmii_clk_level2 178 &gmac1m0_rgmii_bus_level3>; 179 180 tx_delay = <0x41>; 181 rx_delay = <0x2e>; 182 183 phy-handle = <&rgmii_phy1>; 184 status = "okay"; 185}; 186 187>1x { 188 power-supply = <&vcc3v3_lcd0_n>; 189}; 190 191&i2c2 { 192 status = "okay"; 193 pinctrl-0 = <&i2c2m1_xfer>; 194 195 gc2145: gc2145@3c { 196 status = "okay"; 197 compatible = "galaxycore,gc2145"; 198 reg = <0x3c>; 199 clocks = <&cru CLK_CIF_OUT>; 200 clock-names = "xvclk"; 201 power-domains = <&power RK3568_PD_VI>; 202 pinctrl-names = "default"; 203 pinctrl-0 = <&cif_clk &cif_dvp_clk &cif_dvp_bus16>; 204 205 /*avdd-supply = <&vcc2v8_dvp>;*/ 206 /*dovdd-supply = <&vcc1v8_dvp>;*/ 207 /*dvdd-supply = <&vcc1v8_dvp>;*/ 208 209 power-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; 210 /*reset-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>;*/ 211 pwdn-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; 212 rockchip,camera-module-index = <1>; 213 rockchip,camera-module-facing = "front"; 214 rockchip,camera-module-name = "CameraKing"; 215 rockchip,camera-module-lens-name = "Largan"; 216 port { 217 gc2145_out: endpoint { 218 remote-endpoint = <&dvp_in_bcam>; 219 }; 220 }; 221 }; 222 223 ov5695: ov5695@36 { 224 status = "okay"; 225 compatible = "ovti,ov5695"; 226 reg = <0x36>; 227 clocks = <&cru CLK_CAM0_OUT>; 228 clock-names = "xvclk"; 229 power-domains = <&power RK3568_PD_VI>; 230 pinctrl-names = "default"; 231 pinctrl-0 = <&cam_clkout0>; 232 reset-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>; 233 pwdn-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; 234 /*power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;*/ 235 rockchip,camera-module-index = <0>; 236 rockchip,camera-module-facing = "back"; 237 rockchip,camera-module-name = "TongJu"; 238 rockchip,camera-module-lens-name = "CHT842-MD"; 239 port { 240 ov5695_out: endpoint { 241 remote-endpoint = <&mipi_in_ucam0>; 242 data-lanes = <1 2>; 243 }; 244 }; 245 }; 246 247 gc8034: gc8034@37 { 248 compatible = "galaxycore,gc8034"; 249 status = "okay"; 250 reg = <0x37>; 251 clocks = <&cru CLK_CAM0_OUT>; 252 clock-names = "xvclk"; 253 power-domains = <&power RK3568_PD_VI>; 254 pinctrl-names = "default"; 255 pinctrl-0 = <&cam_clkout0>; 256 reset-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_LOW>; 257 pwdn-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; 258 rockchip,camera-module-index = <0>; 259 rockchip,camera-module-facing = "back"; 260 rockchip,camera-module-name = "RK-CMK-8M-2-v1"; 261 rockchip,camera-module-lens-name = "CK8401"; 262 port { 263 gc8034_out: endpoint { 264 remote-endpoint = <&mipi_in_ucam1>; 265 data-lanes = <1 2 3 4>; 266 }; 267 }; 268 }; 269 270}; 271 272&i2s1_8ch { 273 status = "disabled"; 274}; 275 276&i2s2_2ch { 277 pinctrl-0 = <&i2s2m0_sclktx &i2s2m0_lrcktx &i2s2m0_sdi &i2s2m0_sdo>; 278 rockchip,bclk-fs = <32>; 279 status = "disabled"; 280}; 281 282&i2s3_2ch { 283 status = "okay"; 284 pinctrl-names = "default"; 285 rockchip,clk-trcm = <1>; 286 pinctrl-0 = <&i2s3m1_sclk 287 &i2s3m1_lrck 288 &i2s3m1_sdi 289 &i2s3m1_sdo>; 290}; 291 292&mdio1 { 293 rgmii_phy1: phy@0 { 294 compatible = "ethernet-phy-ieee802.3-c22"; 295 reg = <0x0>; 296 }; 297}; 298 299&video_phy0 { 300 status = "okay"; 301}; 302 303&video_phy1 { 304 status = "disabled"; 305}; 306 307&pdm { 308 status = "disabled"; 309 pinctrl-names = "default"; 310 pinctrl-0 = <&pdmm1_clk1 311 &pdmm1_sdi1 312 &pdmm1_sdi2 313 &pdmm1_sdi3>; 314}; 315 316&pdmics { 317 status = "disabled"; 318}; 319 320&pdm_mic_array { 321 status = "disabled"; 322}; 323 324&pinctrl { 325 cam { 326 camera_pwr: camera-pwr { 327 rockchip,pins = 328 /* camera power en */ 329 <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; 330 }; 331 }; 332 333 headphone { 334 hp_det: hp-det { 335 rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; 336 }; 337 }; 338 339 lcd0 { 340 lcd0_rst_gpio: lcd-rst-gpio { 341 rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 342 }; 343 }; 344 345 lcd1 { 346 lcd1_rst_gpio: lcd1-rst-gpio { 347 rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 348 }; 349 }; 350 351 sdio-pwrseq { 352 wifi_enable_h: wifi-enable-h { 353 rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 354 }; 355 }; 356 357 wireless-wlan { 358 wifi_host_wake_irq: wifi-host-wake-irq { 359 rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; 360 }; 361 }; 362 363 wireless-bluetooth { 364 uart1_gpios: uart1-gpios { 365 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 366 }; 367 }; 368}; 369 370&rkcif { 371 status = "okay"; 372}; 373 374&rkcif_dvp { 375 status = "okay"; 376 377 port { 378 /* Parallel bus endpoint */ 379 dvp_in_bcam: endpoint { 380 remote-endpoint = <&gc2145_out>; 381 bus-width = <8>; 382 vsync-active = <0>; 383 hsync-active = <1>; 384 }; 385 }; 386}; 387 388&rkisp { 389 status = "okay"; 390}; 391 392&rkisp_mmu { 393 status = "okay"; 394}; 395 396&rkisp_vir0 { 397 status = "okay"; 398 399 port { 400 #address-cells = <1>; 401 #size-cells = <0>; 402 403 isp0_in: endpoint@0 { 404 reg = <0>; 405 remote-endpoint = <&csidphy_out>; 406 }; 407 }; 408}; 409 410&rk809_codec { 411 compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; 412 clocks = <&cru I2S3_MCLKOUT>; 413 clock-names = "mclk"; 414 assigned-clocks = <&cru I2S3_MCLKOUT>, <&cru I2S3_MCLK_IOE>; 415 assigned-clock-rates = <12288000>; 416 assigned-clock-parents = <&cru I2S3_MCLKOUT_TX>, <&cru I2S3_MCLKOUT>; 417 pinctrl-names = "default"; 418 pinctrl-0 = <&i2s3m1_mclk>; 419 hp-volume = <20>; 420 spk-volume = <3>; 421 mic-in-differential; 422 status = "okay"; 423}; 424 425&rk809_sound { 426 status = "okay"; 427 compatible = "simple-audio-card"; 428 simple-audio-card,format = "i2s"; 429 simple-audio-card,name = "rockchip,rk809-codec"; 430 simple-audio-card,mclk-fs = <256>; 431 432 simple-audio-card,cpu { 433 sound-dai = <&i2s3_2ch>; 434 }; 435 simple-audio-card,codec { 436 sound-dai = <&rk809_codec 0>; 437 }; 438}; 439 440&route_dsi0 { 441 status = "okay"; 442 connect = <&vp1_out_dsi0>; 443}; 444 445&sata1 { 446 status = "okay"; 447}; 448 449&sdio_pwrseq { 450 reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; 451}; 452 453&sdmmc1 { 454 max-frequency = <150000000>; 455 no-sd; 456 no-mmc; 457 bus-width = <4>; 458 disable-wp; 459 cap-sd-highspeed; 460 cap-sdio-irq; 461 keep-power-in-suspend; 462 mmc-pwrseq = <&sdio_pwrseq>; 463 non-removable; 464 pinctrl-names = "default"; 465 pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; 466 sd-uhs-sdr104; 467 status = "okay"; 468}; 469 470&sdmmc2 { 471 status = "disabled"; 472}; 473 474&spdif_8ch { 475 status = "disabled"; 476}; 477 478&uart1 { 479 status = "okay"; 480 pinctrl-names = "default"; 481 pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; 482}; 483 484&vcc3v3_lcd0_n { 485 gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; 486 enable-active-high; 487}; 488 489&wireless_bluetooth { 490 compatible = "bluetooth-platdata"; 491 clocks = <&rk809 1>; 492 clock-names = "ext_clock"; 493 //wifi-bt-power-toggle; 494 uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; 495 pinctrl-names = "default", "rts_gpio"; 496 pinctrl-0 = <&uart1m0_rtsn>; 497 pinctrl-1 = <&uart1_gpios>; 498 BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; 499 BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; 500 BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; 501 status = "okay"; 502}; 503 504&wireless_wlan { 505 pinctrl-names = "default"; 506 pinctrl-0 = <&wifi_host_wake_irq>; 507 WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; 508 WIFI,poweren_gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; 509}; 510 511&work_led { 512 gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; 513}; 514