1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/pinctrl/rockchip.h> 10#include "rk3566.dtsi" 11#include "rk3566-evb.dtsi" 12 13/ { 14 model = "Rockchip RK3566 EVB1 DDR4 V10 Board"; 15 compatible = "rockchip,rk3566-evb1-ddr4-v10", "rockchip,rk3566"; 16 17 vcc3v3_pcie: gpio-regulator { 18 compatible = "regulator-fixed"; 19 regulator-name = "vcc3v3_pcie"; 20 regulator-min-microvolt = <3300000>; 21 regulator-max-microvolt = <3300000>; 22 enable-active-high; 23 gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; 24 startup-delay-us = <5000>; 25 vin-supply = <&dc_12v>; 26 }; 27 28 vcc3v3_vga: vcc3v3-vga { 29 compatible = "regulator-fixed"; 30 regulator-name = "vcc3v3_vga"; 31 regulator-always-on; 32 regulator-boot-on; 33 gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; 34 enable-active-high; 35 vin-supply = <&vcc3v3_sys>; 36 }; 37 38 vcc_camera: vcc-camera-regulator { 39 compatible = "regulator-fixed"; 40 gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; 41 pinctrl-names = "default"; 42 pinctrl-0 = <&camera_pwr>; 43 regulator-name = "vcc_camera"; 44 enable-active-high; 45 regulator-always-on; 46 regulator-boot-on; 47 }; 48}; 49 50&bt_sound { 51 status = "disabled"; 52 simple-audio-card,cpu { 53 sound-dai = <&i2s2_2ch>; 54 }; 55}; 56 57&audiopwmout_diff { 58 status = "disabled"; 59}; 60 61&combphy1_usq { 62 status = "okay"; 63}; 64 65&combphy2_psq { 66 status = "okay"; 67}; 68 69&csi2_dphy_hw { 70 status = "okay"; 71}; 72 73&csi2_dphy1 { 74 status = "okay"; 75 76 /* 77 * dphy1 only used for split mode, 78 * can be used concurrently with dphy2 79 * full mode and split mode are mutually exclusive 80 */ 81 ports { 82 #address-cells = <1>; 83 #size-cells = <0>; 84 85 port@0 { 86 reg = <0>; 87 #address-cells = <1>; 88 #size-cells = <0>; 89 90 dphy1_in: endpoint@1 { 91 reg = <1>; 92 remote-endpoint = <&ov5695_out>; 93 data-lanes = <1 2>; 94 }; 95 }; 96 97 port@1 { 98 reg = <1>; 99 #address-cells = <1>; 100 #size-cells = <0>; 101 102 dphy1_out: endpoint@1 { 103 reg = <1>; 104 remote-endpoint = <&isp0_in>; 105 }; 106 }; 107 }; 108}; 109 110&csi2_dphy2 { 111 status = "okay"; 112 113 /* 114 * dphy2 only used for split mode, 115 * can be used concurrently with dphy1 116 * full mode and split mode are mutually exclusive 117 */ 118 ports { 119 #address-cells = <1>; 120 #size-cells = <0>; 121 122 port@0 { 123 reg = <0>; 124 #address-cells = <1>; 125 #size-cells = <0>; 126 127 dphy2_in: endpoint@1 { 128 reg = <1>; 129 remote-endpoint = <&ov02k10_out>; 130 data-lanes = <1 2>; 131 }; 132 }; 133 134 port@1 { 135 reg = <1>; 136 #address-cells = <1>; 137 #size-cells = <0>; 138 139 dphy2_out: endpoint@1 { 140 reg = <1>; 141 remote-endpoint = <&mipi_csi2_input>; 142 }; 143 }; 144 }; 145}; 146 147&dig_acodec { 148 status = "disabled"; 149 rockchip,pwm-output-mode; 150 pinctrl-names = "default"; 151 pinctrl-0 = <&audiopwm_loutp 152 &audiopwm_loutn 153 &audiopwm_routp 154 &audiopwm_routn 155 >; 156}; 157 158/* 159 * video_phy0 needs to be enabled 160 * when dsi0 is enabled 161 */ 162&dsi0 { 163 status = "okay"; 164}; 165 166&dsi0_in_vp0 { 167 status = "disabled"; 168}; 169 170&dsi0_in_vp1 { 171 status = "okay"; 172}; 173 174&dsi0_panel { 175 power-supply = <&vcc3v3_lcd0_n>; 176 reset-gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_LOW>; 177 pinctrl-names = "default"; 178 pinctrl-0 = <&lcd0_rst_gpio>; 179}; 180 181/* 182 * video_phy1 needs to be enabled 183 * when dsi1 is enabled 184 */ 185&dsi1 { 186 status = "disabled"; 187}; 188 189&dsi1_in_vp0 { 190 status = "disabled"; 191}; 192 193&dsi1_in_vp1 { 194 status = "disabled"; 195}; 196 197&dsi1_panel { 198 power-supply = <&vcc3v3_lcd1_n>; 199 reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; 200 pinctrl-names = "default"; 201 pinctrl-0 = <&lcd1_rst_gpio>; 202}; 203 204&edp { 205 hpd-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; 206 status = "okay"; 207}; 208 209&edp_phy { 210 status = "okay"; 211}; 212 213&edp_in_vp0 { 214 status = "okay"; 215}; 216 217&edp_in_vp1 { 218 status = "disabled"; 219}; 220 221/* 222 * power-supply should switche to vcc3v3_lcd1_n 223 * when mipi panel is connected to dsi1. 224 */ 225>1x { 226 power-supply = <&vcc3v3_lcd0_n>; 227}; 228 229&i2c2 { 230 status = "okay"; 231 pinctrl-names = "default"; 232 pinctrl-0 = <&i2c2m1_xfer>; 233 234 /* split mode: lane0/1 */ 235 ov5695: ov5695@36 { 236 status = "okay"; 237 compatible = "ovti,ov5695"; 238 reg = <0x36>; 239 clocks = <&cru CLK_CAM0_OUT>; 240 clock-names = "xvclk"; 241 power-domains = <&power RK3568_PD_VI>; 242 pinctrl-names = "default"; 243 pinctrl-0 = <&cam_clkout0>; 244 reset-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>; 245 pwdn-gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; 246 /*power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;*/ 247 rockchip,camera-module-index = <0>; 248 rockchip,camera-module-facing = "back"; 249 rockchip,camera-module-name = "TongJu"; 250 rockchip,camera-module-lens-name = "CHT842-MD"; 251 port { 252 ov5695_out: endpoint { 253 remote-endpoint = <&dphy1_in>; 254 data-lanes = <1 2>; 255 }; 256 }; 257 }; 258 259 ov02k10: ov02k10@36 { 260 status = "okay"; 261 compatible = "ovti,ov02k10"; 262 reg = <0x36>; 263 clocks = <&cru CLK_CAM1_OUT>; 264 clock-names = "xvclk"; 265 pinctrl-names = "default"; 266 pinctrl-0 = <&cam_clkout1>; 267 reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; 268 pwdn-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; 269 power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; 270 rockchip,camera-module-index = <0>; 271 rockchip,camera-module-facing = "back"; 272 rockchip,camera-module-name = "TongJu"; 273 rockchip,camera-module-lens-name = "CHT842-MD"; 274 port { 275 ov02k10_out: endpoint { 276 remote-endpoint = <&dphy2_in>; 277 data-lanes = <1 2>; 278 }; 279 }; 280 }; 281}; 282 283&i2s2_2ch { 284 pinctrl-0 = <&i2s2m1_sclktx &i2s2m1_lrcktx &i2s2m1_sdi &i2s2m1_sdo>; 285 rockchip,bclk-fs = <32>; 286 status = "disabled"; 287}; 288 289&i2s3_2ch { 290 status = "disabled"; 291}; 292 293&mipi_csi2 { 294 status = "okay"; 295 296 ports { 297 #address-cells = <1>; 298 #size-cells = <0>; 299 300 port@0 { 301 reg = <0>; 302 #address-cells = <1>; 303 #size-cells = <0>; 304 305 mipi_csi2_input: endpoint@1 { 306 reg = <1>; 307 remote-endpoint = <&dphy2_out>; 308 data-lanes = <1 2>; 309 }; 310 }; 311 312 port@1 { 313 reg = <1>; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 317 mipi_csi2_output: endpoint@0 { 318 reg = <0>; 319 remote-endpoint = <&cif_mipi_in>; 320 data-lanes = <1 2>; 321 }; 322 }; 323 }; 324}; 325 326&video_phy0 { 327 status = "okay"; 328}; 329 330&video_phy1 { 331 status = "disabled"; 332}; 333 334&pcie2x1 { 335 reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; 336 vpcie3v3-supply = <&vcc3v3_pcie>; 337 status = "okay"; 338}; 339 340&pdm { 341 status = "disabled"; 342 pinctrl-names = "default"; 343 pinctrl-0 = <&pdmm1_clk1 344 &pdmm1_sdi1 345 &pdmm1_sdi2 346 &pdmm1_sdi3>; 347}; 348 349&pdmics { 350 status = "disabled"; 351}; 352 353&pdm_mic_array { 354 status = "disabled"; 355}; 356 357&rkcif { 358 status = "okay"; 359}; 360 361&rkcif_mipi_lvds { 362 status = "okay"; 363 364 port { 365 cif_mipi_in: endpoint { 366 remote-endpoint = <&mipi_csi2_output>; 367 data-lanes = <1 2>; 368 }; 369 }; 370}; 371 372&rkcif_mmu { 373 status = "okay"; 374}; 375 376&rkisp { 377 status = "okay"; 378}; 379 380&rkisp_mmu { 381 status = "okay"; 382}; 383 384&rkisp_vir0 { 385 status = "okay"; 386 387 port { 388 #address-cells = <1>; 389 #size-cells = <0>; 390 391 isp0_in: endpoint@0 { 392 reg = <0>; 393 remote-endpoint = <&dphy1_out>; 394 }; 395 }; 396}; 397 398&route_dsi0 { 399 status = "okay"; 400 connect = <&vp1_out_dsi0>; 401}; 402 403&sdmmc2 { 404 max-frequency = <150000000>; 405 no-sd; 406 no-mmc; 407 bus-width = <4>; 408 disable-wp; 409 cap-sd-highspeed; 410 cap-sdio-irq; 411 keep-power-in-suspend; 412 mmc-pwrseq = <&sdio_pwrseq>; 413 non-removable; 414 pinctrl-names = "default"; 415 pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; 416 sd-uhs-sdr104; 417 status = "okay"; 418}; 419 420&uart1 { 421 status = "okay"; 422 pinctrl-names = "default"; 423 pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn>; 424}; 425 426&vcc3v3_lcd0_n { 427 gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; 428 enable-active-high; 429}; 430 431&vcc3v3_lcd1_n { 432 gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; 433 enable-active-high; 434}; 435 436&wireless_bluetooth { 437 uart_rts_gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; 438 pinctrl-names = "default", "rts_gpio"; 439 pinctrl-0 = <&uart1m1_rtsn>; 440 pinctrl-1 = <&uart1_gpios>; 441 BT,reset_gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; 442 BT,wake_gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; 443 BT,wake_host_irq = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; 444 status = "okay"; 445}; 446 447&wireless_wlan { 448 pinctrl-names = "default"; 449 pinctrl-0 = <&wifi_host_wake_irq>; 450 WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; 451}; 452 453&work_led { 454 gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; 455}; 456 457&pinctrl { 458 cam { 459 camera_pwr: camera-pwr { 460 rockchip,pins = 461 /* camera power en */ 462 <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; 463 }; 464 }; 465 466 lcd0 { 467 lcd0_rst_gpio: lcd0-rst-gpio { 468 rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; 469 }; 470 }; 471 472 lcd1 { 473 lcd1_rst_gpio: lcd1-rst-gpio { 474 rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 475 }; 476 }; 477 478 wireless-wlan { 479 wifi_host_wake_irq: wifi-host-wake-irq { 480 rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; 481 }; 482 }; 483 484 wireless-bluetooth { 485 uart1_gpios: uart1-gpios { 486 rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; 487 }; 488 }; 489}; 490