1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7#include "rk3562-evb2-ddr4-v10.dtsi" 8#include "rk3562-android.dtsi" 9#include "rk3562-rk809.dtsi" 10 11/ { 12 vcc_mipicsi0: vcc-mipicsi0-regulator { 13 compatible = "regulator-fixed"; 14 gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; 15 pinctrl-names = "default"; 16 pinctrl-0 = <&mipicsi0_pwr>; 17 regulator-name = "vcc_mipicsi0"; 18 enable-active-high; 19 regulator-always-on; 20 regulator-boot-on; 21 }; 22}; 23 24&csi2_dphy1 { 25 status = "okay"; 26 27 ports { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 port@0 { 31 reg = <0>; 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 mipi_in_ucam0: endpoint@1 { 36 reg = <1>; 37 remote-endpoint = <&gc8034_out0>; 38 data-lanes = <1 2>; 39 }; 40 }; 41 port@1 { 42 reg = <1>; 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 csidphy1_out: endpoint@0 { 47 reg = <0>; 48 remote-endpoint = <&mipi0_csi2_input>; 49 }; 50 }; 51 }; 52}; 53 54&csi2_dphy2 { 55 status = "okay"; 56 57 ports { 58 #address-cells = <1>; 59 #size-cells = <0>; 60 port@0 { 61 reg = <0>; 62 #address-cells = <1>; 63 #size-cells = <0>; 64 65 mipi_in_ucam1: endpoint@1 { 66 reg = <1>; 67 remote-endpoint = <&ov5695_out0>; 68 data-lanes = <1 2>; 69 }; 70 }; 71 port@1 { 72 reg = <1>; 73 #address-cells = <1>; 74 #size-cells = <0>; 75 76 csidphy2_out: endpoint@0 { 77 reg = <0>; 78 remote-endpoint = <&mipi1_csi2_input>; 79 }; 80 }; 81 }; 82}; 83 84&i2c4 { 85 status = "okay"; 86 87 dw9714: dw9714@c { 88 compatible = "dongwoon,dw9714"; 89 status = "okay"; 90 reg = <0x0c>; 91 rockchip,vcm-start-current = <10>; 92 rockchip,vcm-rated-current = <85>; 93 rockchip,vcm-step-mode = <5>; 94 rockchip,camera-module-index = <0>; 95 rockchip,camera-module-facing = "back"; 96 }; 97 98 gc8034: gc8034@37 { 99 compatible = "galaxycore,gc8034"; 100 reg = <0x37>; 101 clocks = <&cru CLK_CAM0_OUT2IO>; 102 clock-names = "xvclk"; 103 pinctrl-names = "default"; 104 pinctrl-0 = <&camm0_clk0_out>; 105 reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; 106 pwdn-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; 107 // dvdd-supply = <&vcc_mipicsi0>; 108 rockchip,camera-module-index = <0>; 109 rockchip,camera-module-facing = "back"; 110 rockchip,camera-module-name = "RK-CMK-8M-2-v1"; 111 rockchip,camera-module-lens-name = "CK8401"; 112 lens-focus = <&dw9714>; 113 port { 114 gc8034_out0: endpoint { 115 remote-endpoint = <&mipi_in_ucam0>; 116 data-lanes = <1 2>; 117 }; 118 }; 119 }; 120 121 ov5695: ov5695@36 { 122 compatible = "ovti,ov5695"; 123 reg = <0x36>; 124 clocks = <&cru CLK_CAM1_OUT2IO>; 125 clock-names = "xvclk"; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&camm0_clk1_out>; 128 reset-gpios = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>; 129 pwdn-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; 130 // dvdd-supply = <&vcc_mipicsi2>; 131 rockchip,camera-module-index = <1>; 132 rockchip,camera-module-facing = "front"; 133 rockchip,camera-module-name = "TongJu"; 134 rockchip,camera-module-lens-name = "CHT842-MD"; 135 port { 136 ov5695_out0: endpoint { 137 remote-endpoint = <&mipi_in_ucam1>; 138 data-lanes = <1 2>; 139 }; 140 }; 141 }; 142}; 143 144&csi2_dphy0_hw { 145 status = "okay"; 146}; 147 148&mipi0_csi2 { 149 status = "okay"; 150 151 ports { 152 #address-cells = <1>; 153 #size-cells = <0>; 154 155 port@0 { 156 reg = <0>; 157 #address-cells = <1>; 158 #size-cells = <0>; 159 160 mipi0_csi2_input: endpoint@1 { 161 reg = <1>; 162 remote-endpoint = <&csidphy1_out>; 163 }; 164 }; 165 166 port@1 { 167 reg = <1>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 171 mipi0_csi2_output: endpoint@0 { 172 reg = <0>; 173 remote-endpoint = <&cif_mipi_in0>; 174 }; 175 }; 176 }; 177}; 178 179&mipi1_csi2 { 180 status = "okay"; 181 182 ports { 183 #address-cells = <1>; 184 #size-cells = <0>; 185 186 port@0 { 187 reg = <0>; 188 #address-cells = <1>; 189 #size-cells = <0>; 190 191 mipi1_csi2_input: endpoint@1 { 192 reg = <1>; 193 remote-endpoint = <&csidphy2_out>; 194 }; 195 }; 196 197 port@1 { 198 reg = <1>; 199 #address-cells = <1>; 200 #size-cells = <0>; 201 202 mipi1_csi2_output: endpoint@0 { 203 reg = <0>; 204 remote-endpoint = <&cif_mipi_in1>; 205 }; 206 }; 207 }; 208}; 209 210&rkcif { 211 status = "okay"; 212}; 213 214&rkcif_mipi_lvds { 215 status = "okay"; 216 217 port { 218 cif_mipi_in0: endpoint { 219 remote-endpoint = <&mipi0_csi2_output>; 220 }; 221 }; 222}; 223 224&rkcif_mipi_lvds1 { 225 status = "okay"; 226 227 port { 228 cif_mipi_in1: endpoint { 229 remote-endpoint = <&mipi1_csi2_output>; 230 }; 231 }; 232}; 233 234&rkcif_mipi_lvds_sditf { 235 status = "okay"; 236 237 port { 238 mipi_lvds_sditf: endpoint { 239 remote-endpoint = <&isp_vir0>; 240 }; 241 }; 242}; 243 244&rkcif_mipi_lvds1_sditf { 245 status = "okay"; 246 247 port { 248 mipi_lvds1_sditf: endpoint { 249 remote-endpoint = <&isp_vir1>; 250 }; 251 }; 252}; 253 254&rkcif_mmu { 255 status = "okay"; 256}; 257 258&rkisp { 259 status = "okay"; 260}; 261 262&rkisp_mmu { 263 status = "okay"; 264}; 265 266&rkisp_vir0 { 267 status = "okay"; 268 269 port { 270 #address-cells = <1>; 271 #size-cells = <0>; 272 273 isp_vir0: endpoint@0 { 274 reg = <0>; 275 remote-endpoint = <&mipi_lvds_sditf>; 276 }; 277 }; 278}; 279 280&rkisp_vir1 { 281 status = "okay"; 282 283 port { 284 #address-cells = <1>; 285 #size-cells = <0>; 286 287 isp_vir1: endpoint@1 { 288 reg = <1>; 289 remote-endpoint = <&mipi_lvds1_sditf>; 290 }; 291 }; 292}; 293 294&pinctrl { 295 cam { 296 mipicsi0_pwr: mipicsi0-pwr { 297 rockchip,pins = 298 /* camera power en */ 299 <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; 300 }; 301 }; 302}; 303 304