1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 */ 5 6/ { 7 rockchip_amp: rockchip-amp { 8 compatible = "rockchip,mcu-amp"; 9 clocks = <&cru FCLK_BUS_CM0_CORE>, <&cru CLK_BUS_CM0_RTC>, 10 <&cru PCLK_MAILBOX>, <&cru PCLK_INTC>, 11 <&cru SCLK_UART7>, <&cru PCLK_UART7>, 12 <&cru PCLK_TIMER>, <&cru CLK_TIMER4>, <&cru CLK_TIMER5>; 13 14 pinctrl-names = "default"; 15 pinctrl-0 = <&uart7m1_xfer>; 16 17 status = "okay"; 18 }; 19 20 rpmsg: rpmsg@a0000000 { 21 compatible = "rockchip,rk3562-rpmsg"; 22 mbox-names = "rpmsg-rx", "rpmsg-tx"; 23 mboxes = <&mailbox 0 &mailbox 3>; 24 rockchip,vdev-nums = <1>; 25 rockchip,link-id = <0x04>; 26 reg = <0x0 0xa0000000 0x0 0x20000>; 27 memory-region = <&rpmsg_dma_reserved>; 28 29 status = "okay"; 30 }; 31 32 reserved-memory { 33 #address-cells = <2>; 34 #size-cells = <2>; 35 ranges; 36 37 /* mcu address */ 38 mcu_reserved: mcu@8200000 { 39 reg = <0x0 0x8200000 0x0 0x100000>; 40 no-map; 41 }; 42 43 rpmsg_reserved: rpmsg@a0000000 { 44 reg = <0x0 0xa0000000 0x0 0x400000>; 45 no-map; 46 }; 47 48 rpmsg_dma_reserved: rpmsg-dma@a0400000 { 49 compatible = "shared-dma-pool"; 50 reg = <0x0 0xa0400000 0x0 0x100000>; 51 no-map; 52 }; 53 }; 54}; 55 56&mailbox { 57 status = "okay"; 58}; 59