xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3399-evb-ind-lpddr4-linux.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2019-2020 Fuzhou Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/dts-v1/;
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun#include "rk3399-evb-ind.dtsi"
9*4882a593Smuzhiyun#include "rk3399-linux.dtsi"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/ {
12*4882a593Smuzhiyun	model = "Rockchip RK3399 EVB IND LPDDR4 Board edp (Linux)";
13*4882a593Smuzhiyun	compatible = "rockchip,linux", "rockchip,rk3399-evb-ind-lpddr4-linux", "rockchip,rk3399";
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun	iram: sram@ff8d0000 {
16*4882a593Smuzhiyun		compatible = "mmio-sram";
17*4882a593Smuzhiyun		reg = <0x0 0xff8d0000 0x0 0x20000>;
18*4882a593Smuzhiyun	};
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun	hub_reset: hub-reset {
21*4882a593Smuzhiyun		compatible = "regulator-fixed";
22*4882a593Smuzhiyun		enable-active-high;
23*4882a593Smuzhiyun		gpio = <&gpio4 18 GPIO_ACTIVE_HIGH>;
24*4882a593Smuzhiyun		regulator-name = "hub_reset";
25*4882a593Smuzhiyun		regulator-always-on;
26*4882a593Smuzhiyun		regulator-boot-on;
27*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
28*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
29*4882a593Smuzhiyun	};
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun	vcc_lcd: vcc-lcd {
32*4882a593Smuzhiyun		compatible = "regulator-fixed";
33*4882a593Smuzhiyun		regulator-name = "vcc_lcd";
34*4882a593Smuzhiyun		startup-delay-us = <20000>;
35*4882a593Smuzhiyun		enable-active-high;
36*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
37*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
38*4882a593Smuzhiyun		regulator-boot-on;
39*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
40*4882a593Smuzhiyun	};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun	panel: panel {
43*4882a593Smuzhiyun		compatible = "simple-panel";
44*4882a593Smuzhiyun		backlight = <&backlight>;
45*4882a593Smuzhiyun		power-supply = <&vcc_lcd>;
46*4882a593Smuzhiyun		reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
47*4882a593Smuzhiyun		prepare-delay-ms = <20>;
48*4882a593Smuzhiyun		enable-delay-ms = <20>;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun		display-timings {
51*4882a593Smuzhiyun			native-mode = <&timing0>;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun			timing0: timing0 {
54*4882a593Smuzhiyun				clock-frequency = <200000000>;
55*4882a593Smuzhiyun				hactive = <1536>;
56*4882a593Smuzhiyun				vactive = <2048>;
57*4882a593Smuzhiyun				hfront-porch = <12>;
58*4882a593Smuzhiyun				hsync-len = <16>;
59*4882a593Smuzhiyun				hback-porch = <48>;
60*4882a593Smuzhiyun				vfront-porch = <8>;
61*4882a593Smuzhiyun				vsync-len = <4>;
62*4882a593Smuzhiyun				vback-porch = <8>;
63*4882a593Smuzhiyun				hsync-active = <0>;
64*4882a593Smuzhiyun				vsync-active = <0>;
65*4882a593Smuzhiyun				de-active = <0>;
66*4882a593Smuzhiyun				pixelclk-active = <0>;
67*4882a593Smuzhiyun			};
68*4882a593Smuzhiyun		};
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun		ports {
71*4882a593Smuzhiyun			panel_in: endpoint {
72*4882a593Smuzhiyun				remote-endpoint = <&edp_out>;
73*4882a593Smuzhiyun			};
74*4882a593Smuzhiyun		};
75*4882a593Smuzhiyun	};
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun	test-power {
78*4882a593Smuzhiyun		status = "okay";
79*4882a593Smuzhiyun	};
80*4882a593Smuzhiyun};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun&backlight {
83*4882a593Smuzhiyun	enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
84*4882a593Smuzhiyun};
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun&display_subsystem {
87*4882a593Smuzhiyun	status = "okay";
88*4882a593Smuzhiyun};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun&dmac_bus {
91*4882a593Smuzhiyun	iram = <&iram>;
92*4882a593Smuzhiyun	rockchip,force-iram;
93*4882a593Smuzhiyun};
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun&dp_sound {
96*4882a593Smuzhiyun	status = "disabled";
97*4882a593Smuzhiyun};
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun&edp {
100*4882a593Smuzhiyun	status = "okay";
101*4882a593Smuzhiyun	force-hpd;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun	ports {
104*4882a593Smuzhiyun		port@1 {
105*4882a593Smuzhiyun			reg = <1>;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun			edp_out: endpoint {
108*4882a593Smuzhiyun				remote-endpoint = <&panel_in>;
109*4882a593Smuzhiyun			};
110*4882a593Smuzhiyun		};
111*4882a593Smuzhiyun	};
112*4882a593Smuzhiyun};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun&edp_in_vopb {
115*4882a593Smuzhiyun	status = "disabled";
116*4882a593Smuzhiyun};
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun&hdmi {
119*4882a593Smuzhiyun	pinctrl-names = "default";
120*4882a593Smuzhiyun	pinctrl-0 = <&hdmi_i2c_xfer>, <&hdmi_cec>;
121*4882a593Smuzhiyun	#address-cells = <1>;
122*4882a593Smuzhiyun	#size-cells = <0>;
123*4882a593Smuzhiyun	#sound-dai-cells = <0>;
124*4882a593Smuzhiyun	status = "okay";
125*4882a593Smuzhiyun};
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun&hdmi_in_vopl {
128*4882a593Smuzhiyun	status = "disabled";
129*4882a593Smuzhiyun};
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun&hdmi_sound {
132*4882a593Smuzhiyun	status = "okay";
133*4882a593Smuzhiyun};
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun&i2c1 {
136*4882a593Smuzhiyun	status = "okay";
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun	vm149c: vm149c@0c {
139*4882a593Smuzhiyun		compatible = "silicon touch,vm149c";
140*4882a593Smuzhiyun		status = "okay";
141*4882a593Smuzhiyun		reg = <0x0c>;
142*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
143*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
144*4882a593Smuzhiyun	};
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun	ov13850: ov13850@10 {
147*4882a593Smuzhiyun		compatible = "ovti,ov13850";
148*4882a593Smuzhiyun		status = "okay";
149*4882a593Smuzhiyun		reg = <0x10>;
150*4882a593Smuzhiyun		clocks = <&cru SCLK_CIF_OUT>;
151*4882a593Smuzhiyun		clock-names = "xvclk";
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun		/* conflict with csi-ctl-gpios */
154*4882a593Smuzhiyun		reset-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
155*4882a593Smuzhiyun		pwdn-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
156*4882a593Smuzhiyun		pinctrl-names = "rockchip,camera_default";
157*4882a593Smuzhiyun		pinctrl-0 = <&cif_clkout>;
158*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
159*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
160*4882a593Smuzhiyun		rockchip,camera-module-name = "CMK-CT0116";
161*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "Largan-50013A1";
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun		lens-focus = <&vm149c>;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun		port {
166*4882a593Smuzhiyun			ucam_out0: endpoint {
167*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam0>;
168*4882a593Smuzhiyun				data-lanes = <1 2>;
169*4882a593Smuzhiyun			};
170*4882a593Smuzhiyun		};
171*4882a593Smuzhiyun	};
172*4882a593Smuzhiyun};
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun&i2s0 {
175*4882a593Smuzhiyun	#sound-dai-cells = <0>;
176*4882a593Smuzhiyun	status = "okay";
177*4882a593Smuzhiyun};
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun&i2s1 {
180*4882a593Smuzhiyun	#sound-dai-cells = <0>;
181*4882a593Smuzhiyun	status = "okay";
182*4882a593Smuzhiyun};
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun&i2s2 {
185*4882a593Smuzhiyun	#sound-dai-cells = <0>;
186*4882a593Smuzhiyun	status = "okay";
187*4882a593Smuzhiyun};
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun&mipi_dphy_rx0 {
190*4882a593Smuzhiyun	status = "okay";
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun	ports {
193*4882a593Smuzhiyun		#address-cells = <1>;
194*4882a593Smuzhiyun		#size-cells = <0>;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun		port@0 {
197*4882a593Smuzhiyun			reg = <0>;
198*4882a593Smuzhiyun			#address-cells = <1>;
199*4882a593Smuzhiyun			#size-cells = <0>;
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun			mipi_in_ucam0: endpoint@1 {
202*4882a593Smuzhiyun				reg = <1>;
203*4882a593Smuzhiyun				remote-endpoint = <&ucam_out0>;
204*4882a593Smuzhiyun				data-lanes = <1 2>;
205*4882a593Smuzhiyun			};
206*4882a593Smuzhiyun		};
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun		port@1 {
209*4882a593Smuzhiyun			reg = <1>;
210*4882a593Smuzhiyun			#address-cells = <1>;
211*4882a593Smuzhiyun			#size-cells = <0>;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun			dphy_rx0_out: endpoint@0 {
214*4882a593Smuzhiyun				reg = <0>;
215*4882a593Smuzhiyun				remote-endpoint = <&isp0_mipi_in>;
216*4882a593Smuzhiyun			};
217*4882a593Smuzhiyun		};
218*4882a593Smuzhiyun	};
219*4882a593Smuzhiyun};
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun&mipi_dphy_tx1rx1 {
222*4882a593Smuzhiyun	status = "okay";
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun	ports {
225*4882a593Smuzhiyun		#address-cells = <1>;
226*4882a593Smuzhiyun		#size-cells = <0>;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun		port@0 {
229*4882a593Smuzhiyun			reg = <0>;
230*4882a593Smuzhiyun			#address-cells = <1>;
231*4882a593Smuzhiyun			#size-cells = <0>;
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun			mipi_in_ucam1: endpoint@1 {
234*4882a593Smuzhiyun				reg = <1>;
235*4882a593Smuzhiyun				/* Unlinked camera */
236*4882a593Smuzhiyun				//remote-endpoint = <&ucam_out1>;
237*4882a593Smuzhiyun				data-lanes = <1 2>;
238*4882a593Smuzhiyun			};
239*4882a593Smuzhiyun		};
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun		port@1 {
242*4882a593Smuzhiyun			reg = <1>;
243*4882a593Smuzhiyun			#address-cells = <1>;
244*4882a593Smuzhiyun			#size-cells = <0>;
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun			dphy_tx1rx1_out: endpoint@0 {
247*4882a593Smuzhiyun				reg = <0>;
248*4882a593Smuzhiyun				remote-endpoint = <&isp1_mipi_in>;
249*4882a593Smuzhiyun			};
250*4882a593Smuzhiyun		};
251*4882a593Smuzhiyun	};
252*4882a593Smuzhiyun};
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun&rk809_sound {
255*4882a593Smuzhiyun	status = "okay";
256*4882a593Smuzhiyun};
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun&rkisp1_0 {
259*4882a593Smuzhiyun	status = "okay";
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun	port {
262*4882a593Smuzhiyun		#address-cells = <1>;
263*4882a593Smuzhiyun		#size-cells = <0>;
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun		isp0_mipi_in: endpoint@0 {
266*4882a593Smuzhiyun			reg = <0>;
267*4882a593Smuzhiyun			remote-endpoint = <&dphy_rx0_out>;
268*4882a593Smuzhiyun		};
269*4882a593Smuzhiyun	};
270*4882a593Smuzhiyun};
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun&rkisp1_1 {
273*4882a593Smuzhiyun	status = "okay";
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun	port {
276*4882a593Smuzhiyun		#address-cells = <1>;
277*4882a593Smuzhiyun		#size-cells = <0>;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun		isp1_mipi_in: endpoint@0 {
280*4882a593Smuzhiyun			reg = <0>;
281*4882a593Smuzhiyun			remote-endpoint = <&dphy_tx1rx1_out>;
282*4882a593Smuzhiyun		};
283*4882a593Smuzhiyun	};
284*4882a593Smuzhiyun};
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun&route_edp {
287*4882a593Smuzhiyun	status = "okay";
288*4882a593Smuzhiyun};
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun&route_hdmi {
291*4882a593Smuzhiyun	status = "okay";
292*4882a593Smuzhiyun	connect = <&vopb_out_hdmi>;
293*4882a593Smuzhiyun};
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun/*
296*4882a593Smuzhiyun * if enable dp_sound, should disable spdif_sound and spdif_out
297*4882a593Smuzhiyun */
298*4882a593Smuzhiyun&spdif_out {
299*4882a593Smuzhiyun	status = "disabled";
300*4882a593Smuzhiyun};
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun&spdif_sound {
303*4882a593Smuzhiyun	status = "disabled";
304*4882a593Smuzhiyun};
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun&tc358749x_sound {
307*4882a593Smuzhiyun	status = "disabled";
308*4882a593Smuzhiyun};
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun&vcca_0v9 {
311*4882a593Smuzhiyun	regulator-always-on;
312*4882a593Smuzhiyun	regulator-boot-on;
313*4882a593Smuzhiyun	regulator-min-microvolt = <900000>;
314*4882a593Smuzhiyun	regulator-max-microvolt = <900000>;
315*4882a593Smuzhiyun	regulator-name = "vcca_0v9";
316*4882a593Smuzhiyun	regulator-state-mem {
317*4882a593Smuzhiyun		regulator-on-in-suspend;
318*4882a593Smuzhiyun		regulator-suspend-microvolt = <900000>;
319*4882a593Smuzhiyun	};
320*4882a593Smuzhiyun};
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun&vcc0v9_soc {
323*4882a593Smuzhiyun	regulator-always-on;
324*4882a593Smuzhiyun	regulator-boot-on;
325*4882a593Smuzhiyun	regulator-min-microvolt = <900000>;
326*4882a593Smuzhiyun	regulator-max-microvolt = <900000>;
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun	regulator-name = "vcc0v9_soc";
329*4882a593Smuzhiyun	regulator-state-mem {
330*4882a593Smuzhiyun		regulator-off-in-suspend;
331*4882a593Smuzhiyun	};
332*4882a593Smuzhiyun};
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun&vopb {
335*4882a593Smuzhiyun	status = "okay";
336*4882a593Smuzhiyun};
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun&vopb_mmu {
339*4882a593Smuzhiyun	status = "okay";
340*4882a593Smuzhiyun};
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun&vopl {
343*4882a593Smuzhiyun	status = "okay";
344*4882a593Smuzhiyun};
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun&vopl_mmu {
347*4882a593Smuzhiyun	status = "okay";
348*4882a593Smuzhiyun};
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun&pinctrl {
351*4882a593Smuzhiyun	lcd-panel {
352*4882a593Smuzhiyun		lcd_panel_reset: lcd-panel-reset {
353*4882a593Smuzhiyun			rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
354*4882a593Smuzhiyun		};
355*4882a593Smuzhiyun	};
356*4882a593Smuzhiyun};
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun/* DON'T PUT ANYTHING BELOW HERE.  PUT IT ABOVE PINCTRL */
359*4882a593Smuzhiyun/* DON'T PUT ANYTHING BELOW HERE.  PUT IT ABOVE PINCTRL */
360*4882a593Smuzhiyun/* DON'T PUT ANYTHING BELOW HERE.  PUT IT ABOVE PINCTRL */
361*4882a593Smuzhiyun
362