1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 8*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h> 9*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 10*4882a593Smuzhiyun#include "px30-robot.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "Rockchip rk3326 evb lpddr3 v10 board for robot linux"; 14*4882a593Smuzhiyun compatible = "rockchip,rk3326-evb-lp3-v10-robot-linux", "rockchip,rk3326"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun adc-keys { 17*4882a593Smuzhiyun compatible = "adc-keys"; 18*4882a593Smuzhiyun io-channels = <&saradc 2>; 19*4882a593Smuzhiyun io-channel-names = "buttons"; 20*4882a593Smuzhiyun poll-interval = <100>; 21*4882a593Smuzhiyun keyup-threshold-microvolt = <1800000>; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun esc-key { 24*4882a593Smuzhiyun linux,code = <KEY_ESC>; 25*4882a593Smuzhiyun label = "esc"; 26*4882a593Smuzhiyun press-threshold-microvolt = <1310000>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun home-key { 30*4882a593Smuzhiyun linux,code = <KEY_HOME>; 31*4882a593Smuzhiyun label = "home"; 32*4882a593Smuzhiyun press-threshold-microvolt = <624000>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun menu-key { 36*4882a593Smuzhiyun linux,code = <KEY_MENU>; 37*4882a593Smuzhiyun label = "menu"; 38*4882a593Smuzhiyun press-threshold-microvolt = <987000>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun vol-down-key { 42*4882a593Smuzhiyun linux,code = <KEY_VOLUMEDOWN>; 43*4882a593Smuzhiyun label = "volume down"; 44*4882a593Smuzhiyun press-threshold-microvolt = <300000>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun vol-up-key { 48*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 49*4882a593Smuzhiyun label = "volume up"; 50*4882a593Smuzhiyun press-threshold-microvolt = <17000>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun rk817-sound { 55*4882a593Smuzhiyun compatible = "simple-audio-card"; 56*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 57*4882a593Smuzhiyun simple-audio-card,name = "rockchip,rk817-codec"; 58*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 59*4882a593Smuzhiyun simple-audio-card,cpu { 60*4882a593Smuzhiyun sound-dai = <&i2s1_2ch>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun simple-audio-card,codec { 63*4882a593Smuzhiyun sound-dai = <&rk817_codec>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun sdio_pwrseq: sdio-pwrseq { 68*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 69*4882a593Smuzhiyun /*clocks = <&rk817 1>;*/ 70*4882a593Smuzhiyun /*clock-names = "ext_clock";*/ 71*4882a593Smuzhiyun pinctrl-names = "default"; 72*4882a593Smuzhiyun pinctrl-0 = <&wifi_enable_h>; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* 75*4882a593Smuzhiyun * On the module itself this is one of these (depending 76*4882a593Smuzhiyun * on the actual card populated): 77*4882a593Smuzhiyun * - SDIO_RESET_L_WL_REG_ON 78*4882a593Smuzhiyun * - PDN (power down when low) 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun vccsys: vccsys { 84*4882a593Smuzhiyun compatible = "regulator-fixed"; 85*4882a593Smuzhiyun regulator-name = "vcc3v8_sys"; 86*4882a593Smuzhiyun regulator-always-on; 87*4882a593Smuzhiyun regulator-boot-on; 88*4882a593Smuzhiyun regulator-min-microvolt = <3800000>; 89*4882a593Smuzhiyun regulator-max-microvolt = <3800000>; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun wireless-wlan { 93*4882a593Smuzhiyun compatible = "wlan-platdata"; 94*4882a593Smuzhiyun wifi_chip_type = "AP6210"; 95*4882a593Smuzhiyun WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; 96*4882a593Smuzhiyun status = "okay"; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun}; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun&bus_apll { 101*4882a593Smuzhiyun bus-supply = <&vdd_logic>; 102*4882a593Smuzhiyun status = "okay"; 103*4882a593Smuzhiyun}; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun&cif_new { 106*4882a593Smuzhiyun status = "okay"; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun port { 109*4882a593Smuzhiyun cif_in: endpoint { 110*4882a593Smuzhiyun remote-endpoint = <&gc2155_out>; 111*4882a593Smuzhiyun vsync-active = <0>; 112*4882a593Smuzhiyun hsync-active = <1>; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun}; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun&cpu0 { 118*4882a593Smuzhiyun cpu-supply = <&vdd_arm>; 119*4882a593Smuzhiyun}; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun&dfi { 122*4882a593Smuzhiyun status = "okay"; 123*4882a593Smuzhiyun}; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun&dmc { 126*4882a593Smuzhiyun center-supply = <&vdd_logic>; 127*4882a593Smuzhiyun status = "okay"; 128*4882a593Smuzhiyun}; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun&emmc { 131*4882a593Smuzhiyun bus-width = <8>; 132*4882a593Smuzhiyun cap-mmc-highspeed; 133*4882a593Smuzhiyun mmc-hs200-1_8v; 134*4882a593Smuzhiyun no-sdio; 135*4882a593Smuzhiyun no-sd; 136*4882a593Smuzhiyun disable-wp; 137*4882a593Smuzhiyun non-removable; 138*4882a593Smuzhiyun num-slots = <1>; 139*4882a593Smuzhiyun status = "okay"; 140*4882a593Smuzhiyun}; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun&gpu { 143*4882a593Smuzhiyun mali-supply = <&vdd_logic>; 144*4882a593Smuzhiyun status = "okay"; 145*4882a593Smuzhiyun}; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun&i2c0 { 148*4882a593Smuzhiyun status = "okay"; 149*4882a593Smuzhiyun clock-frequency = <400000>; 150*4882a593Smuzhiyun i2c-scl-rising-time-ns = <280>; 151*4882a593Smuzhiyun i2c-scl-falling-time-ns = <16>; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun rk817: pmic@20 { 154*4882a593Smuzhiyun compatible = "rockchip,rk817"; 155*4882a593Smuzhiyun reg = <0x20>; 156*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 157*4882a593Smuzhiyun interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 158*4882a593Smuzhiyun pinctrl-names = "default", "pmic-sleep", 159*4882a593Smuzhiyun "pmic-power-off", "pmic-reset"; 160*4882a593Smuzhiyun pinctrl-0 = <&pmic_int>; 161*4882a593Smuzhiyun pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; 162*4882a593Smuzhiyun pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; 163*4882a593Smuzhiyun pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; 164*4882a593Smuzhiyun rockchip,system-power-controller; 165*4882a593Smuzhiyun wakeup-source; 166*4882a593Smuzhiyun #clock-cells = <1>; 167*4882a593Smuzhiyun clock-output-names = "rk808-clkout1", "rk808-clkout2"; 168*4882a593Smuzhiyun //fb-inner-reg-idxs = <2>; 169*4882a593Smuzhiyun /* 1: rst regs (default in codes), 0: rst the pmic */ 170*4882a593Smuzhiyun pmic-reset-func = <1>; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun vcc1-supply = <&vccsys>; 173*4882a593Smuzhiyun vcc2-supply = <&vccsys>; 174*4882a593Smuzhiyun vcc3-supply = <&vccsys>; 175*4882a593Smuzhiyun vcc4-supply = <&vccsys>; 176*4882a593Smuzhiyun vcc5-supply = <&vccsys>; 177*4882a593Smuzhiyun vcc6-supply = <&vccsys>; 178*4882a593Smuzhiyun vcc7-supply = <&vcc_3v0>; 179*4882a593Smuzhiyun vcc8-supply = <&vccsys>; 180*4882a593Smuzhiyun vcc9-supply = <&dcdc_boost>; 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun pwrkey { 183*4882a593Smuzhiyun status = "okay"; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun pinctrl_rk8xx: pinctrl_rk8xx { 187*4882a593Smuzhiyun gpio-controller; 188*4882a593Smuzhiyun #gpio-cells = <2>; 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun rk817_ts_gpio1: rk817_ts_gpio1 { 191*4882a593Smuzhiyun pins = "gpio_ts"; 192*4882a593Smuzhiyun function = "pin_fun1"; 193*4882a593Smuzhiyun /* output-low; */ 194*4882a593Smuzhiyun /* input-enable; */ 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun rk817_gt_gpio2: rk817_gt_gpio2 { 198*4882a593Smuzhiyun pins = "gpio_gt"; 199*4882a593Smuzhiyun function = "pin_fun1"; 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun rk817_pin_ts: rk817_pin_ts { 203*4882a593Smuzhiyun pins = "gpio_ts"; 204*4882a593Smuzhiyun function = "pin_fun0"; 205*4882a593Smuzhiyun }; 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun rk817_pin_gt: rk817_pin_gt { 208*4882a593Smuzhiyun pins = "gpio_gt"; 209*4882a593Smuzhiyun function = "pin_fun0"; 210*4882a593Smuzhiyun }; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun rk817_slppin_null: rk817_slppin_null { 213*4882a593Smuzhiyun pins = "gpio_slp"; 214*4882a593Smuzhiyun function = "pin_fun0"; 215*4882a593Smuzhiyun }; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun rk817_slppin_slp: rk817_slppin_slp { 218*4882a593Smuzhiyun pins = "gpio_slp"; 219*4882a593Smuzhiyun function = "pin_fun1"; 220*4882a593Smuzhiyun }; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun rk817_slppin_pwrdn: rk817_slppin_pwrdn { 223*4882a593Smuzhiyun pins = "gpio_slp"; 224*4882a593Smuzhiyun function = "pin_fun2"; 225*4882a593Smuzhiyun }; 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun rk817_slppin_rst: rk817_slppin_rst { 228*4882a593Smuzhiyun pins = "gpio_slp"; 229*4882a593Smuzhiyun function = "pin_fun3"; 230*4882a593Smuzhiyun }; 231*4882a593Smuzhiyun }; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun regulators { 234*4882a593Smuzhiyun vdd_logic: DCDC_REG1 { 235*4882a593Smuzhiyun regulator-always-on; 236*4882a593Smuzhiyun regulator-boot-on; 237*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 238*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 239*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 240*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 241*4882a593Smuzhiyun regulator-name = "vdd_logic"; 242*4882a593Smuzhiyun regulator-state-mem { 243*4882a593Smuzhiyun regulator-on-in-suspend; 244*4882a593Smuzhiyun regulator-suspend-microvolt = <950000>; 245*4882a593Smuzhiyun }; 246*4882a593Smuzhiyun }; 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun vdd_arm: DCDC_REG2 { 249*4882a593Smuzhiyun regulator-always-on; 250*4882a593Smuzhiyun regulator-boot-on; 251*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 252*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 253*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 254*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 255*4882a593Smuzhiyun regulator-name = "vdd_arm"; 256*4882a593Smuzhiyun regulator-state-mem { 257*4882a593Smuzhiyun regulator-off-in-suspend; 258*4882a593Smuzhiyun regulator-suspend-microvolt = <950000>; 259*4882a593Smuzhiyun }; 260*4882a593Smuzhiyun }; 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun vcc_ddr: DCDC_REG3 { 263*4882a593Smuzhiyun regulator-always-on; 264*4882a593Smuzhiyun regulator-boot-on; 265*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 266*4882a593Smuzhiyun regulator-name = "vcc_ddr"; 267*4882a593Smuzhiyun regulator-state-mem { 268*4882a593Smuzhiyun regulator-on-in-suspend; 269*4882a593Smuzhiyun }; 270*4882a593Smuzhiyun }; 271*4882a593Smuzhiyun 272*4882a593Smuzhiyun vcc_3v0: DCDC_REG4 { 273*4882a593Smuzhiyun regulator-always-on; 274*4882a593Smuzhiyun regulator-boot-on; 275*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 276*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 277*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 278*4882a593Smuzhiyun regulator-name = "vcc_3v0"; 279*4882a593Smuzhiyun regulator-state-mem { 280*4882a593Smuzhiyun regulator-off-in-suspend; 281*4882a593Smuzhiyun regulator-suspend-microvolt = <3000000>; 282*4882a593Smuzhiyun }; 283*4882a593Smuzhiyun }; 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun vcc_1v0: LDO_REG1 { 286*4882a593Smuzhiyun regulator-always-on; 287*4882a593Smuzhiyun regulator-boot-on; 288*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 289*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 290*4882a593Smuzhiyun regulator-name = "vcc_1v0"; 291*4882a593Smuzhiyun regulator-state-mem { 292*4882a593Smuzhiyun regulator-on-in-suspend; 293*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 294*4882a593Smuzhiyun }; 295*4882a593Smuzhiyun }; 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun vcc1v8_soc: LDO_REG2 { 298*4882a593Smuzhiyun regulator-always-on; 299*4882a593Smuzhiyun regulator-boot-on; 300*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 301*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun regulator-name = "vcc1v8_soc"; 304*4882a593Smuzhiyun regulator-state-mem { 305*4882a593Smuzhiyun regulator-on-in-suspend; 306*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 307*4882a593Smuzhiyun }; 308*4882a593Smuzhiyun }; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun vdd1v0_soc: LDO_REG3 { 311*4882a593Smuzhiyun regulator-always-on; 312*4882a593Smuzhiyun regulator-boot-on; 313*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 314*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun regulator-name = "vcc1v0_soc"; 317*4882a593Smuzhiyun regulator-state-mem { 318*4882a593Smuzhiyun regulator-on-in-suspend; 319*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 320*4882a593Smuzhiyun }; 321*4882a593Smuzhiyun }; 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun vcc3v0_pmu: LDO_REG4 { 324*4882a593Smuzhiyun regulator-always-on; 325*4882a593Smuzhiyun regulator-boot-on; 326*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 327*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 328*4882a593Smuzhiyun 329*4882a593Smuzhiyun regulator-name = "vcc3v0_pmu"; 330*4882a593Smuzhiyun regulator-state-mem { 331*4882a593Smuzhiyun regulator-on-in-suspend; 332*4882a593Smuzhiyun regulator-suspend-microvolt = <3000000>; 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun }; 335*4882a593Smuzhiyun }; 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun vccio_sd: LDO_REG5 { 338*4882a593Smuzhiyun regulator-always-on; 339*4882a593Smuzhiyun regulator-boot-on; 340*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 341*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 342*4882a593Smuzhiyun 343*4882a593Smuzhiyun regulator-name = "vccio_sd"; 344*4882a593Smuzhiyun regulator-state-mem { 345*4882a593Smuzhiyun regulator-on-in-suspend; 346*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 347*4882a593Smuzhiyun }; 348*4882a593Smuzhiyun }; 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun vcc_sd: LDO_REG6 { 351*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 352*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun regulator-name = "vcc_sd"; 355*4882a593Smuzhiyun regulator-state-mem { 356*4882a593Smuzhiyun regulator-on-in-suspend; 357*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun }; 360*4882a593Smuzhiyun }; 361*4882a593Smuzhiyun 362*4882a593Smuzhiyun vcc2v8_dvp: LDO_REG7 { 363*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 364*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun regulator-name = "vcc2v8_dvp"; 367*4882a593Smuzhiyun regulator-state-mem { 368*4882a593Smuzhiyun regulator-off-in-suspend; 369*4882a593Smuzhiyun regulator-suspend-microvolt = <2800000>; 370*4882a593Smuzhiyun }; 371*4882a593Smuzhiyun }; 372*4882a593Smuzhiyun 373*4882a593Smuzhiyun vcc1v8_dvp: LDO_REG8 { 374*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 375*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 376*4882a593Smuzhiyun 377*4882a593Smuzhiyun regulator-name = "vcc1v8_dvp"; 378*4882a593Smuzhiyun regulator-state-mem { 379*4882a593Smuzhiyun regulator-on-in-suspend; 380*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 381*4882a593Smuzhiyun }; 382*4882a593Smuzhiyun }; 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun vdd1v5_dvp: LDO_REG9 { 385*4882a593Smuzhiyun regulator-min-microvolt = <1500000>; 386*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun regulator-name = "vdd1v5_dvp"; 389*4882a593Smuzhiyun regulator-state-mem { 390*4882a593Smuzhiyun regulator-off-in-suspend; 391*4882a593Smuzhiyun regulator-suspend-microvolt = <1500000>; 392*4882a593Smuzhiyun }; 393*4882a593Smuzhiyun }; 394*4882a593Smuzhiyun 395*4882a593Smuzhiyun dcdc_boost: BOOST { 396*4882a593Smuzhiyun regulator-always-on; 397*4882a593Smuzhiyun regulator-boot-on; 398*4882a593Smuzhiyun regulator-min-microvolt = <4700000>; 399*4882a593Smuzhiyun regulator-max-microvolt = <5400000>; 400*4882a593Smuzhiyun regulator-name = "boost"; 401*4882a593Smuzhiyun }; 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun otg_switch: OTG_SWITCH { 404*4882a593Smuzhiyun regulator-name = "otg_switch"; 405*4882a593Smuzhiyun }; 406*4882a593Smuzhiyun }; 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun battery { 409*4882a593Smuzhiyun compatible = "rk817,battery"; 410*4882a593Smuzhiyun ocv_table = <3500 3625 3685 3697 3718 3735 3748 411*4882a593Smuzhiyun 3760 3774 3788 3802 3816 3834 3853 412*4882a593Smuzhiyun 3877 3908 3946 3975 4018 4071 4106>; 413*4882a593Smuzhiyun design_capacity = <2500>; 414*4882a593Smuzhiyun design_qmax = <2750>; 415*4882a593Smuzhiyun bat_res = <100>; 416*4882a593Smuzhiyun sleep_enter_current = <300>; 417*4882a593Smuzhiyun sleep_exit_current = <300>; 418*4882a593Smuzhiyun sleep_filter_current = <100>; 419*4882a593Smuzhiyun power_off_thresd = <3500>; 420*4882a593Smuzhiyun zero_algorithm_vol = <3850>; 421*4882a593Smuzhiyun max_soc_offset = <60>; 422*4882a593Smuzhiyun monitor_sec = <5>; 423*4882a593Smuzhiyun sample_res = <10>; 424*4882a593Smuzhiyun virtual_power = <1>; 425*4882a593Smuzhiyun }; 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun charger { 428*4882a593Smuzhiyun compatible = "rk817,charger"; 429*4882a593Smuzhiyun min_input_voltage = <4500>; 430*4882a593Smuzhiyun max_input_current = <1500>; 431*4882a593Smuzhiyun max_chrg_current = <2000>; 432*4882a593Smuzhiyun max_chrg_voltage = <4200>; 433*4882a593Smuzhiyun chrg_term_mode = <0>; 434*4882a593Smuzhiyun chrg_finish_cur = <300>; 435*4882a593Smuzhiyun virtual_power = <0>; 436*4882a593Smuzhiyun dc_det_adc = <0>; 437*4882a593Smuzhiyun extcon = <&u2phy>; 438*4882a593Smuzhiyun }; 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun rk817_codec: codec { 441*4882a593Smuzhiyun #sound-dai-cells = <0>; 442*4882a593Smuzhiyun compatible = "rockchip,rk817-codec"; 443*4882a593Smuzhiyun clocks = <&cru SCLK_I2S1_OUT>; 444*4882a593Smuzhiyun clock-names = "mclk"; 445*4882a593Smuzhiyun pinctrl-names = "default"; 446*4882a593Smuzhiyun pinctrl-0 = <&i2s1_2ch_mclk>; 447*4882a593Smuzhiyun hp-volume = <20>; 448*4882a593Smuzhiyun spk-volume = <3>; 449*4882a593Smuzhiyun status = "okay"; 450*4882a593Smuzhiyun }; 451*4882a593Smuzhiyun }; 452*4882a593Smuzhiyun}; 453*4882a593Smuzhiyun 454*4882a593Smuzhiyun&i2c2 { 455*4882a593Smuzhiyun status = "okay"; 456*4882a593Smuzhiyun clock-frequency = <400000>; 457*4882a593Smuzhiyun 458*4882a593Smuzhiyun /* 24M mclk is shared for multiple cameras */ 459*4882a593Smuzhiyun pinctrl-0 = <&i2c2_xfer &cif_clkout_m0>; 460*4882a593Smuzhiyun 461*4882a593Smuzhiyun /* These are relatively safe rise/fall times; TODO: measure */ 462*4882a593Smuzhiyun i2c-scl-falling-time-ns = <50>; 463*4882a593Smuzhiyun i2c-scl-rising-time-ns = <300>; 464*4882a593Smuzhiyun 465*4882a593Smuzhiyun gc2155: gc2155@3c { 466*4882a593Smuzhiyun compatible = "gc,gc2155"; 467*4882a593Smuzhiyun reg = <0x3c>; 468*4882a593Smuzhiyun pinctrl-names = "default"; 469*4882a593Smuzhiyun pinctrl-0 = <&cif_pin_m0>; 470*4882a593Smuzhiyun 471*4882a593Smuzhiyun clocks = <&cru SCLK_CIF_OUT>; 472*4882a593Smuzhiyun clock-names = "xvclk"; 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun avdd-supply = <&vcc2v8_dvp>; 475*4882a593Smuzhiyun dovdd-supply = <&vcc1v8_dvp>; 476*4882a593Smuzhiyun dvdd-supply = <&vcc1v8_dvp>; 477*4882a593Smuzhiyun 478*4882a593Smuzhiyun /* hw changed the pwdn to gpio2_b5 */ 479*4882a593Smuzhiyun pwdn-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; 480*4882a593Smuzhiyun 481*4882a593Smuzhiyun port { 482*4882a593Smuzhiyun gc2155_out: endpoint { 483*4882a593Smuzhiyun remote-endpoint = <&cif_in>; 484*4882a593Smuzhiyun }; 485*4882a593Smuzhiyun }; 486*4882a593Smuzhiyun }; 487*4882a593Smuzhiyun 488*4882a593Smuzhiyun ov5695: ov5695@36 { 489*4882a593Smuzhiyun compatible = "ovti,ov5695"; 490*4882a593Smuzhiyun reg = <0x36>; 491*4882a593Smuzhiyun 492*4882a593Smuzhiyun clocks = <&cru SCLK_CIF_OUT>; 493*4882a593Smuzhiyun clock-names = "xvclk"; 494*4882a593Smuzhiyun 495*4882a593Smuzhiyun avdd-supply = <&vcc2v8_dvp>; 496*4882a593Smuzhiyun dovdd-supply = <&vcc1v8_dvp>; 497*4882a593Smuzhiyun dvdd-supply = <&vcc1v8_dvp>; 498*4882a593Smuzhiyun 499*4882a593Smuzhiyun /*reset-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;*/ 500*4882a593Smuzhiyun pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; 501*4882a593Smuzhiyun 502*4882a593Smuzhiyun port { 503*4882a593Smuzhiyun ucam_out: endpoint { 504*4882a593Smuzhiyun remote-endpoint = <&mipi_in_ucam>; 505*4882a593Smuzhiyun data-lanes = <1 2>; 506*4882a593Smuzhiyun }; 507*4882a593Smuzhiyun }; 508*4882a593Smuzhiyun }; 509*4882a593Smuzhiyun}; 510*4882a593Smuzhiyun 511*4882a593Smuzhiyun&i2s1_2ch { 512*4882a593Smuzhiyun status = "okay"; 513*4882a593Smuzhiyun #sound-dai-cells = <0>; 514*4882a593Smuzhiyun}; 515*4882a593Smuzhiyun 516*4882a593Smuzhiyun&io_domains { 517*4882a593Smuzhiyun status = "okay"; 518*4882a593Smuzhiyun 519*4882a593Smuzhiyun vccio1-supply = <&vcc1v8_soc>; 520*4882a593Smuzhiyun vccio2-supply = <&vccio_sd>; 521*4882a593Smuzhiyun vccio3-supply = <&vcc1v8_dvp>; 522*4882a593Smuzhiyun vccio4-supply = <&vcc_3v0>; 523*4882a593Smuzhiyun vccio5-supply = <&vcc_3v0>; 524*4882a593Smuzhiyun}; 525*4882a593Smuzhiyun 526*4882a593Smuzhiyun&isp_mmu { 527*4882a593Smuzhiyun status = "okay"; 528*4882a593Smuzhiyun}; 529*4882a593Smuzhiyun 530*4882a593Smuzhiyun&mipi_dphy_rx0 { 531*4882a593Smuzhiyun status = "okay"; 532*4882a593Smuzhiyun 533*4882a593Smuzhiyun ports { 534*4882a593Smuzhiyun #address-cells = <1>; 535*4882a593Smuzhiyun #size-cells = <0>; 536*4882a593Smuzhiyun 537*4882a593Smuzhiyun port@0 { 538*4882a593Smuzhiyun reg = <0>; 539*4882a593Smuzhiyun #address-cells = <1>; 540*4882a593Smuzhiyun #size-cells = <0>; 541*4882a593Smuzhiyun 542*4882a593Smuzhiyun mipi_in_ucam: endpoint@1 { 543*4882a593Smuzhiyun reg = <1>; 544*4882a593Smuzhiyun remote-endpoint = <&ucam_out>; 545*4882a593Smuzhiyun data-lanes = <1 2>; 546*4882a593Smuzhiyun }; 547*4882a593Smuzhiyun }; 548*4882a593Smuzhiyun 549*4882a593Smuzhiyun port@1 { 550*4882a593Smuzhiyun reg = <1>; 551*4882a593Smuzhiyun #address-cells = <1>; 552*4882a593Smuzhiyun #size-cells = <0>; 553*4882a593Smuzhiyun 554*4882a593Smuzhiyun dphy_rx0_out: endpoint@0 { 555*4882a593Smuzhiyun reg = <0>; 556*4882a593Smuzhiyun remote-endpoint = <&isp0_mipi_in>; 557*4882a593Smuzhiyun }; 558*4882a593Smuzhiyun }; 559*4882a593Smuzhiyun }; 560*4882a593Smuzhiyun}; 561*4882a593Smuzhiyun 562*4882a593Smuzhiyun&nandc0 { 563*4882a593Smuzhiyun status = "okay"; 564*4882a593Smuzhiyun}; 565*4882a593Smuzhiyun 566*4882a593Smuzhiyun&rkisp1 { 567*4882a593Smuzhiyun status = "okay"; 568*4882a593Smuzhiyun 569*4882a593Smuzhiyun port { 570*4882a593Smuzhiyun #address-cells = <1>; 571*4882a593Smuzhiyun #size-cells = <0>; 572*4882a593Smuzhiyun 573*4882a593Smuzhiyun isp0_mipi_in: endpoint@0 { 574*4882a593Smuzhiyun reg = <0>; 575*4882a593Smuzhiyun remote-endpoint = <&dphy_rx0_out>; 576*4882a593Smuzhiyun }; 577*4882a593Smuzhiyun }; 578*4882a593Smuzhiyun}; 579*4882a593Smuzhiyun 580*4882a593Smuzhiyun&pmu_io_domains { 581*4882a593Smuzhiyun status = "okay"; 582*4882a593Smuzhiyun 583*4882a593Smuzhiyun pmuio1-supply = <&vcc3v0_pmu>; 584*4882a593Smuzhiyun pmuio2-supply = <&vcc3v0_pmu>; 585*4882a593Smuzhiyun}; 586*4882a593Smuzhiyun 587*4882a593Smuzhiyun&rk_rga { 588*4882a593Smuzhiyun status = "okay"; 589*4882a593Smuzhiyun}; 590*4882a593Smuzhiyun 591*4882a593Smuzhiyun&saradc { 592*4882a593Smuzhiyun status = "okay"; 593*4882a593Smuzhiyun vref-supply = <&vcc1v8_soc>; 594*4882a593Smuzhiyun}; 595*4882a593Smuzhiyun 596*4882a593Smuzhiyun&sdmmc { 597*4882a593Smuzhiyun bus-width = <4>; 598*4882a593Smuzhiyun cap-mmc-highspeed; 599*4882a593Smuzhiyun cap-sd-highspeed; 600*4882a593Smuzhiyun no-sdio; 601*4882a593Smuzhiyun no-mmc; 602*4882a593Smuzhiyun card-detect-delay = <800>; 603*4882a593Smuzhiyun ignore-pm-notify; 604*4882a593Smuzhiyun /*cd-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; [> CD GPIO <]*/ 605*4882a593Smuzhiyun sd-uhs-sdr12; 606*4882a593Smuzhiyun sd-uhs-sdr25; 607*4882a593Smuzhiyun sd-uhs-sdr50; 608*4882a593Smuzhiyun sd-uhs-sdr104; 609*4882a593Smuzhiyun vqmmc-supply = <&vccio_sd>; 610*4882a593Smuzhiyun vmmc-supply = <&vcc_sd>; 611*4882a593Smuzhiyun status = "disabled"; 612*4882a593Smuzhiyun}; 613*4882a593Smuzhiyun 614*4882a593Smuzhiyun&sdio { 615*4882a593Smuzhiyun bus-width = <4>; 616*4882a593Smuzhiyun cap-sd-highspeed; 617*4882a593Smuzhiyun no-sd; 618*4882a593Smuzhiyun no-mmc; 619*4882a593Smuzhiyun ignore-pm-notify; 620*4882a593Smuzhiyun keep-power-in-suspend; 621*4882a593Smuzhiyun non-removable; 622*4882a593Smuzhiyun mmc-pwrseq = <&sdio_pwrseq>; 623*4882a593Smuzhiyun sd-uhs-sdr104; 624*4882a593Smuzhiyun status = "okay"; 625*4882a593Smuzhiyun}; 626*4882a593Smuzhiyun 627*4882a593Smuzhiyun&tsadc { 628*4882a593Smuzhiyun pinctrl-names = "init", "default"; 629*4882a593Smuzhiyun pinctrl-0 = <&tsadc_otp_gpio>; 630*4882a593Smuzhiyun pinctrl-1 = <&tsadc_otp_out>; 631*4882a593Smuzhiyun status = "okay"; 632*4882a593Smuzhiyun}; 633*4882a593Smuzhiyun 634*4882a593Smuzhiyun&u2phy { 635*4882a593Smuzhiyun status = "okay"; 636*4882a593Smuzhiyun 637*4882a593Smuzhiyun u2phy_host: host-port { 638*4882a593Smuzhiyun status = "okay"; 639*4882a593Smuzhiyun }; 640*4882a593Smuzhiyun 641*4882a593Smuzhiyun u2phy_otg: otg-port { 642*4882a593Smuzhiyun status = "okay"; 643*4882a593Smuzhiyun }; 644*4882a593Smuzhiyun}; 645*4882a593Smuzhiyun 646*4882a593Smuzhiyun&usb20_otg { 647*4882a593Smuzhiyun status = "okay"; 648*4882a593Smuzhiyun}; 649*4882a593Smuzhiyun 650*4882a593Smuzhiyun&uart1 { 651*4882a593Smuzhiyun pinctrl-names = "default"; 652*4882a593Smuzhiyun pinctrl-0 = <&uart1_xfer &uart1_cts>; 653*4882a593Smuzhiyun status = "okay"; 654*4882a593Smuzhiyun}; 655*4882a593Smuzhiyun 656*4882a593Smuzhiyun&vip_mmu { 657*4882a593Smuzhiyun status = "okay"; 658*4882a593Smuzhiyun}; 659*4882a593Smuzhiyun 660*4882a593Smuzhiyun&mpp_srv { 661*4882a593Smuzhiyun status = "okay"; 662*4882a593Smuzhiyun}; 663*4882a593Smuzhiyun 664*4882a593Smuzhiyun&vdpu { 665*4882a593Smuzhiyun status = "okay"; 666*4882a593Smuzhiyun}; 667*4882a593Smuzhiyun 668*4882a593Smuzhiyun&vepu { 669*4882a593Smuzhiyun status = "okay"; 670*4882a593Smuzhiyun}; 671*4882a593Smuzhiyun 672*4882a593Smuzhiyun&vpu_mmu { 673*4882a593Smuzhiyun status = "okay"; 674*4882a593Smuzhiyun}; 675*4882a593Smuzhiyun 676*4882a593Smuzhiyun&hevc { 677*4882a593Smuzhiyun status = "okay"; 678*4882a593Smuzhiyun}; 679*4882a593Smuzhiyun 680*4882a593Smuzhiyun&hevc_mmu { 681*4882a593Smuzhiyun status = "okay"; 682*4882a593Smuzhiyun}; 683*4882a593Smuzhiyun 684*4882a593Smuzhiyun&pinctrl { 685*4882a593Smuzhiyun cif-pin-m0 { 686*4882a593Smuzhiyun cif_pin_m0: cif-pin-m0 { 687*4882a593Smuzhiyun rockchip,pins = 688*4882a593Smuzhiyun <2 RK_PA0 1 &pcfg_pull_none>,/* cif_data2 */ 689*4882a593Smuzhiyun <2 RK_PA1 1 &pcfg_pull_none>,/* cif_data3 */ 690*4882a593Smuzhiyun <2 RK_PA2 1 &pcfg_pull_none>,/* cif_data4 */ 691*4882a593Smuzhiyun <2 RK_PA3 1 &pcfg_pull_none>,/* cif_data5 */ 692*4882a593Smuzhiyun <2 RK_PA4 1 &pcfg_pull_none>,/* cif_data6 */ 693*4882a593Smuzhiyun <2 RK_PA5 1 &pcfg_pull_none>,/* cif_data7 */ 694*4882a593Smuzhiyun <2 RK_PA6 1 &pcfg_pull_none>,/* cif_data8 */ 695*4882a593Smuzhiyun <2 RK_PA7 1 &pcfg_pull_none>,/* cif_data9 */ 696*4882a593Smuzhiyun <2 RK_PB0 1 &pcfg_pull_none>,/* cif_sync */ 697*4882a593Smuzhiyun <2 RK_PB1 1 &pcfg_pull_none>,/* cif_href */ 698*4882a593Smuzhiyun <2 RK_PB2 1 &pcfg_pull_none>;/* cif_clkin */ 699*4882a593Smuzhiyun }; 700*4882a593Smuzhiyun 701*4882a593Smuzhiyun cif_pin_m1: cif-pin-m1 { 702*4882a593Smuzhiyun rockchip,pins = 703*4882a593Smuzhiyun <3 RK_PA3 3 &pcfg_pull_none>,/* cif_data2 */ 704*4882a593Smuzhiyun <3 RK_PA5 3 &pcfg_pull_none>,/* cif_data3 */ 705*4882a593Smuzhiyun <3 RK_PA7 3 &pcfg_pull_none>,/* cif_data4 */ 706*4882a593Smuzhiyun <3 RK_PB0 3 &pcfg_pull_none>,/* cif_data5 */ 707*4882a593Smuzhiyun <3 RK_PB1 3 &pcfg_pull_none>,/* cif_data6 */ 708*4882a593Smuzhiyun <3 RK_PB4 3 &pcfg_pull_none>,/* cif_data7 */ 709*4882a593Smuzhiyun <3 RK_PB6 3 &pcfg_pull_none>,/* cif_data8 */ 710*4882a593Smuzhiyun <3 RK_PB7 3 &pcfg_pull_none>,/* cif_data9 */ 711*4882a593Smuzhiyun <3 RK_PD1 3 &pcfg_pull_none>,/* cif_sync */ 712*4882a593Smuzhiyun <3 RK_PD2 3 &pcfg_pull_none>,/* cif_href */ 713*4882a593Smuzhiyun <3 RK_PD3 3 &pcfg_pull_none>;/* cif_clkin */ 714*4882a593Smuzhiyun }; 715*4882a593Smuzhiyun }; 716*4882a593Smuzhiyun 717*4882a593Smuzhiyun pmic { 718*4882a593Smuzhiyun pmic_int: pmic_int { 719*4882a593Smuzhiyun rockchip,pins = 720*4882a593Smuzhiyun <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; 721*4882a593Smuzhiyun }; 722*4882a593Smuzhiyun 723*4882a593Smuzhiyun soc_slppin_gpio: soc_slppin_gpio { 724*4882a593Smuzhiyun rockchip,pins = 725*4882a593Smuzhiyun <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; 726*4882a593Smuzhiyun }; 727*4882a593Smuzhiyun 728*4882a593Smuzhiyun soc_slppin_slp: soc_slppin_slp { 729*4882a593Smuzhiyun rockchip,pins = 730*4882a593Smuzhiyun <0 RK_PA4 1 &pcfg_pull_none>; 731*4882a593Smuzhiyun }; 732*4882a593Smuzhiyun 733*4882a593Smuzhiyun soc_slppin_rst: soc_slppin_rst { 734*4882a593Smuzhiyun rockchip,pins = 735*4882a593Smuzhiyun <0 RK_PA4 2 &pcfg_pull_none>; 736*4882a593Smuzhiyun }; 737*4882a593Smuzhiyun }; 738*4882a593Smuzhiyun 739*4882a593Smuzhiyun sdio-pwrseq { 740*4882a593Smuzhiyun wifi_enable_h: wifi-enable-h { 741*4882a593Smuzhiyun rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; 742*4882a593Smuzhiyun }; 743*4882a593Smuzhiyun }; 744*4882a593Smuzhiyun}; 745*4882a593Smuzhiyun 746*4882a593Smuzhiyun/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ 747*4882a593Smuzhiyun/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ 748*4882a593Smuzhiyun/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ 749