xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3326-evb-lp3-v10-robot-linux.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
4 */
5
6/dts-v1/;
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/pinctrl/rockchip.h>
9#include <dt-bindings/input/input.h>
10#include "px30-robot.dtsi"
11
12/ {
13	model = "Rockchip rk3326 evb lpddr3 v10 board for robot linux";
14	compatible = "rockchip,rk3326-evb-lp3-v10-robot-linux", "rockchip,rk3326";
15
16	adc-keys {
17		compatible = "adc-keys";
18		io-channels = <&saradc 2>;
19		io-channel-names = "buttons";
20		poll-interval = <100>;
21		keyup-threshold-microvolt = <1800000>;
22
23		esc-key {
24			linux,code = <KEY_ESC>;
25			label = "esc";
26			press-threshold-microvolt = <1310000>;
27		};
28
29		home-key {
30			linux,code = <KEY_HOME>;
31			label = "home";
32			press-threshold-microvolt = <624000>;
33		};
34
35		menu-key {
36			linux,code = <KEY_MENU>;
37			label = "menu";
38			press-threshold-microvolt = <987000>;
39		};
40
41		vol-down-key {
42			linux,code = <KEY_VOLUMEDOWN>;
43			label = "volume down";
44			press-threshold-microvolt = <300000>;
45		};
46
47		vol-up-key {
48			linux,code = <KEY_VOLUMEUP>;
49			label = "volume up";
50			press-threshold-microvolt = <17000>;
51		};
52	};
53
54	rk817-sound {
55		compatible = "simple-audio-card";
56		simple-audio-card,format = "i2s";
57		simple-audio-card,name = "rockchip,rk817-codec";
58		simple-audio-card,mclk-fs = <256>;
59		simple-audio-card,cpu {
60			sound-dai = <&i2s1_2ch>;
61		};
62		simple-audio-card,codec {
63			sound-dai = <&rk817_codec>;
64		};
65	};
66
67	sdio_pwrseq: sdio-pwrseq {
68		compatible = "mmc-pwrseq-simple";
69		/*clocks = <&rk817 1>;*/
70		/*clock-names = "ext_clock";*/
71		pinctrl-names = "default";
72		pinctrl-0 = <&wifi_enable_h>;
73
74		/*
75		 * On the module itself this is one of these (depending
76		 * on the actual card populated):
77		 * - SDIO_RESET_L_WL_REG_ON
78		 * - PDN (power down when low)
79		 */
80		reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */
81	};
82
83	vccsys: vccsys {
84		compatible = "regulator-fixed";
85		regulator-name = "vcc3v8_sys";
86		regulator-always-on;
87		regulator-boot-on;
88		regulator-min-microvolt = <3800000>;
89		regulator-max-microvolt = <3800000>;
90	};
91
92	wireless-wlan {
93		compatible = "wlan-platdata";
94		wifi_chip_type = "AP6210";
95		WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
96		status = "okay";
97	};
98};
99
100&bus_apll {
101	bus-supply = <&vdd_logic>;
102	status = "okay";
103};
104
105&cif_new {
106	status = "okay";
107
108	port {
109		cif_in: endpoint {
110			remote-endpoint = <&gc2155_out>;
111			vsync-active = <0>;
112			hsync-active = <1>;
113		};
114	};
115};
116
117&cpu0 {
118	cpu-supply = <&vdd_arm>;
119};
120
121&dfi {
122	status = "okay";
123};
124
125&dmc {
126	center-supply = <&vdd_logic>;
127	status = "okay";
128};
129
130&emmc {
131	bus-width = <8>;
132	cap-mmc-highspeed;
133	mmc-hs200-1_8v;
134	no-sdio;
135	no-sd;
136	disable-wp;
137	non-removable;
138	num-slots = <1>;
139	status = "okay";
140};
141
142&gpu {
143	mali-supply = <&vdd_logic>;
144	status = "okay";
145};
146
147&i2c0 {
148	status = "okay";
149	clock-frequency = <400000>;
150	i2c-scl-rising-time-ns = <280>;
151	i2c-scl-falling-time-ns = <16>;
152
153	rk817: pmic@20 {
154		compatible = "rockchip,rk817";
155		reg = <0x20>;
156		interrupt-parent = <&gpio0>;
157		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
158		pinctrl-names = "default", "pmic-sleep",
159				"pmic-power-off", "pmic-reset";
160		pinctrl-0 = <&pmic_int>;
161		pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
162		pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
163		pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
164		rockchip,system-power-controller;
165		wakeup-source;
166		#clock-cells = <1>;
167		clock-output-names = "rk808-clkout1", "rk808-clkout2";
168		//fb-inner-reg-idxs = <2>;
169		/* 1: rst regs (default in codes), 0: rst the pmic */
170		pmic-reset-func = <1>;
171
172		vcc1-supply = <&vccsys>;
173		vcc2-supply = <&vccsys>;
174		vcc3-supply = <&vccsys>;
175		vcc4-supply = <&vccsys>;
176		vcc5-supply = <&vccsys>;
177		vcc6-supply = <&vccsys>;
178		vcc7-supply = <&vcc_3v0>;
179		vcc8-supply = <&vccsys>;
180		vcc9-supply = <&dcdc_boost>;
181
182		pwrkey {
183			status = "okay";
184		};
185
186		pinctrl_rk8xx: pinctrl_rk8xx {
187			gpio-controller;
188			#gpio-cells = <2>;
189
190			rk817_ts_gpio1: rk817_ts_gpio1 {
191				pins = "gpio_ts";
192				function = "pin_fun1";
193				/* output-low; */
194				/* input-enable; */
195			};
196
197			rk817_gt_gpio2: rk817_gt_gpio2 {
198				pins = "gpio_gt";
199				function = "pin_fun1";
200			};
201
202			rk817_pin_ts: rk817_pin_ts {
203				pins = "gpio_ts";
204				function = "pin_fun0";
205			};
206
207			rk817_pin_gt: rk817_pin_gt {
208				pins = "gpio_gt";
209				function = "pin_fun0";
210			};
211
212			rk817_slppin_null: rk817_slppin_null {
213				pins = "gpio_slp";
214				function = "pin_fun0";
215			};
216
217			rk817_slppin_slp: rk817_slppin_slp {
218				pins = "gpio_slp";
219				function = "pin_fun1";
220			};
221
222			rk817_slppin_pwrdn: rk817_slppin_pwrdn {
223				pins = "gpio_slp";
224				function = "pin_fun2";
225			};
226
227			rk817_slppin_rst: rk817_slppin_rst {
228				pins = "gpio_slp";
229				function = "pin_fun3";
230			};
231		};
232
233		regulators {
234			vdd_logic: DCDC_REG1 {
235				regulator-always-on;
236				regulator-boot-on;
237				regulator-min-microvolt = <850000>;
238				regulator-max-microvolt = <1350000>;
239				regulator-ramp-delay = <6001>;
240				regulator-initial-mode = <0x2>;
241				regulator-name = "vdd_logic";
242				regulator-state-mem {
243					regulator-on-in-suspend;
244					regulator-suspend-microvolt = <950000>;
245				};
246			};
247
248			vdd_arm: DCDC_REG2 {
249				regulator-always-on;
250				regulator-boot-on;
251				regulator-min-microvolt = <850000>;
252				regulator-max-microvolt = <1350000>;
253				regulator-ramp-delay = <6001>;
254				regulator-initial-mode = <0x2>;
255				regulator-name = "vdd_arm";
256				regulator-state-mem {
257					regulator-off-in-suspend;
258					regulator-suspend-microvolt = <950000>;
259				};
260			};
261
262			vcc_ddr: DCDC_REG3 {
263				regulator-always-on;
264				regulator-boot-on;
265				regulator-initial-mode = <0x2>;
266				regulator-name = "vcc_ddr";
267				regulator-state-mem {
268					regulator-on-in-suspend;
269				};
270			};
271
272			vcc_3v0: DCDC_REG4 {
273				regulator-always-on;
274				regulator-boot-on;
275				regulator-min-microvolt = <3000000>;
276				regulator-max-microvolt = <3000000>;
277				regulator-initial-mode = <0x2>;
278				regulator-name = "vcc_3v0";
279				regulator-state-mem {
280					regulator-off-in-suspend;
281					regulator-suspend-microvolt = <3000000>;
282				};
283			};
284
285			vcc_1v0: LDO_REG1 {
286				regulator-always-on;
287				regulator-boot-on;
288				regulator-min-microvolt = <1000000>;
289				regulator-max-microvolt = <1000000>;
290				regulator-name = "vcc_1v0";
291				regulator-state-mem {
292					regulator-on-in-suspend;
293					regulator-suspend-microvolt = <1000000>;
294				};
295			};
296
297			vcc1v8_soc: LDO_REG2 {
298				regulator-always-on;
299				regulator-boot-on;
300				regulator-min-microvolt = <1800000>;
301				regulator-max-microvolt = <1800000>;
302
303				regulator-name = "vcc1v8_soc";
304				regulator-state-mem {
305					regulator-on-in-suspend;
306					regulator-suspend-microvolt = <1800000>;
307				};
308			};
309
310			vdd1v0_soc: LDO_REG3 {
311				regulator-always-on;
312				regulator-boot-on;
313				regulator-min-microvolt = <1000000>;
314				regulator-max-microvolt = <1000000>;
315
316				regulator-name = "vcc1v0_soc";
317				regulator-state-mem {
318					regulator-on-in-suspend;
319					regulator-suspend-microvolt = <1000000>;
320				};
321			};
322
323			vcc3v0_pmu: LDO_REG4 {
324				regulator-always-on;
325				regulator-boot-on;
326				regulator-min-microvolt = <3000000>;
327				regulator-max-microvolt = <3000000>;
328
329				regulator-name = "vcc3v0_pmu";
330				regulator-state-mem {
331					regulator-on-in-suspend;
332					regulator-suspend-microvolt = <3000000>;
333
334				};
335			};
336
337			vccio_sd: LDO_REG5 {
338				regulator-always-on;
339				regulator-boot-on;
340				regulator-min-microvolt = <1800000>;
341				regulator-max-microvolt = <3300000>;
342
343				regulator-name = "vccio_sd";
344				regulator-state-mem {
345					regulator-on-in-suspend;
346					regulator-suspend-microvolt = <3300000>;
347				};
348			};
349
350			vcc_sd: LDO_REG6 {
351				regulator-min-microvolt = <3300000>;
352				regulator-max-microvolt = <3300000>;
353
354				regulator-name = "vcc_sd";
355				regulator-state-mem {
356					regulator-on-in-suspend;
357					regulator-suspend-microvolt = <3300000>;
358
359				};
360			};
361
362			vcc2v8_dvp: LDO_REG7 {
363				regulator-min-microvolt = <2800000>;
364				regulator-max-microvolt = <2800000>;
365
366				regulator-name = "vcc2v8_dvp";
367				regulator-state-mem {
368					regulator-off-in-suspend;
369					regulator-suspend-microvolt = <2800000>;
370				};
371			};
372
373			vcc1v8_dvp: LDO_REG8 {
374				regulator-min-microvolt = <1800000>;
375				regulator-max-microvolt = <1800000>;
376
377				regulator-name = "vcc1v8_dvp";
378				regulator-state-mem {
379					regulator-on-in-suspend;
380					regulator-suspend-microvolt = <1800000>;
381				};
382			};
383
384			vdd1v5_dvp: LDO_REG9 {
385				regulator-min-microvolt = <1500000>;
386				regulator-max-microvolt = <1500000>;
387
388				regulator-name = "vdd1v5_dvp";
389				regulator-state-mem {
390					regulator-off-in-suspend;
391					regulator-suspend-microvolt = <1500000>;
392				};
393			};
394
395			dcdc_boost: BOOST {
396				regulator-always-on;
397				regulator-boot-on;
398				regulator-min-microvolt = <4700000>;
399				regulator-max-microvolt = <5400000>;
400				regulator-name = "boost";
401			};
402
403			otg_switch: OTG_SWITCH {
404				regulator-name = "otg_switch";
405			};
406		};
407
408		battery {
409			compatible = "rk817,battery";
410			ocv_table = <3500 3625 3685 3697 3718 3735 3748
411			3760 3774 3788 3802 3816 3834 3853
412			3877 3908 3946 3975 4018 4071 4106>;
413			design_capacity = <2500>;
414			design_qmax = <2750>;
415			bat_res = <100>;
416			sleep_enter_current = <300>;
417			sleep_exit_current = <300>;
418			sleep_filter_current = <100>;
419			power_off_thresd = <3500>;
420			zero_algorithm_vol = <3850>;
421			max_soc_offset = <60>;
422			monitor_sec = <5>;
423			sample_res = <10>;
424			virtual_power = <1>;
425		};
426
427		charger {
428			compatible = "rk817,charger";
429			min_input_voltage = <4500>;
430			max_input_current = <1500>;
431			max_chrg_current = <2000>;
432			max_chrg_voltage = <4200>;
433			chrg_term_mode = <0>;
434			chrg_finish_cur = <300>;
435			virtual_power = <0>;
436			dc_det_adc = <0>;
437			extcon = <&u2phy>;
438		};
439
440		rk817_codec: codec {
441			#sound-dai-cells = <0>;
442			compatible = "rockchip,rk817-codec";
443			clocks = <&cru SCLK_I2S1_OUT>;
444			clock-names = "mclk";
445			pinctrl-names = "default";
446			pinctrl-0 = <&i2s1_2ch_mclk>;
447			hp-volume = <20>;
448			spk-volume = <3>;
449			status = "okay";
450		};
451	};
452};
453
454&i2c2 {
455	status = "okay";
456	clock-frequency = <400000>;
457
458	/* 24M mclk is shared for multiple cameras */
459	pinctrl-0 = <&i2c2_xfer &cif_clkout_m0>;
460
461	/* These are relatively safe rise/fall times; TODO: measure */
462	i2c-scl-falling-time-ns = <50>;
463	i2c-scl-rising-time-ns = <300>;
464
465	gc2155: gc2155@3c {
466		compatible = "gc,gc2155";
467		reg = <0x3c>;
468		pinctrl-names = "default";
469		pinctrl-0 = <&cif_pin_m0>;
470
471		clocks = <&cru SCLK_CIF_OUT>;
472		clock-names = "xvclk";
473
474		avdd-supply = <&vcc2v8_dvp>;
475		dovdd-supply = <&vcc1v8_dvp>;
476		dvdd-supply = <&vcc1v8_dvp>;
477
478		/* hw changed the pwdn to gpio2_b5 */
479		pwdn-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
480
481		port {
482			gc2155_out: endpoint {
483				remote-endpoint = <&cif_in>;
484			};
485		};
486	};
487
488	ov5695: ov5695@36 {
489		compatible = "ovti,ov5695";
490		reg = <0x36>;
491
492		clocks = <&cru SCLK_CIF_OUT>;
493		clock-names = "xvclk";
494
495		avdd-supply = <&vcc2v8_dvp>;
496		dovdd-supply = <&vcc1v8_dvp>;
497		dvdd-supply = <&vcc1v8_dvp>;
498
499		/*reset-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;*/
500		pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;
501
502		port {
503			ucam_out: endpoint {
504				remote-endpoint = <&mipi_in_ucam>;
505				data-lanes = <1 2>;
506			};
507		};
508	};
509};
510
511&i2s1_2ch {
512	status = "okay";
513	#sound-dai-cells = <0>;
514};
515
516&io_domains {
517	status = "okay";
518
519	vccio1-supply = <&vcc1v8_soc>;
520	vccio2-supply = <&vccio_sd>;
521	vccio3-supply = <&vcc1v8_dvp>;
522	vccio4-supply = <&vcc_3v0>;
523	vccio5-supply = <&vcc_3v0>;
524};
525
526&isp_mmu {
527	status = "okay";
528};
529
530&mipi_dphy_rx0 {
531	status = "okay";
532
533	ports {
534		#address-cells = <1>;
535		#size-cells = <0>;
536
537		port@0 {
538			reg = <0>;
539			#address-cells = <1>;
540			#size-cells = <0>;
541
542			mipi_in_ucam: endpoint@1 {
543				reg = <1>;
544				remote-endpoint = <&ucam_out>;
545				data-lanes = <1 2>;
546			};
547		};
548
549		port@1 {
550			reg = <1>;
551			#address-cells = <1>;
552			#size-cells = <0>;
553
554			dphy_rx0_out: endpoint@0 {
555				reg = <0>;
556				remote-endpoint = <&isp0_mipi_in>;
557			};
558		};
559	};
560};
561
562&nandc0 {
563	status = "okay";
564};
565
566&rkisp1 {
567	status = "okay";
568
569	port {
570		#address-cells = <1>;
571		#size-cells = <0>;
572
573		isp0_mipi_in: endpoint@0 {
574			reg = <0>;
575			remote-endpoint = <&dphy_rx0_out>;
576		};
577	};
578};
579
580&pmu_io_domains {
581	status = "okay";
582
583	pmuio1-supply = <&vcc3v0_pmu>;
584	pmuio2-supply = <&vcc3v0_pmu>;
585};
586
587&rk_rga {
588	status = "okay";
589};
590
591&saradc {
592	status = "okay";
593	vref-supply = <&vcc1v8_soc>;
594};
595
596&sdmmc {
597	bus-width = <4>;
598	cap-mmc-highspeed;
599	cap-sd-highspeed;
600	no-sdio;
601	no-mmc;
602	card-detect-delay = <800>;
603	ignore-pm-notify;
604	/*cd-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; [> CD GPIO <]*/
605	sd-uhs-sdr12;
606	sd-uhs-sdr25;
607	sd-uhs-sdr50;
608	sd-uhs-sdr104;
609	vqmmc-supply = <&vccio_sd>;
610	vmmc-supply = <&vcc_sd>;
611	status = "disabled";
612};
613
614&sdio {
615	bus-width = <4>;
616	cap-sd-highspeed;
617	no-sd;
618	no-mmc;
619	ignore-pm-notify;
620	keep-power-in-suspend;
621	non-removable;
622	mmc-pwrseq = <&sdio_pwrseq>;
623	sd-uhs-sdr104;
624	status = "okay";
625};
626
627&tsadc {
628	pinctrl-names = "init", "default";
629	pinctrl-0 = <&tsadc_otp_gpio>;
630	pinctrl-1 = <&tsadc_otp_out>;
631	status = "okay";
632};
633
634&u2phy {
635	status = "okay";
636
637	u2phy_host: host-port {
638		status = "okay";
639	};
640
641	u2phy_otg: otg-port {
642		status = "okay";
643	};
644};
645
646&usb20_otg {
647	status = "okay";
648};
649
650&uart1 {
651	pinctrl-names = "default";
652	pinctrl-0 = <&uart1_xfer &uart1_cts>;
653	status = "okay";
654};
655
656&vip_mmu {
657	status = "okay";
658};
659
660&mpp_srv {
661	status = "okay";
662};
663
664&vdpu {
665	status = "okay";
666};
667
668&vepu {
669	status = "okay";
670};
671
672&vpu_mmu {
673	status = "okay";
674};
675
676&hevc {
677	status = "okay";
678};
679
680&hevc_mmu {
681	status = "okay";
682};
683
684&pinctrl {
685	cif-pin-m0 {
686		cif_pin_m0: cif-pin-m0 {
687			rockchip,pins =
688				<2 RK_PA0 1 &pcfg_pull_none>,/* cif_data2 */
689				<2 RK_PA1 1 &pcfg_pull_none>,/* cif_data3 */
690				<2 RK_PA2 1 &pcfg_pull_none>,/* cif_data4 */
691				<2 RK_PA3 1 &pcfg_pull_none>,/* cif_data5 */
692				<2 RK_PA4 1 &pcfg_pull_none>,/* cif_data6 */
693				<2 RK_PA5 1 &pcfg_pull_none>,/* cif_data7 */
694				<2 RK_PA6 1 &pcfg_pull_none>,/* cif_data8 */
695				<2 RK_PA7 1 &pcfg_pull_none>,/* cif_data9 */
696				<2 RK_PB0 1 &pcfg_pull_none>,/* cif_sync */
697				<2 RK_PB1 1 &pcfg_pull_none>,/* cif_href */
698				<2 RK_PB2 1 &pcfg_pull_none>;/* cif_clkin */
699		};
700
701		cif_pin_m1: cif-pin-m1 {
702			rockchip,pins =
703				<3 RK_PA3 3 &pcfg_pull_none>,/* cif_data2 */
704				<3 RK_PA5 3 &pcfg_pull_none>,/* cif_data3 */
705				<3 RK_PA7 3 &pcfg_pull_none>,/* cif_data4 */
706				<3 RK_PB0 3 &pcfg_pull_none>,/* cif_data5 */
707				<3 RK_PB1 3 &pcfg_pull_none>,/* cif_data6 */
708				<3 RK_PB4 3 &pcfg_pull_none>,/* cif_data7 */
709				<3 RK_PB6 3 &pcfg_pull_none>,/* cif_data8 */
710				<3 RK_PB7 3 &pcfg_pull_none>,/* cif_data9 */
711				<3 RK_PD1 3 &pcfg_pull_none>,/* cif_sync */
712				<3 RK_PD2 3 &pcfg_pull_none>,/* cif_href */
713				<3 RK_PD3 3 &pcfg_pull_none>;/* cif_clkin */
714		};
715	};
716
717	pmic {
718		pmic_int: pmic_int {
719			rockchip,pins =
720				<0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
721		};
722
723		soc_slppin_gpio: soc_slppin_gpio {
724			rockchip,pins =
725				<0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
726		};
727
728		soc_slppin_slp: soc_slppin_slp {
729			rockchip,pins =
730				<0 RK_PA4 1 &pcfg_pull_none>;
731		};
732
733		soc_slppin_rst: soc_slppin_rst {
734			rockchip,pins =
735				<0 RK_PA4 2 &pcfg_pull_none>;
736		};
737	};
738
739	sdio-pwrseq {
740		wifi_enable_h: wifi-enable-h {
741			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
742		};
743	};
744};
745
746/* DON'T PUT ANYTHING BELOW HERE.  PUT IT ABOVE PINCTRL */
747/* DON'T PUT ANYTHING BELOW HERE.  PUT IT ABOVE PINCTRL */
748/* DON'T PUT ANYTHING BELOW HERE.  PUT IT ABOVE PINCTRL */
749