1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include "px30.dtsi" 7 8/ { 9 compatible = "rockchip,linux", "rockchip,px30-robot"; 10 11 chosen { 12 bootargs = "console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootwait"; 13 }; 14 15 fiq-debugger { 16 compatible = "rockchip,fiq-debugger"; 17 rockchip,serial-id = <2>; 18 rockchip,wake-irq = <0>; 19 /* If enable uart uses irq instead of fiq */ 20 rockchip,irq-mode-enable = <1>; 21 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 22 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 23 pinctrl-names = "default"; 24 pinctrl-0 = <&uart2m0_xfer>; 25 status = "okay"; 26 }; 27 28 reserved-memory { 29 #address-cells = <2>; 30 #size-cells = <2>; 31 ranges; 32 33 ramoops: ramoops@8000000 { 34 compatible = "ramoops"; 35 reg = <0x0 0x8000000 0x0 0xa0000>; 36 record-size = <0x20000>; 37 console-size = <0x80000>; 38 ftrace-size = <0x00000>; 39 pmsg-size = <0x00000>; 40 }; 41 }; 42}; 43 44&cpu0_opp_table { 45 /delete-node/ opp-1248000000; 46 /delete-node/ opp-1296000000; 47 /delete-node/ opp-1416000000; 48 /delete-node/ opp-1512000000; 49}; 50 51&dmc_opp_table { 52 /delete-node/ opp-666000000; 53 /delete-node/ opp-768000000; 54}; 55 56&i2s1_2ch { 57 rockchip,playback-only; 58}; 59 60&rng { 61 status = "okay"; 62}; 63 64&soc_thermal { 65 trips { 66 threshold: trip-point-0 { 67 temperature = <75000>; 68 hysteresis = <2000>; 69 type = "passive"; 70 }; 71 target: trip-point-1 { 72 temperature = <90000>; 73 hysteresis = <2000>; 74 type = "passive"; 75 }; 76 soc_crit: soc-crit { 77 temperature = <115000>; 78 hysteresis = <2000>; 79 type = "critical"; 80 }; 81 }; 82}; 83 84&tsadc { 85 pinctrl-names = "gpio", "otpout"; 86 pinctrl-0 = <&tsadc_otp_gpio>; 87 pinctrl-1 = <&tsadc_otp_out>; 88 status = "okay"; 89}; 90 91&uart2 { 92 status = "disabled"; 93}; 94