1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 8*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h> 9*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 10*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h> 11*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h> 12*4882a593Smuzhiyun#include "px30.dtsi" 13*4882a593Smuzhiyun#include "px30-android.dtsi" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/ { 16*4882a593Smuzhiyun model = "Rockchip PX30 AD D6 board"; 17*4882a593Smuzhiyun compatible = "rockchip,px30-ad-d6", "rockchip,px30"; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun dvdd12_anx: dvdd12-anx { 20*4882a593Smuzhiyun compatible = "regulator-fixed"; 21*4882a593Smuzhiyun regulator-name = "dvdd12-anx"; 22*4882a593Smuzhiyun regulator-boot-on; 23*4882a593Smuzhiyun gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; 24*4882a593Smuzhiyun enable-active-high; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun regulator-state-mem { 27*4882a593Smuzhiyun regulator-off-in-suspend; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun adc-keys { 32*4882a593Smuzhiyun compatible = "adc-keys"; 33*4882a593Smuzhiyun io-channels = <&saradc 2>; 34*4882a593Smuzhiyun io-channel-names = "buttons"; 35*4882a593Smuzhiyun poll-interval = <100>; 36*4882a593Smuzhiyun keyup-threshold-microvolt = <1800000>; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun esc-key { 39*4882a593Smuzhiyun linux,code = <KEY_ESC>; 40*4882a593Smuzhiyun label = "esc"; 41*4882a593Smuzhiyun press-threshold-microvolt = <1310000>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun home-key { 45*4882a593Smuzhiyun linux,code = <KEY_HOME>; 46*4882a593Smuzhiyun label = "home"; 47*4882a593Smuzhiyun press-threshold-microvolt = <624000>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun menu-key { 51*4882a593Smuzhiyun linux,code = <KEY_MENU>; 52*4882a593Smuzhiyun label = "menu"; 53*4882a593Smuzhiyun press-threshold-microvolt = <987000>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun vol-down-key { 57*4882a593Smuzhiyun linux,code = <KEY_VOLUMEDOWN>; 58*4882a593Smuzhiyun label = "volume down"; 59*4882a593Smuzhiyun press-threshold-microvolt = <300000>; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun vol-up-key { 63*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 64*4882a593Smuzhiyun label = "volume up"; 65*4882a593Smuzhiyun press-threshold-microvolt = <17000>; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun backlight: backlight { 70*4882a593Smuzhiyun compatible = "pwm-backlight"; 71*4882a593Smuzhiyun pwms = <&pwm1 0 25000 0>; 72*4882a593Smuzhiyun brightness-levels = < 73*4882a593Smuzhiyun 0 1 2 3 4 5 6 7 74*4882a593Smuzhiyun 8 9 10 11 12 13 14 15 75*4882a593Smuzhiyun 16 17 18 19 20 21 22 23 76*4882a593Smuzhiyun 24 25 26 27 28 29 30 31 77*4882a593Smuzhiyun 32 33 34 35 36 37 38 39 78*4882a593Smuzhiyun 40 41 42 43 44 45 46 47 79*4882a593Smuzhiyun 48 49 50 51 52 53 54 55 80*4882a593Smuzhiyun 56 57 58 59 60 61 62 63 81*4882a593Smuzhiyun 64 65 66 67 68 69 70 71 82*4882a593Smuzhiyun 72 73 74 75 76 77 78 79 83*4882a593Smuzhiyun 80 81 82 83 84 85 86 87 84*4882a593Smuzhiyun 88 89 90 91 92 93 94 95 85*4882a593Smuzhiyun 96 97 98 99 100 101 102 103 86*4882a593Smuzhiyun 104 105 106 107 108 109 110 111 87*4882a593Smuzhiyun 112 113 114 115 116 117 118 119 88*4882a593Smuzhiyun 120 121 122 123 124 125 126 127 89*4882a593Smuzhiyun 128 129 130 131 132 133 134 135 90*4882a593Smuzhiyun 136 137 138 139 140 141 142 143 91*4882a593Smuzhiyun 144 145 146 147 148 149 150 151 92*4882a593Smuzhiyun 152 153 154 155 156 157 158 159 93*4882a593Smuzhiyun 160 161 162 163 164 165 166 167 94*4882a593Smuzhiyun 168 169 170 171 172 173 174 175 95*4882a593Smuzhiyun 176 177 178 179 180 181 182 183 96*4882a593Smuzhiyun 184 185 186 187 188 189 190 191 97*4882a593Smuzhiyun 192 193 194 195 196 197 198 199 98*4882a593Smuzhiyun 200 201 202 203 204 205 206 207 99*4882a593Smuzhiyun 208 209 210 211 212 213 214 215 100*4882a593Smuzhiyun 216 217 218 219 220 221 222 223 101*4882a593Smuzhiyun 224 225 226 227 228 229 230 231 102*4882a593Smuzhiyun 232 233 234 235 236 237 238 239 103*4882a593Smuzhiyun 240 241 242 243 244 245 246 247 104*4882a593Smuzhiyun 248 249 250 251 252 253 254 255>; 105*4882a593Smuzhiyun default-brightness-level = <200>; 106*4882a593Smuzhiyun enable-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun sdio_pwrseq: sdio-pwrseq { 110*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 111*4882a593Smuzhiyun pinctrl-names = "default"; 112*4882a593Smuzhiyun pinctrl-0 = <&wifi_enable_h>; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* 115*4882a593Smuzhiyun * On the module itself this is one of these (depending 116*4882a593Smuzhiyun * on the actual card populated): 117*4882a593Smuzhiyun * - SDIO_RESET_L_WL_REG_ON 118*4882a593Smuzhiyun * - PDN (power down when low) 119*4882a593Smuzhiyun */ 120*4882a593Smuzhiyun reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun vcc_phy: vcc-phy-regulator { 124*4882a593Smuzhiyun compatible = "regulator-fixed"; 125*4882a593Smuzhiyun regulator-name = "vcc_phy"; 126*4882a593Smuzhiyun regulator-always-on; 127*4882a593Smuzhiyun regulator-boot-on; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun vcc5v0_sys: vccsys { 131*4882a593Smuzhiyun compatible = "regulator-fixed"; 132*4882a593Smuzhiyun regulator-name = "vcc5v0_sys"; 133*4882a593Smuzhiyun regulator-always-on; 134*4882a593Smuzhiyun regulator-boot-on; 135*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 136*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun}; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun&bus_apll { 141*4882a593Smuzhiyun bus-supply = <&vdd_logic>; 142*4882a593Smuzhiyun status = "okay"; 143*4882a593Smuzhiyun}; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun&cpu0 { 146*4882a593Smuzhiyun cpu-supply = <&vdd_arm>; 147*4882a593Smuzhiyun}; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun&dfi { 150*4882a593Smuzhiyun status = "okay"; 151*4882a593Smuzhiyun}; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun&dmc { 154*4882a593Smuzhiyun auto-freq-en = <0>; 155*4882a593Smuzhiyun center-supply = <&vdd_logic>; 156*4882a593Smuzhiyun status = "okay"; 157*4882a593Smuzhiyun}; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun&emmc { 160*4882a593Smuzhiyun bus-width = <8>; 161*4882a593Smuzhiyun cap-mmc-highspeed; 162*4882a593Smuzhiyun mmc-hs200-1_8v; 163*4882a593Smuzhiyun no-sdio; 164*4882a593Smuzhiyun no-sd; 165*4882a593Smuzhiyun disable-wp; 166*4882a593Smuzhiyun non-removable; 167*4882a593Smuzhiyun num-slots = <1>; 168*4882a593Smuzhiyun status = "okay"; 169*4882a593Smuzhiyun}; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun&gpu { 172*4882a593Smuzhiyun mali-supply = <&vdd_logic>; 173*4882a593Smuzhiyun status = "okay"; 174*4882a593Smuzhiyun}; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun&i2c0 { 177*4882a593Smuzhiyun status = "okay"; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun rk809: pmic@20 { 180*4882a593Smuzhiyun compatible = "rockchip,rk809"; 181*4882a593Smuzhiyun reg = <0x20>; 182*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 183*4882a593Smuzhiyun interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 184*4882a593Smuzhiyun pinctrl-names = "default", "pmic-sleep", 185*4882a593Smuzhiyun "pmic-power-off", "pmic-reset"; 186*4882a593Smuzhiyun pinctrl-0 = <&pmic_int>; 187*4882a593Smuzhiyun pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; 188*4882a593Smuzhiyun pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; 189*4882a593Smuzhiyun pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; 190*4882a593Smuzhiyun rockchip,system-power-controller; 191*4882a593Smuzhiyun wakeup-source; 192*4882a593Smuzhiyun #clock-cells = <1>; 193*4882a593Smuzhiyun clock-output-names = "rk808-clkout1", "rk808-clkout2"; 194*4882a593Smuzhiyun pmic-reset-func = <1>; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun vcc1-supply = <&vcc5v0_sys>; 197*4882a593Smuzhiyun vcc2-supply = <&vcc5v0_sys>; 198*4882a593Smuzhiyun vcc3-supply = <&vcc5v0_sys>; 199*4882a593Smuzhiyun vcc4-supply = <&vcc5v0_sys>; 200*4882a593Smuzhiyun vcc5-supply = <&vcc3v3_sys>; 201*4882a593Smuzhiyun vcc6-supply = <&vcc3v3_sys>; 202*4882a593Smuzhiyun vcc7-supply = <&vcc3v3_sys>; 203*4882a593Smuzhiyun vcc8-supply = <&vcc3v3_sys>; 204*4882a593Smuzhiyun vcc9-supply = <&vcc5v0_sys>; 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun pwrkey { 207*4882a593Smuzhiyun status = "okay"; 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun pinctrl_rk8xx: pinctrl_rk8xx { 211*4882a593Smuzhiyun gpio-controller; 212*4882a593Smuzhiyun #gpio-cells = <2>; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun rk817_slppin_null: rk817_slppin_null { 215*4882a593Smuzhiyun pins = "gpio_slp"; 216*4882a593Smuzhiyun function = "pin_fun0"; 217*4882a593Smuzhiyun }; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun rk817_slppin_slp: rk817_slppin_slp { 220*4882a593Smuzhiyun pins = "gpio_slp"; 221*4882a593Smuzhiyun function = "pin_fun1"; 222*4882a593Smuzhiyun }; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun rk817_slppin_pwrdn: rk817_slppin_pwrdn { 225*4882a593Smuzhiyun pins = "gpio_slp"; 226*4882a593Smuzhiyun function = "pin_fun2"; 227*4882a593Smuzhiyun }; 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun rk817_slppin_rst: rk817_slppin_rst { 230*4882a593Smuzhiyun pins = "gpio_slp"; 231*4882a593Smuzhiyun function = "pin_fun3"; 232*4882a593Smuzhiyun }; 233*4882a593Smuzhiyun }; 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun regulators { 236*4882a593Smuzhiyun vdd_logic: DCDC_REG1 { 237*4882a593Smuzhiyun regulator-always-on; 238*4882a593Smuzhiyun regulator-boot-on; 239*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 240*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 241*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 242*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 243*4882a593Smuzhiyun regulator-name = "vdd_logic"; 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun regulator-state-mem { 246*4882a593Smuzhiyun regulator-on-in-suspend; 247*4882a593Smuzhiyun regulator-suspend-microvolt = <950000>; 248*4882a593Smuzhiyun }; 249*4882a593Smuzhiyun }; 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun vdd_arm: DCDC_REG2 { 252*4882a593Smuzhiyun regulator-always-on; 253*4882a593Smuzhiyun regulator-boot-on; 254*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 255*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 256*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 257*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 258*4882a593Smuzhiyun regulator-name = "vdd_arm"; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun regulator-state-mem { 261*4882a593Smuzhiyun regulator-off-in-suspend; 262*4882a593Smuzhiyun regulator-suspend-microvolt = <950000>; 263*4882a593Smuzhiyun }; 264*4882a593Smuzhiyun }; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun vcc_ddr: DCDC_REG3 { 267*4882a593Smuzhiyun regulator-always-on; 268*4882a593Smuzhiyun regulator-boot-on; 269*4882a593Smuzhiyun regulator-name = "vcc_ddr"; 270*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 271*4882a593Smuzhiyun 272*4882a593Smuzhiyun regulator-state-mem { 273*4882a593Smuzhiyun regulator-on-in-suspend; 274*4882a593Smuzhiyun }; 275*4882a593Smuzhiyun }; 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun vcc_3v0: DCDC_REG4 { 278*4882a593Smuzhiyun regulator-always-on; 279*4882a593Smuzhiyun regulator-boot-on; 280*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 281*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 282*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 283*4882a593Smuzhiyun regulator-name = "vcc_3v0"; 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun regulator-state-mem { 286*4882a593Smuzhiyun regulator-on-in-suspend; 287*4882a593Smuzhiyun regulator-suspend-microvolt = <3000000>; 288*4882a593Smuzhiyun }; 289*4882a593Smuzhiyun }; 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun vcc_1v0: LDO_REG1 { 292*4882a593Smuzhiyun regulator-always-on; 293*4882a593Smuzhiyun regulator-boot-on; 294*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 295*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 296*4882a593Smuzhiyun regulator-name = "vcc_1v0"; 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun regulator-state-mem { 299*4882a593Smuzhiyun regulator-on-in-suspend; 300*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 301*4882a593Smuzhiyun }; 302*4882a593Smuzhiyun }; 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun vcc1v8_soc: LDO_REG2 { 305*4882a593Smuzhiyun regulator-always-on; 306*4882a593Smuzhiyun regulator-boot-on; 307*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 308*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 309*4882a593Smuzhiyun regulator-name = "vcc1v8_soc"; 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun regulator-state-mem { 312*4882a593Smuzhiyun regulator-on-in-suspend; 313*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 314*4882a593Smuzhiyun }; 315*4882a593Smuzhiyun }; 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun vdd1v0_soc: LDO_REG3 { 318*4882a593Smuzhiyun regulator-always-on; 319*4882a593Smuzhiyun regulator-boot-on; 320*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 321*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 322*4882a593Smuzhiyun regulator-name = "vcc1v0_soc"; 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun regulator-state-mem { 325*4882a593Smuzhiyun regulator-on-in-suspend; 326*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 327*4882a593Smuzhiyun }; 328*4882a593Smuzhiyun }; 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun vcc3v0_pmu: LDO_REG4 { 331*4882a593Smuzhiyun regulator-always-on; 332*4882a593Smuzhiyun regulator-boot-on; 333*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 334*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 335*4882a593Smuzhiyun regulator-name = "vcc3v0_pmu"; 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun regulator-state-mem { 338*4882a593Smuzhiyun regulator-on-in-suspend; 339*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 340*4882a593Smuzhiyun 341*4882a593Smuzhiyun }; 342*4882a593Smuzhiyun }; 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun vccio_sd: LDO_REG5 { 345*4882a593Smuzhiyun regulator-always-on; 346*4882a593Smuzhiyun regulator-boot-on; 347*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 348*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 349*4882a593Smuzhiyun regulator-name = "vccio_sd"; 350*4882a593Smuzhiyun 351*4882a593Smuzhiyun regulator-state-mem { 352*4882a593Smuzhiyun regulator-on-in-suspend; 353*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 354*4882a593Smuzhiyun }; 355*4882a593Smuzhiyun }; 356*4882a593Smuzhiyun 357*4882a593Smuzhiyun vcc_sd: LDO_REG6 { 358*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 359*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 360*4882a593Smuzhiyun regulator-name = "vcc_sd"; 361*4882a593Smuzhiyun 362*4882a593Smuzhiyun regulator-state-mem { 363*4882a593Smuzhiyun regulator-on-in-suspend; 364*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun }; 367*4882a593Smuzhiyun }; 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun vcc2v8_dvp: LDO_REG7 { 370*4882a593Smuzhiyun regulator-always-on; 371*4882a593Smuzhiyun regulator-boot-on; 372*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 373*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 374*4882a593Smuzhiyun regulator-name = "vcc2v8_dvp"; 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun regulator-state-mem { 377*4882a593Smuzhiyun regulator-off-in-suspend; 378*4882a593Smuzhiyun regulator-suspend-microvolt = <2800000>; 379*4882a593Smuzhiyun }; 380*4882a593Smuzhiyun }; 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun vcc1v8_dvp: LDO_REG8 { 383*4882a593Smuzhiyun regulator-always-on; 384*4882a593Smuzhiyun regulator-boot-on; 385*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 386*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 387*4882a593Smuzhiyun regulator-name = "vcc1v8_dvp"; 388*4882a593Smuzhiyun 389*4882a593Smuzhiyun regulator-state-mem { 390*4882a593Smuzhiyun regulator-on-in-suspend; 391*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 392*4882a593Smuzhiyun }; 393*4882a593Smuzhiyun }; 394*4882a593Smuzhiyun 395*4882a593Smuzhiyun vdd1v5_dvp: LDO_REG9 { 396*4882a593Smuzhiyun regulator-always-on; 397*4882a593Smuzhiyun regulator-boot-on; 398*4882a593Smuzhiyun regulator-min-microvolt = <1500000>; 399*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 400*4882a593Smuzhiyun regulator-name = "vdd1v5_dvp"; 401*4882a593Smuzhiyun 402*4882a593Smuzhiyun regulator-state-mem { 403*4882a593Smuzhiyun regulator-off-in-suspend; 404*4882a593Smuzhiyun regulator-suspend-microvolt = <1500000>; 405*4882a593Smuzhiyun }; 406*4882a593Smuzhiyun }; 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun vcc3v3_sys: DCDC_REG5 { 409*4882a593Smuzhiyun regulator-always-on; 410*4882a593Smuzhiyun regulator-boot-on; 411*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 412*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 413*4882a593Smuzhiyun regulator-name = "vcc3v3_sys"; 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun regulator-state-mem { 416*4882a593Smuzhiyun regulator-on-in-suspend; 417*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 418*4882a593Smuzhiyun }; 419*4882a593Smuzhiyun }; 420*4882a593Smuzhiyun 421*4882a593Smuzhiyun vcc5v0_host: SWITCH_REG1 { 422*4882a593Smuzhiyun regulator-name = "vcc5v0_host"; 423*4882a593Smuzhiyun }; 424*4882a593Smuzhiyun 425*4882a593Smuzhiyun vcc3v3_lcd: SWITCH_REG2 { 426*4882a593Smuzhiyun regulator-boot-on; 427*4882a593Smuzhiyun regulator-name = "vcc3v3_lcd"; 428*4882a593Smuzhiyun 429*4882a593Smuzhiyun regulator-state-mem { 430*4882a593Smuzhiyun regulator-off-in-suspend; 431*4882a593Smuzhiyun }; 432*4882a593Smuzhiyun }; 433*4882a593Smuzhiyun }; 434*4882a593Smuzhiyun }; 435*4882a593Smuzhiyun}; 436*4882a593Smuzhiyun 437*4882a593Smuzhiyun&io_domains { 438*4882a593Smuzhiyun vccio1-supply = <&vcc1v8_soc>; 439*4882a593Smuzhiyun vccio2-supply = <&vccio_sd>; 440*4882a593Smuzhiyun vccio3-supply = <&vcc_3v0>; 441*4882a593Smuzhiyun vccio4-supply = <&vcc3v0_pmu>; 442*4882a593Smuzhiyun vccio5-supply = <&vcc_3v0>; 443*4882a593Smuzhiyun status = "okay"; 444*4882a593Smuzhiyun}; 445*4882a593Smuzhiyun 446*4882a593Smuzhiyun&nandc0 { 447*4882a593Smuzhiyun status = "okay"; 448*4882a593Smuzhiyun}; 449*4882a593Smuzhiyun 450*4882a593Smuzhiyun&pmu_io_domains { 451*4882a593Smuzhiyun pmuio1-supply = <&vcc3v0_pmu>; 452*4882a593Smuzhiyun pmuio2-supply = <&vcc3v0_pmu>; 453*4882a593Smuzhiyun status = "okay"; 454*4882a593Smuzhiyun}; 455*4882a593Smuzhiyun 456*4882a593Smuzhiyun&pwm1 { 457*4882a593Smuzhiyun status = "okay"; 458*4882a593Smuzhiyun}; 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun&rk_rga { 461*4882a593Smuzhiyun status = "okay"; 462*4882a593Smuzhiyun}; 463*4882a593Smuzhiyun 464*4882a593Smuzhiyun&rockchip_suspend { 465*4882a593Smuzhiyun rockchip,sleep-debug-en = <1>; 466*4882a593Smuzhiyun status = "okay"; 467*4882a593Smuzhiyun}; 468*4882a593Smuzhiyun 469*4882a593Smuzhiyun&saradc { 470*4882a593Smuzhiyun vref-supply = <&vcc1v8_soc>; 471*4882a593Smuzhiyun status = "okay"; 472*4882a593Smuzhiyun}; 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun&sdmmc { 475*4882a593Smuzhiyun bus-width = <4>; 476*4882a593Smuzhiyun cap-mmc-highspeed; 477*4882a593Smuzhiyun cap-sd-highspeed; 478*4882a593Smuzhiyun no-sdio; 479*4882a593Smuzhiyun no-mmc; 480*4882a593Smuzhiyun card-detect-delay = <800>; 481*4882a593Smuzhiyun ignore-pm-notify; 482*4882a593Smuzhiyun sd-uhs-sdr12; 483*4882a593Smuzhiyun sd-uhs-sdr25; 484*4882a593Smuzhiyun sd-uhs-sdr50; 485*4882a593Smuzhiyun sd-uhs-sdr104; 486*4882a593Smuzhiyun vqmmc-supply = <&vccio_sd>; 487*4882a593Smuzhiyun vmmc-supply = <&vcc_sd>; 488*4882a593Smuzhiyun status = "okay"; 489*4882a593Smuzhiyun}; 490*4882a593Smuzhiyun 491*4882a593Smuzhiyun&sdio { 492*4882a593Smuzhiyun bus-width = <4>; 493*4882a593Smuzhiyun cap-sd-highspeed; 494*4882a593Smuzhiyun no-sd; 495*4882a593Smuzhiyun no-mmc; 496*4882a593Smuzhiyun ignore-pm-notify; 497*4882a593Smuzhiyun keep-power-in-suspend; 498*4882a593Smuzhiyun non-removable; 499*4882a593Smuzhiyun mmc-pwrseq = <&sdio_pwrseq>; 500*4882a593Smuzhiyun sd-uhs-sdr104; 501*4882a593Smuzhiyun status = "okay"; 502*4882a593Smuzhiyun}; 503*4882a593Smuzhiyun 504*4882a593Smuzhiyun&tsadc { 505*4882a593Smuzhiyun pinctrl-names = "init", "default"; 506*4882a593Smuzhiyun pinctrl-0 = <&tsadc_otp_gpio>; 507*4882a593Smuzhiyun pinctrl-1 = <&tsadc_otp_out>; 508*4882a593Smuzhiyun status = "okay"; 509*4882a593Smuzhiyun}; 510*4882a593Smuzhiyun 511*4882a593Smuzhiyun&uart1 { 512*4882a593Smuzhiyun pinctrl-names = "default"; 513*4882a593Smuzhiyun pinctrl-0 = <&uart1_xfer &uart1_cts>; 514*4882a593Smuzhiyun status = "okay"; 515*4882a593Smuzhiyun}; 516*4882a593Smuzhiyun 517*4882a593Smuzhiyun&u2phy { 518*4882a593Smuzhiyun status = "okay"; 519*4882a593Smuzhiyun 520*4882a593Smuzhiyun u2phy_host: host-port { 521*4882a593Smuzhiyun status = "okay"; 522*4882a593Smuzhiyun }; 523*4882a593Smuzhiyun 524*4882a593Smuzhiyun u2phy_otg: otg-port { 525*4882a593Smuzhiyun status = "okay"; 526*4882a593Smuzhiyun }; 527*4882a593Smuzhiyun}; 528*4882a593Smuzhiyun 529*4882a593Smuzhiyun&usb20_otg { 530*4882a593Smuzhiyun status = "okay"; 531*4882a593Smuzhiyun}; 532*4882a593Smuzhiyun 533*4882a593Smuzhiyun&usb_host0_ehci { 534*4882a593Smuzhiyun status = "okay"; 535*4882a593Smuzhiyun}; 536*4882a593Smuzhiyun 537*4882a593Smuzhiyun&usb_host0_ohci { 538*4882a593Smuzhiyun status = "okay"; 539*4882a593Smuzhiyun}; 540*4882a593Smuzhiyun 541*4882a593Smuzhiyun&display_subsystem { 542*4882a593Smuzhiyun status = "okay"; 543*4882a593Smuzhiyun}; 544*4882a593Smuzhiyun 545*4882a593Smuzhiyun&vopb { 546*4882a593Smuzhiyun status = "okay"; 547*4882a593Smuzhiyun}; 548*4882a593Smuzhiyun 549*4882a593Smuzhiyun&vopb_mmu { 550*4882a593Smuzhiyun status = "okay"; 551*4882a593Smuzhiyun}; 552*4882a593Smuzhiyun 553*4882a593Smuzhiyun&vopl { 554*4882a593Smuzhiyun status = "okay"; 555*4882a593Smuzhiyun}; 556*4882a593Smuzhiyun 557*4882a593Smuzhiyun&vopl_mmu { 558*4882a593Smuzhiyun status = "okay"; 559*4882a593Smuzhiyun}; 560*4882a593Smuzhiyun 561*4882a593Smuzhiyun&mpp_srv { 562*4882a593Smuzhiyun status = "okay"; 563*4882a593Smuzhiyun}; 564*4882a593Smuzhiyun 565*4882a593Smuzhiyun&vdpu { 566*4882a593Smuzhiyun status = "okay"; 567*4882a593Smuzhiyun}; 568*4882a593Smuzhiyun 569*4882a593Smuzhiyun&vepu { 570*4882a593Smuzhiyun status = "okay"; 571*4882a593Smuzhiyun}; 572*4882a593Smuzhiyun 573*4882a593Smuzhiyun&vpu_mmu { 574*4882a593Smuzhiyun status = "okay"; 575*4882a593Smuzhiyun}; 576*4882a593Smuzhiyun 577*4882a593Smuzhiyun&hevc { 578*4882a593Smuzhiyun status = "okay"; 579*4882a593Smuzhiyun}; 580*4882a593Smuzhiyun 581*4882a593Smuzhiyun&hevc_mmu { 582*4882a593Smuzhiyun status = "okay"; 583*4882a593Smuzhiyun}; 584*4882a593Smuzhiyun 585*4882a593Smuzhiyun&i2c1 { 586*4882a593Smuzhiyun status = "okay"; 587*4882a593Smuzhiyun 588*4882a593Smuzhiyun anx6345@38 { 589*4882a593Smuzhiyun compatible = "analogix,anx6345"; 590*4882a593Smuzhiyun reg = <0x38>; 591*4882a593Smuzhiyun reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; 592*4882a593Smuzhiyun panel-supply = <&vcc3v3_lcd>; 593*4882a593Smuzhiyun dvdd25-supply = <&vcc3v3_lcd>; 594*4882a593Smuzhiyun dvdd12-supply = <&dvdd12_anx>; 595*4882a593Smuzhiyun 596*4882a593Smuzhiyun ports { 597*4882a593Smuzhiyun #address-cells = <1>; 598*4882a593Smuzhiyun #size-cells = <0>; 599*4882a593Smuzhiyun 600*4882a593Smuzhiyun port@0 { 601*4882a593Smuzhiyun reg = <0>; 602*4882a593Smuzhiyun 603*4882a593Smuzhiyun anx6345_in_rgb: endpoint { 604*4882a593Smuzhiyun remote-endpoint = <&rgb_out_anx6345>; 605*4882a593Smuzhiyun }; 606*4882a593Smuzhiyun }; 607*4882a593Smuzhiyun }; 608*4882a593Smuzhiyun }; 609*4882a593Smuzhiyun}; 610*4882a593Smuzhiyun 611*4882a593Smuzhiyun&rgb { 612*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 613*4882a593Smuzhiyun pinctrl-0 = <&lcdc_rgb_pins>; 614*4882a593Smuzhiyun pinctrl-1 = <&lcdc_sleep_pins>; 615*4882a593Smuzhiyun status = "okay"; 616*4882a593Smuzhiyun 617*4882a593Smuzhiyun ports { 618*4882a593Smuzhiyun port@1 { 619*4882a593Smuzhiyun reg = <1>; 620*4882a593Smuzhiyun 621*4882a593Smuzhiyun rgb_out_anx6345: endpoint { 622*4882a593Smuzhiyun remote-endpoint = <&anx6345_in_rgb>; 623*4882a593Smuzhiyun }; 624*4882a593Smuzhiyun }; 625*4882a593Smuzhiyun }; 626*4882a593Smuzhiyun}; 627*4882a593Smuzhiyun 628*4882a593Smuzhiyun&rgb_in_vopb { 629*4882a593Smuzhiyun status = "okay"; 630*4882a593Smuzhiyun}; 631*4882a593Smuzhiyun 632*4882a593Smuzhiyun&rgb_in_vopl { 633*4882a593Smuzhiyun status = "disabled"; 634*4882a593Smuzhiyun}; 635*4882a593Smuzhiyun 636*4882a593Smuzhiyun&route_rgb { 637*4882a593Smuzhiyun connect = <&vopb_out_rgb>; 638*4882a593Smuzhiyun status = "okay"; 639*4882a593Smuzhiyun}; 640*4882a593Smuzhiyun 641*4882a593Smuzhiyun&pinctrl { 642*4882a593Smuzhiyun lcdc { 643*4882a593Smuzhiyun lcdc_rgb_pins: lcdc-rgb-pins { 644*4882a593Smuzhiyun rockchip,pins = 645*4882a593Smuzhiyun <3 RK_PA0 1 &pcfg_pull_none_8ma>, /* LCDC_DCLK */ 646*4882a593Smuzhiyun <3 RK_PA1 1 &pcfg_pull_none_8ma>, /* LCDC_HSYNC */ 647*4882a593Smuzhiyun <3 RK_PA2 1 &pcfg_pull_none_8ma>, /* LCDC_VSYNC */ 648*4882a593Smuzhiyun <3 RK_PA3 1 &pcfg_pull_none_8ma>, /* LCDC_DEN */ 649*4882a593Smuzhiyun <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* LCDC_D23 */ 650*4882a593Smuzhiyun <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* LCDC_D22 */ 651*4882a593Smuzhiyun <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* LCDC_D21 */ 652*4882a593Smuzhiyun <3 RK_PD0 1 &pcfg_pull_none_8ma>, /* LCDC_D20 */ 653*4882a593Smuzhiyun <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* LCDC_D19 */ 654*4882a593Smuzhiyun <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* LCDC_D18 */ 655*4882a593Smuzhiyun <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* LCDC_D17 */ 656*4882a593Smuzhiyun <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* LCDC_D16 */ 657*4882a593Smuzhiyun <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* LCDC_D15 */ 658*4882a593Smuzhiyun <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* LCDC_D14 */ 659*4882a593Smuzhiyun <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* LCDC_D13 */ 660*4882a593Smuzhiyun <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* LCDC_D12 */ 661*4882a593Smuzhiyun <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* LCDC_D11 */ 662*4882a593Smuzhiyun <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* LCDC_D10 */ 663*4882a593Smuzhiyun <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* LCDC_D9 */ 664*4882a593Smuzhiyun <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* LCDC_D8 */ 665*4882a593Smuzhiyun <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* LCDC_D7 */ 666*4882a593Smuzhiyun <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* LCDC_D6 */ 667*4882a593Smuzhiyun <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* LCDC_D5 */ 668*4882a593Smuzhiyun <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* LCDC_D4 */ 669*4882a593Smuzhiyun <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* LCDC_D3 */ 670*4882a593Smuzhiyun <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* LCDC_D2 */ 671*4882a593Smuzhiyun <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* LCDC_D1 */ 672*4882a593Smuzhiyun <3 RK_PA4 1 &pcfg_pull_none_8ma>; /* LCDC_D0 */ 673*4882a593Smuzhiyun }; 674*4882a593Smuzhiyun 675*4882a593Smuzhiyun lcdc_sleep_pins: lcdc-sleep-pins { 676*4882a593Smuzhiyun rockchip,pins = 677*4882a593Smuzhiyun <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DCLK */ 678*4882a593Smuzhiyun <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_HSYNC */ 679*4882a593Smuzhiyun <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_VSYNC */ 680*4882a593Smuzhiyun <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DEN */ 681*4882a593Smuzhiyun <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */ 682*4882a593Smuzhiyun <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */ 683*4882a593Smuzhiyun <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */ 684*4882a593Smuzhiyun <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */ 685*4882a593Smuzhiyun <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */ 686*4882a593Smuzhiyun <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */ 687*4882a593Smuzhiyun <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */ 688*4882a593Smuzhiyun <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */ 689*4882a593Smuzhiyun <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */ 690*4882a593Smuzhiyun <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */ 691*4882a593Smuzhiyun <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */ 692*4882a593Smuzhiyun <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */ 693*4882a593Smuzhiyun <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */ 694*4882a593Smuzhiyun <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */ 695*4882a593Smuzhiyun <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D9 */ 696*4882a593Smuzhiyun <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D8 */ 697*4882a593Smuzhiyun <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D7 */ 698*4882a593Smuzhiyun <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D6 */ 699*4882a593Smuzhiyun <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D5 */ 700*4882a593Smuzhiyun <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D4 */ 701*4882a593Smuzhiyun <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D3 */ 702*4882a593Smuzhiyun <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D2 */ 703*4882a593Smuzhiyun <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D1 */ 704*4882a593Smuzhiyun <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; /* LCDC_D0 */ 705*4882a593Smuzhiyun }; 706*4882a593Smuzhiyun }; 707*4882a593Smuzhiyun 708*4882a593Smuzhiyun pmic { 709*4882a593Smuzhiyun pmic_int: pmic_int { 710*4882a593Smuzhiyun rockchip,pins = 711*4882a593Smuzhiyun <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; 712*4882a593Smuzhiyun }; 713*4882a593Smuzhiyun 714*4882a593Smuzhiyun soc_slppin_gpio: soc_slppin_gpio { 715*4882a593Smuzhiyun rockchip,pins = 716*4882a593Smuzhiyun <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; 717*4882a593Smuzhiyun }; 718*4882a593Smuzhiyun 719*4882a593Smuzhiyun soc_slppin_slp: soc_slppin_slp { 720*4882a593Smuzhiyun rockchip,pins = 721*4882a593Smuzhiyun <0 RK_PA4 1 &pcfg_pull_none>; 722*4882a593Smuzhiyun }; 723*4882a593Smuzhiyun 724*4882a593Smuzhiyun soc_slppin_rst: soc_slppin_rst { 725*4882a593Smuzhiyun rockchip,pins = 726*4882a593Smuzhiyun <0 RK_PA4 2 &pcfg_pull_none>; 727*4882a593Smuzhiyun }; 728*4882a593Smuzhiyun }; 729*4882a593Smuzhiyun 730*4882a593Smuzhiyun sdio-pwrseq { 731*4882a593Smuzhiyun wifi_enable_h: wifi-enable-h { 732*4882a593Smuzhiyun rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; 733*4882a593Smuzhiyun }; 734*4882a593Smuzhiyun }; 735*4882a593Smuzhiyun}; 736*4882a593Smuzhiyun 737*4882a593Smuzhiyun&firmware_android { 738*4882a593Smuzhiyun compatible = "android,firmware"; 739*4882a593Smuzhiyun 740*4882a593Smuzhiyun fstab { 741*4882a593Smuzhiyun compatible = "android,fstab"; 742*4882a593Smuzhiyun 743*4882a593Smuzhiyun system { 744*4882a593Smuzhiyun compatible = "android,system"; 745*4882a593Smuzhiyun dev = "/dev/block/by-name/system"; 746*4882a593Smuzhiyun type = "ext4"; 747*4882a593Smuzhiyun mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; 748*4882a593Smuzhiyun fsmgr_flags = "wait"; 749*4882a593Smuzhiyun }; 750*4882a593Smuzhiyun 751*4882a593Smuzhiyun vendor { 752*4882a593Smuzhiyun compatible = "android,vendor"; 753*4882a593Smuzhiyun dev = "/dev/block/by-name/vendor"; 754*4882a593Smuzhiyun type = "ext4"; 755*4882a593Smuzhiyun mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; 756*4882a593Smuzhiyun fsmgr_flags = "wait"; 757*4882a593Smuzhiyun }; 758*4882a593Smuzhiyun }; 759*4882a593Smuzhiyun}; 760