1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef RKPM_GICV2_H 7*4882a593Smuzhiyun #define RKPM_GICV2_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun struct plat_gicv2_dist_ctx_t { 10*4882a593Smuzhiyun u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; 11*4882a593Smuzhiyun u32 saved_spi_prio[DIV_ROUND_UP(1020, 4)]; 12*4882a593Smuzhiyun u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; 13*4882a593Smuzhiyun u32 saved_spi_grp[DIV_ROUND_UP(1020, 32)]; 14*4882a593Smuzhiyun u32 saved_spi_active[DIV_ROUND_UP(1020, 32)]; 15*4882a593Smuzhiyun u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; 16*4882a593Smuzhiyun u32 saved_gicd_ctrl; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun struct plat_gicv2_cpu_ctx_t { 20*4882a593Smuzhiyun u32 saved_ppi_enable; 21*4882a593Smuzhiyun u32 saved_ppi_active; 22*4882a593Smuzhiyun u32 saved_ppi_conf[DIV_ROUND_UP(32, 16)]; 23*4882a593Smuzhiyun u32 saved_ppi_prio[DIV_ROUND_UP(32, 4)]; 24*4882a593Smuzhiyun u32 saved_ppi_grp; 25*4882a593Smuzhiyun u32 saved_gicc_ctrl; 26*4882a593Smuzhiyun u32 saved_gicc_pmr; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun void rkpm_gicv2_dist_save(void __iomem *dist_base, 30*4882a593Smuzhiyun struct plat_gicv2_dist_ctx_t *ctx); 31*4882a593Smuzhiyun void rkpm_gicv2_dist_restore(void __iomem *dist_base, 32*4882a593Smuzhiyun struct plat_gicv2_dist_ctx_t *ctx); 33*4882a593Smuzhiyun void rkpm_gicv2_cpu_save(void __iomem *dist_base, 34*4882a593Smuzhiyun void __iomem *cpu_base, 35*4882a593Smuzhiyun struct plat_gicv2_cpu_ctx_t *ctx); 36*4882a593Smuzhiyun void rkpm_gicv2_cpu_restore(void __iomem *dist_base, 37*4882a593Smuzhiyun void __iomem *cpu_base, 38*4882a593Smuzhiyun struct plat_gicv2_cpu_ctx_t *ctx); 39*4882a593Smuzhiyun #endif 40