1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 */ 5 6 #ifndef RKPM_GICV2_H 7 #define RKPM_GICV2_H 8 9 struct plat_gicv2_dist_ctx_t { 10 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; 11 u32 saved_spi_prio[DIV_ROUND_UP(1020, 4)]; 12 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; 13 u32 saved_spi_grp[DIV_ROUND_UP(1020, 32)]; 14 u32 saved_spi_active[DIV_ROUND_UP(1020, 32)]; 15 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; 16 u32 saved_gicd_ctrl; 17 }; 18 19 struct plat_gicv2_cpu_ctx_t { 20 u32 saved_ppi_enable; 21 u32 saved_ppi_active; 22 u32 saved_ppi_conf[DIV_ROUND_UP(32, 16)]; 23 u32 saved_ppi_prio[DIV_ROUND_UP(32, 4)]; 24 u32 saved_ppi_grp; 25 u32 saved_gicc_ctrl; 26 u32 saved_gicc_pmr; 27 }; 28 29 void rkpm_gicv2_dist_save(void __iomem *dist_base, 30 struct plat_gicv2_dist_ctx_t *ctx); 31 void rkpm_gicv2_dist_restore(void __iomem *dist_base, 32 struct plat_gicv2_dist_ctx_t *ctx); 33 void rkpm_gicv2_cpu_save(void __iomem *dist_base, 34 void __iomem *cpu_base, 35 struct plat_gicv2_cpu_ctx_t *ctx); 36 void rkpm_gicv2_cpu_restore(void __iomem *dist_base, 37 void __iomem *cpu_base, 38 struct plat_gicv2_cpu_ctx_t *ctx); 39 #endif 40