1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
4 */
5
6 #include <linux/io.h>
7 #include <linux/irqchip/arm-gic.h>
8
9 #include "rkpm_helpers.h"
10 #include "rkpm_gicv2.h"
11
rkpm_gicv2_dist_save(void __iomem * dist_base,struct plat_gicv2_dist_ctx_t * ctx)12 void rkpm_gicv2_dist_save(void __iomem *dist_base,
13 struct plat_gicv2_dist_ctx_t *ctx)
14 {
15 int i;
16 int gic_irqs;
17
18 gic_irqs = readl_relaxed(dist_base + GIC_DIST_CTR) & 0x1f;
19 gic_irqs = (gic_irqs + 1) << 5;
20 if (gic_irqs > 1020)
21 gic_irqs = 1020;
22
23 for (i = 32; i < gic_irqs; i += 4)
24 ctx->saved_spi_target[i >> 2] =
25 readl_relaxed(dist_base + GIC_DIST_TARGET + i);
26
27 for (i = 32; i < gic_irqs; i += 4)
28 ctx->saved_spi_prio[i >> 2] =
29 readl_relaxed(dist_base + GIC_DIST_PRI + i);
30
31 for (i = 32; i < gic_irqs; i += 16)
32 ctx->saved_spi_conf[i >> 4] =
33 readl_relaxed(dist_base + GIC_DIST_CONFIG +
34 (i >> 4 << 2));
35
36 for (i = 32; i < gic_irqs; i += 32)
37 ctx->saved_spi_grp[i >> 5] =
38 readl_relaxed(dist_base + GIC_DIST_IGROUP +
39 (i >> 5 << 2));
40
41 for (i = 32; i < gic_irqs; i += 32)
42 ctx->saved_spi_active[i >> 5] =
43 readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET +
44 (i >> 5 << 2));
45
46 for (i = 32; i < gic_irqs; i += 32)
47 ctx->saved_spi_enable[i >> 5] =
48 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET +
49 (i >> 5 << 2));
50
51 ctx->saved_gicd_ctrl = readl_relaxed(dist_base + GIC_DIST_CTRL);
52 }
53
rkpm_gicv2_dist_restore(void __iomem * dist_base,struct plat_gicv2_dist_ctx_t * ctx)54 void rkpm_gicv2_dist_restore(void __iomem *dist_base,
55 struct plat_gicv2_dist_ctx_t *ctx)
56 {
57 int i = 0;
58 int gic_irqs;
59
60 gic_irqs = readl_relaxed(dist_base + GIC_DIST_CTR) & 0x1f;
61 gic_irqs = (gic_irqs + 1) << 5;
62 if (gic_irqs > 1020)
63 gic_irqs = 1020;
64
65 writel_relaxed(0, dist_base + GIC_DIST_CTRL);
66 dsb(sy);
67
68 for (i = 32; i < gic_irqs; i += 4)
69 writel_relaxed(ctx->saved_spi_target[i >> 2],
70 dist_base + GIC_DIST_TARGET + i);
71
72 for (i = 32; i < gic_irqs; i += 4)
73 writel_relaxed(ctx->saved_spi_prio[i >> 2],
74 dist_base + GIC_DIST_PRI + i);
75
76 for (i = 32; i < gic_irqs; i += 16)
77 writel_relaxed(ctx->saved_spi_conf[i >> 4],
78 dist_base + GIC_DIST_CONFIG + (i >> 4 << 2));
79
80 for (i = 32; i < gic_irqs; i += 32)
81 writel_relaxed(ctx->saved_spi_grp[i >> 5],
82 dist_base + GIC_DIST_IGROUP + (i >> 5 << 2));
83
84 for (i = 32; i < gic_irqs; i += 32) {
85 writel_relaxed(~0U, dist_base + GIC_DIST_ACTIVE_CLEAR + (i >> 5 << 2));
86 dsb(sy);
87 writel_relaxed(ctx->saved_spi_active[i >> 5],
88 dist_base + GIC_DIST_ACTIVE_SET + (i >> 5 << 2));
89 }
90
91 for (i = 32; i < gic_irqs; i += 32) {
92 writel_relaxed(~0U, dist_base + GIC_DIST_ENABLE_CLEAR + (i >> 5 << 2));
93 dsb(sy);
94 writel_relaxed(ctx->saved_spi_enable[i >> 5],
95 dist_base + GIC_DIST_ENABLE_SET + (i >> 5 << 2));
96 }
97
98 dsb(sy);
99
100 writel_relaxed(ctx->saved_gicd_ctrl, dist_base + GIC_DIST_CTRL);
101 dsb(sy);
102 }
103
rkpm_gicv2_cpu_save(void __iomem * dist_base,void __iomem * cpu_base,struct plat_gicv2_cpu_ctx_t * ctx)104 void rkpm_gicv2_cpu_save(void __iomem *dist_base,
105 void __iomem *cpu_base,
106 struct plat_gicv2_cpu_ctx_t *ctx)
107 {
108 int i;
109
110 ctx->saved_ppi_enable =
111 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET);
112
113 ctx->saved_ppi_active =
114 readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET);
115
116 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
117 ctx->saved_ppi_conf[i] =
118 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
119
120 for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
121 ctx->saved_ppi_prio[i] =
122 readl_relaxed(dist_base + GIC_DIST_PRI + i * 4);
123
124 ctx->saved_ppi_grp =
125 readl_relaxed(dist_base + GIC_DIST_IGROUP);
126
127 ctx->saved_gicc_pmr =
128 readl_relaxed(cpu_base + GIC_CPU_PRIMASK);
129 ctx->saved_gicc_ctrl =
130 readl_relaxed(cpu_base + GIC_CPU_CTRL);
131 }
132
rkpm_gicv2_cpu_restore(void __iomem * dist_base,void __iomem * cpu_base,struct plat_gicv2_cpu_ctx_t * ctx)133 void rkpm_gicv2_cpu_restore(void __iomem *dist_base,
134 void __iomem *cpu_base,
135 struct plat_gicv2_cpu_ctx_t *ctx)
136 {
137 int i;
138
139 writel_relaxed(0, cpu_base + GIC_CPU_CTRL);
140 dsb(sy);
141
142 writel_relaxed(~0U, dist_base + GIC_DIST_ENABLE_CLEAR);
143 dsb(sy);
144 writel_relaxed(ctx->saved_ppi_enable, dist_base + GIC_DIST_ENABLE_SET);
145
146 writel_relaxed(~0U, dist_base + GIC_DIST_ACTIVE_CLEAR);
147 dsb(sy);
148 writel_relaxed(ctx->saved_ppi_active, dist_base + GIC_DIST_ACTIVE_SET);
149
150 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
151 writel_relaxed(ctx->saved_ppi_conf[i], dist_base + GIC_DIST_CONFIG + i * 4);
152
153 for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
154 writel_relaxed(ctx->saved_ppi_prio[i], dist_base + GIC_DIST_PRI + i * 4);
155
156 writel_relaxed(ctx->saved_ppi_grp, dist_base + GIC_DIST_IGROUP);
157 writel_relaxed(ctx->saved_gicc_pmr, cpu_base + GIC_CPU_PRIMASK);
158 dsb(sy);
159
160 writel_relaxed(ctx->saved_gicc_ctrl, cpu_base + GIC_CPU_CTRL);
161 dsb(sy);
162 }
163