1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include "rv1126.dtsi" 8*4882a593Smuzhiyun#include "rv1126-ipc.dtsi" 9*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "Rockchip RV1126 SPHERICALIPC DDR3 V10 Board"; 13*4882a593Smuzhiyun compatible = "rockchip,rv1126-sphericalipc-ddr3-v10", "rockchip,rv1126"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun adc-keys { 16*4882a593Smuzhiyun compatible = "adc-keys"; 17*4882a593Smuzhiyun io-channels = <&saradc 0>; 18*4882a593Smuzhiyun io-channel-names = "buttons"; 19*4882a593Smuzhiyun poll-interval = <100>; 20*4882a593Smuzhiyun keyup-threshold-microvolt = <1800000>; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun recovery { 23*4882a593Smuzhiyun label = "Volum_up"; 24*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 25*4882a593Smuzhiyun press-threshold-microvolt = <0>; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun rk809_sound: rk809-sound { 30*4882a593Smuzhiyun compatible = "simple-audio-card"; 31*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 32*4882a593Smuzhiyun simple-audio-card,name = "rockchip,rk809-codec"; 33*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 34*4882a593Smuzhiyun simple-audio-card,widgets = 35*4882a593Smuzhiyun "Microphone", "Mic Jack", 36*4882a593Smuzhiyun "Headphone", "Headphone Jack"; 37*4882a593Smuzhiyun simple-audio-card,routing = 38*4882a593Smuzhiyun "Mic Jack", "MICBIAS1", 39*4882a593Smuzhiyun "IN1P", "Mic Jack", 40*4882a593Smuzhiyun "Headphone Jack", "HPOL", 41*4882a593Smuzhiyun "Headphone Jack", "HPOR"; 42*4882a593Smuzhiyun simple-audio-card,cpu { 43*4882a593Smuzhiyun sound-dai = <&i2s0_8ch>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun simple-audio-card,codec { 46*4882a593Smuzhiyun sound-dai = <&rk809_codec>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun}; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun&csi_dphy0 { 52*4882a593Smuzhiyun status = "okay"; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun ports { 55*4882a593Smuzhiyun #address-cells = <1>; 56*4882a593Smuzhiyun #size-cells = <0>; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun port@0 { 59*4882a593Smuzhiyun reg = <0>; 60*4882a593Smuzhiyun #address-cells = <1>; 61*4882a593Smuzhiyun #size-cells = <0>; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun mipi_in_ucam0: endpoint@1 { 64*4882a593Smuzhiyun reg = <1>; 65*4882a593Smuzhiyun remote-endpoint = <&ucam_out0>; 66*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun port@1 { 71*4882a593Smuzhiyun reg = <1>; 72*4882a593Smuzhiyun #address-cells = <1>; 73*4882a593Smuzhiyun #size-cells = <0>; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun csidphy0_out: endpoint@0 { 76*4882a593Smuzhiyun reg = <0>; 77*4882a593Smuzhiyun remote-endpoint = <&isp_in>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun}; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun&emmc { 85*4882a593Smuzhiyun bus-width = <8>; 86*4882a593Smuzhiyun cap-mmc-highspeed; 87*4882a593Smuzhiyun non-removable; 88*4882a593Smuzhiyun mmc-hs200-1_8v; 89*4882a593Smuzhiyun rockchip,default-sample-phase = <90>; 90*4882a593Smuzhiyun no-sdio; 91*4882a593Smuzhiyun no-sd; 92*4882a593Smuzhiyun /delete-property/ pinctrl-names; 93*4882a593Smuzhiyun /delete-property/ pinctrl-0; 94*4882a593Smuzhiyun status = "okay"; 95*4882a593Smuzhiyun}; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun&gmac { 98*4882a593Smuzhiyun phy-mode = "rmii"; 99*4882a593Smuzhiyun clock_in_out = "output"; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun snps,reset-gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; 102*4882a593Smuzhiyun snps,reset-active-low; 103*4882a593Smuzhiyun snps,reset-delays-us = <0 50000 50000>; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>; 106*4882a593Smuzhiyun assigned-clock-parents = <&cru CLK_GMAC_SRC_M0>, <&cru RMII_MODE_CLK>; 107*4882a593Smuzhiyun assigned-clock-rates = <50000000>; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun pinctrl-names = "default"; 110*4882a593Smuzhiyun pinctrl-0 = <&rmiim0_miim &rgmiim0_rxer &rmiim0_bus2 &rgmiim0_mclkinout_level0>; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun phy-handle = <&phy>; 113*4882a593Smuzhiyun status = "okay"; 114*4882a593Smuzhiyun}; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun&i2c0 { 117*4882a593Smuzhiyun status = "okay"; 118*4882a593Smuzhiyun clock-frequency = <400000>; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun rk809: pmic@20 { 121*4882a593Smuzhiyun compatible = "rockchip,rk809"; 122*4882a593Smuzhiyun reg = <0x20>; 123*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 124*4882a593Smuzhiyun interrupts = <9 IRQ_TYPE_LEVEL_LOW>; 125*4882a593Smuzhiyun pinctrl-names = "default", "pmic-sleep", 126*4882a593Smuzhiyun "pmic-power-off", "pmic-reset"; 127*4882a593Smuzhiyun pinctrl-0 = <&pmic_int>; 128*4882a593Smuzhiyun pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; 129*4882a593Smuzhiyun pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; 130*4882a593Smuzhiyun pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; 131*4882a593Smuzhiyun rockchip,system-power-controller; 132*4882a593Smuzhiyun wakeup-source; 133*4882a593Smuzhiyun #clock-cells = <1>; 134*4882a593Smuzhiyun clock-output-names = "rk808-clkout1", "rk808-clkout2"; 135*4882a593Smuzhiyun /* 0: rst the pmic, 1: rst regs (default in codes) */ 136*4882a593Smuzhiyun pmic-reset-func = <0>; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun vcc1-supply = <&vcc5v0_sys>; 139*4882a593Smuzhiyun vcc2-supply = <&vcc5v0_sys>; 140*4882a593Smuzhiyun vcc3-supply = <&vcc5v0_sys>; 141*4882a593Smuzhiyun vcc4-supply = <&vcc5v0_sys>; 142*4882a593Smuzhiyun vcc5-supply = <&vcc_buck5>; 143*4882a593Smuzhiyun vcc6-supply = <&vcc_buck5>; 144*4882a593Smuzhiyun vcc7-supply = <&vcc5v0_sys>; 145*4882a593Smuzhiyun vcc8-supply = <&vcc3v3_sys>; 146*4882a593Smuzhiyun vcc9-supply = <&vcc5v0_sys>; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun pwrkey { 149*4882a593Smuzhiyun status = "okay"; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun pinctrl_rk8xx: pinctrl_rk8xx { 153*4882a593Smuzhiyun gpio-controller; 154*4882a593Smuzhiyun #gpio-cells = <2>; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /omit-if-no-ref/ 157*4882a593Smuzhiyun rk817_slppin_null: rk817_slppin_null { 158*4882a593Smuzhiyun pins = "gpio_slp"; 159*4882a593Smuzhiyun function = "pin_fun0"; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun /omit-if-no-ref/ 163*4882a593Smuzhiyun rk817_slppin_slp: rk817_slppin_slp { 164*4882a593Smuzhiyun pins = "gpio_slp"; 165*4882a593Smuzhiyun function = "pin_fun1"; 166*4882a593Smuzhiyun }; 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun /omit-if-no-ref/ 169*4882a593Smuzhiyun rk817_slppin_pwrdn: rk817_slppin_pwrdn { 170*4882a593Smuzhiyun pins = "gpio_slp"; 171*4882a593Smuzhiyun function = "pin_fun2"; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun /omit-if-no-ref/ 175*4882a593Smuzhiyun rk817_slppin_rst: rk817_slppin_rst { 176*4882a593Smuzhiyun pins = "gpio_slp"; 177*4882a593Smuzhiyun function = "pin_fun3"; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun regulators { 182*4882a593Smuzhiyun vdd_logic: DCDC_REG1 { 183*4882a593Smuzhiyun regulator-always-on; 184*4882a593Smuzhiyun regulator-boot-on; 185*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 186*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 187*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 188*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 189*4882a593Smuzhiyun regulator-name = "vdd_logic"; 190*4882a593Smuzhiyun regulator-state-mem { 191*4882a593Smuzhiyun regulator-on-in-suspend; 192*4882a593Smuzhiyun regulator-suspend-microvolt = <800000>; 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun vdd_arm: DCDC_REG2 { 197*4882a593Smuzhiyun regulator-always-on; 198*4882a593Smuzhiyun regulator-boot-on; 199*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 200*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 201*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 202*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 203*4882a593Smuzhiyun regulator-name = "vdd_arm"; 204*4882a593Smuzhiyun regulator-state-mem { 205*4882a593Smuzhiyun regulator-off-in-suspend; 206*4882a593Smuzhiyun }; 207*4882a593Smuzhiyun }; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun vcc_ddr: DCDC_REG3 { 210*4882a593Smuzhiyun regulator-always-on; 211*4882a593Smuzhiyun regulator-boot-on; 212*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 213*4882a593Smuzhiyun regulator-name = "vcc_ddr"; 214*4882a593Smuzhiyun regulator-state-mem { 215*4882a593Smuzhiyun regulator-on-in-suspend; 216*4882a593Smuzhiyun }; 217*4882a593Smuzhiyun }; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun vcc3v3_sys: DCDC_REG4 { 220*4882a593Smuzhiyun regulator-always-on; 221*4882a593Smuzhiyun regulator-boot-on; 222*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 223*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 224*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 225*4882a593Smuzhiyun regulator-name = "vcc3v3_sys"; 226*4882a593Smuzhiyun regulator-state-mem { 227*4882a593Smuzhiyun regulator-on-in-suspend; 228*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 229*4882a593Smuzhiyun }; 230*4882a593Smuzhiyun }; 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun vcc_buck5: DCDC_REG5 { 233*4882a593Smuzhiyun regulator-always-on; 234*4882a593Smuzhiyun regulator-boot-on; 235*4882a593Smuzhiyun regulator-min-microvolt = <2200000>; 236*4882a593Smuzhiyun regulator-max-microvolt = <2200000>; 237*4882a593Smuzhiyun regulator-name = "vcc_buck5"; 238*4882a593Smuzhiyun regulator-state-mem { 239*4882a593Smuzhiyun regulator-on-in-suspend; 240*4882a593Smuzhiyun regulator-suspend-microvolt = <2200000>; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun }; 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun vcc_0v8: LDO_REG1 { 245*4882a593Smuzhiyun regulator-always-on; 246*4882a593Smuzhiyun regulator-boot-on; 247*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 248*4882a593Smuzhiyun regulator-max-microvolt = <800000>; 249*4882a593Smuzhiyun regulator-name = "vcc_0v8"; 250*4882a593Smuzhiyun regulator-state-mem { 251*4882a593Smuzhiyun regulator-off-in-suspend; 252*4882a593Smuzhiyun }; 253*4882a593Smuzhiyun }; 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun vcc1v8_pmu: LDO_REG2 { 256*4882a593Smuzhiyun regulator-always-on; 257*4882a593Smuzhiyun regulator-boot-on; 258*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 259*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 260*4882a593Smuzhiyun regulator-name = "vcc1v8_pmu"; 261*4882a593Smuzhiyun regulator-state-mem { 262*4882a593Smuzhiyun regulator-on-in-suspend; 263*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 264*4882a593Smuzhiyun }; 265*4882a593Smuzhiyun }; 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun vdd0v8_pmu: LDO_REG3 { 268*4882a593Smuzhiyun regulator-always-on; 269*4882a593Smuzhiyun regulator-boot-on; 270*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 271*4882a593Smuzhiyun regulator-max-microvolt = <800000>; 272*4882a593Smuzhiyun regulator-name = "vcc0v8_pmu"; 273*4882a593Smuzhiyun regulator-state-mem { 274*4882a593Smuzhiyun regulator-on-in-suspend; 275*4882a593Smuzhiyun regulator-suspend-microvolt = <800000>; 276*4882a593Smuzhiyun }; 277*4882a593Smuzhiyun }; 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun vcc_1v8: LDO_REG4 { 280*4882a593Smuzhiyun regulator-always-on; 281*4882a593Smuzhiyun regulator-boot-on; 282*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 283*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 284*4882a593Smuzhiyun regulator-name = "vcc_1v8"; 285*4882a593Smuzhiyun regulator-state-mem { 286*4882a593Smuzhiyun regulator-on-in-suspend; 287*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 288*4882a593Smuzhiyun }; 289*4882a593Smuzhiyun }; 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun vcc_dovdd: LDO_REG5 { 292*4882a593Smuzhiyun regulator-boot-on; 293*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 294*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 295*4882a593Smuzhiyun regulator-name = "vcc_dovdd"; 296*4882a593Smuzhiyun regulator-state-mem { 297*4882a593Smuzhiyun regulator-off-in-suspend; 298*4882a593Smuzhiyun }; 299*4882a593Smuzhiyun }; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun vcc_dvdd: LDO_REG6 { 302*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 303*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 304*4882a593Smuzhiyun regulator-name = "vcc_dvdd"; 305*4882a593Smuzhiyun regulator-state-mem { 306*4882a593Smuzhiyun regulator-off-in-suspend; 307*4882a593Smuzhiyun }; 308*4882a593Smuzhiyun }; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun vcc_avdd: LDO_REG7 { 311*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 312*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 313*4882a593Smuzhiyun regulator-name = "vcc_avdd"; 314*4882a593Smuzhiyun regulator-state-mem { 315*4882a593Smuzhiyun regulator-off-in-suspend; 316*4882a593Smuzhiyun }; 317*4882a593Smuzhiyun }; 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun vccio_sd: LDO_REG8 { 320*4882a593Smuzhiyun regulator-always-on; 321*4882a593Smuzhiyun regulator-boot-on; 322*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 323*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 324*4882a593Smuzhiyun regulator-name = "vccio_sd"; 325*4882a593Smuzhiyun regulator-state-mem { 326*4882a593Smuzhiyun regulator-off-in-suspend; 327*4882a593Smuzhiyun }; 328*4882a593Smuzhiyun }; 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun vcc_ldo9: LDO_REG9 { 331*4882a593Smuzhiyun regulator-always-off; 332*4882a593Smuzhiyun regulator-boot-off; 333*4882a593Smuzhiyun regulator-name = "vcc_ldo9"; 334*4882a593Smuzhiyun regulator-state-mem { 335*4882a593Smuzhiyun regulator-off-in-suspend; 336*4882a593Smuzhiyun }; 337*4882a593Smuzhiyun }; 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun vcc_sw1: SWITCH_REG1 { 340*4882a593Smuzhiyun regulator-always-off; 341*4882a593Smuzhiyun regulator-boot-off; 342*4882a593Smuzhiyun regulator-name = "vcc_sw1"; 343*4882a593Smuzhiyun }; 344*4882a593Smuzhiyun 345*4882a593Smuzhiyun vcc_3v3: SWITCH_REG2 { 346*4882a593Smuzhiyun regulator-always-on; 347*4882a593Smuzhiyun regulator-boot-on; 348*4882a593Smuzhiyun regulator-name = "vcc_3v3"; 349*4882a593Smuzhiyun }; 350*4882a593Smuzhiyun }; 351*4882a593Smuzhiyun 352*4882a593Smuzhiyun rk809_codec: codec { 353*4882a593Smuzhiyun #sound-dai-cells = <0>; 354*4882a593Smuzhiyun compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; 355*4882a593Smuzhiyun clocks = <&cru MCLK_I2S0_TX_OUT2IO>; 356*4882a593Smuzhiyun clock-names = "mclk"; 357*4882a593Smuzhiyun pinctrl-names = "default"; 358*4882a593Smuzhiyun assigned-clocks = <&cru MCLK_I2S0_TX_OUT2IO>; 359*4882a593Smuzhiyun assigned-clock-parents = <&cru MCLK_I2S0_TX>; 360*4882a593Smuzhiyun pinctrl-0 = <&i2s0m0_mclk>; 361*4882a593Smuzhiyun hp-volume = <20>; 362*4882a593Smuzhiyun spk-volume = <3>; 363*4882a593Smuzhiyun }; 364*4882a593Smuzhiyun }; 365*4882a593Smuzhiyun}; 366*4882a593Smuzhiyun 367*4882a593Smuzhiyun&i2c1 { 368*4882a593Smuzhiyun status = "okay"; 369*4882a593Smuzhiyun clock-frequency = <400000>; 370*4882a593Smuzhiyun i2c-scl-rising-time-ns = <280>; 371*4882a593Smuzhiyun i2c-scl-falling-time-ns = <16>; 372*4882a593Smuzhiyun 373*4882a593Smuzhiyun imx347: imx347@37 { 374*4882a593Smuzhiyun compatible = "sony,imx347"; 375*4882a593Smuzhiyun reg = <0x37>; 376*4882a593Smuzhiyun clocks = <&cru CLK_MIPICSI_OUT>; 377*4882a593Smuzhiyun clock-names = "xvclk"; 378*4882a593Smuzhiyun power-domains = <&power RV1126_PD_VI>; 379*4882a593Smuzhiyun pinctrl-names = "default"; 380*4882a593Smuzhiyun pinctrl-0 = <&mipicsi_clk0>; 381*4882a593Smuzhiyun avdd-supply = <&vcc_avdd>; 382*4882a593Smuzhiyun dovdd-supply = <&vcc_dovdd>; 383*4882a593Smuzhiyun dvdd-supply = <&vcc_dvdd>; 384*4882a593Smuzhiyun pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; 385*4882a593Smuzhiyun rockchip,camera-module-index = <1>; 386*4882a593Smuzhiyun rockchip,camera-module-facing = "front"; 387*4882a593Smuzhiyun rockchip,camera-module-name = "JSD3425-C1"; 388*4882a593Smuzhiyun rockchip,camera-module-lens-name = "40IRC"; 389*4882a593Smuzhiyun port { 390*4882a593Smuzhiyun ucam_out0: endpoint { 391*4882a593Smuzhiyun remote-endpoint = <&mipi_in_ucam0>; 392*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 393*4882a593Smuzhiyun }; 394*4882a593Smuzhiyun }; 395*4882a593Smuzhiyun }; 396*4882a593Smuzhiyun}; 397*4882a593Smuzhiyun 398*4882a593Smuzhiyun&i2s0_8ch { 399*4882a593Smuzhiyun status = "okay"; 400*4882a593Smuzhiyun #sound-dai-cells = <0>; 401*4882a593Smuzhiyun rockchip,clk-trcm = <1>; 402*4882a593Smuzhiyun rockchip,i2s-rx-route = <3 1 2 0>; 403*4882a593Smuzhiyun pinctrl-names = "default"; 404*4882a593Smuzhiyun pinctrl-0 = <&i2s0m0_sclk_tx 405*4882a593Smuzhiyun &i2s0m0_lrck_tx 406*4882a593Smuzhiyun &i2s0m0_sdo0 407*4882a593Smuzhiyun &i2s0m0_sdo1_sdi3>; 408*4882a593Smuzhiyun}; 409*4882a593Smuzhiyun 410*4882a593Smuzhiyun&mdio { 411*4882a593Smuzhiyun phy: phy@0 { 412*4882a593Smuzhiyun compatible = "ethernet-phy-ieee802.3-c22"; 413*4882a593Smuzhiyun reg = <0x0>; 414*4882a593Smuzhiyun }; 415*4882a593Smuzhiyun}; 416*4882a593Smuzhiyun 417*4882a593Smuzhiyun&mipi_dphy { 418*4882a593Smuzhiyun status = "okay"; 419*4882a593Smuzhiyun}; 420*4882a593Smuzhiyun 421*4882a593Smuzhiyun&pmu_io_domains { 422*4882a593Smuzhiyun status = "okay"; 423*4882a593Smuzhiyun 424*4882a593Smuzhiyun pmuio0-supply = <&vcc1v8_pmu>; 425*4882a593Smuzhiyun pmuio1-supply = <&vcc3v3_sys>; 426*4882a593Smuzhiyun vccio2-supply = <&vccio_sd>; 427*4882a593Smuzhiyun vccio4-supply = <&vcc_1v8>; 428*4882a593Smuzhiyun vccio5-supply = <&vcc_3v3>; 429*4882a593Smuzhiyun vccio6-supply = <&vcc_3v3>; 430*4882a593Smuzhiyun vccio7-supply = <&vcc_1v8>; 431*4882a593Smuzhiyun}; 432*4882a593Smuzhiyun 433*4882a593Smuzhiyun&rkisp_vir0 { 434*4882a593Smuzhiyun status = "okay"; 435*4882a593Smuzhiyun 436*4882a593Smuzhiyun ports { 437*4882a593Smuzhiyun port@0 { 438*4882a593Smuzhiyun reg = <0>; 439*4882a593Smuzhiyun #address-cells = <1>; 440*4882a593Smuzhiyun #size-cells = <0>; 441*4882a593Smuzhiyun 442*4882a593Smuzhiyun isp_in: endpoint@0 { 443*4882a593Smuzhiyun reg = <0>; 444*4882a593Smuzhiyun remote-endpoint = <&csidphy0_out>; 445*4882a593Smuzhiyun }; 446*4882a593Smuzhiyun }; 447*4882a593Smuzhiyun }; 448*4882a593Smuzhiyun}; 449*4882a593Smuzhiyun 450*4882a593Smuzhiyun&saradc { 451*4882a593Smuzhiyun status = "okay"; 452*4882a593Smuzhiyun vref-supply = <&vcc_1v8>; 453*4882a593Smuzhiyun}; 454*4882a593Smuzhiyun 455*4882a593Smuzhiyun&sdmmc { 456*4882a593Smuzhiyun bus-width = <4>; 457*4882a593Smuzhiyun cap-mmc-highspeed; 458*4882a593Smuzhiyun cap-sd-highspeed; 459*4882a593Smuzhiyun card-detect-delay = <200>; 460*4882a593Smuzhiyun rockchip,default-sample-phase = <90>; 461*4882a593Smuzhiyun no-sdio; 462*4882a593Smuzhiyun no-mmc; 463*4882a593Smuzhiyun sd-uhs-sdr12; 464*4882a593Smuzhiyun sd-uhs-sdr25; 465*4882a593Smuzhiyun sd-uhs-sdr104; 466*4882a593Smuzhiyun vqmmc-supply = <&vccio_sd>; 467*4882a593Smuzhiyun status = "okay"; 468*4882a593Smuzhiyun}; 469