1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/pinctrl/rockchip.h> 7#include "rockchip-pinconf.dtsi" 8 9/* 10 * This file is auto generated by pin2dts tool, please keep these code 11 * by adding changes at end of this file. 12 */ 13&pinctrl { 14 acodec { 15 /omit-if-no-ref/ 16 acodec_pins: acodec-pins { 17 rockchip,pins = 18 /* acodec_adc_clk */ 19 <3 RK_PD1 3 &pcfg_pull_none>, 20 /* acodec_adc_data */ 21 <3 RK_PD7 3 &pcfg_pull_none>, 22 /* acodec_adc_sync */ 23 <3 RK_PD4 3 &pcfg_pull_none>, 24 /* acodec_dac_clk */ 25 <3 RK_PD0 3 &pcfg_pull_none>, 26 /* acodec_dac_datal */ 27 <3 RK_PD6 3 &pcfg_pull_none>, 28 /* acodec_dac_datar */ 29 <3 RK_PD5 3 &pcfg_pull_none>, 30 /* acodec_dac_sync */ 31 <3 RK_PD3 3 &pcfg_pull_none>; 32 }; 33 }; 34 auddsm { 35 /omit-if-no-ref/ 36 auddsm_pins: auddsm-pins { 37 rockchip,pins = 38 /* auddsm_ln */ 39 <3 RK_PD3 5 &pcfg_pull_none>, 40 /* auddsm_lp */ 41 <3 RK_PD5 5 &pcfg_pull_none>, 42 /* auddsm_rn */ 43 <4 RK_PA0 5 &pcfg_pull_none>, 44 /* auddsm_rp */ 45 <4 RK_PA1 5 &pcfg_pull_none>; 46 }; 47 }; 48 audpwm { 49 /omit-if-no-ref/ 50 audpwmm0_pins: audpwmm0-pins { 51 rockchip,pins = 52 /* audpwm_l_m0 */ 53 <4 RK_PA0 3 &pcfg_pull_none>, 54 /* audpwm_r_m0 */ 55 <4 RK_PA1 3 &pcfg_pull_none>; 56 }; 57 /omit-if-no-ref/ 58 audpwmm1_pins: audpwmm1-pins { 59 rockchip,pins = 60 /* audpwm_l_m1 */ 61 <3 RK_PD3 4 &pcfg_pull_none>, 62 /* audpwm_r_m1 */ 63 <3 RK_PD5 4 &pcfg_pull_none>; 64 }; 65 }; 66 can { 67 /omit-if-no-ref/ 68 canm0_pins: canm0-pins { 69 rockchip,pins = 70 /* can_rxd_m0 */ 71 <3 RK_PA0 3 &pcfg_pull_none>, 72 /* can_txd_m0 */ 73 <3 RK_PA1 3 &pcfg_pull_none>; 74 }; 75 /omit-if-no-ref/ 76 canm1_pins: canm1-pins { 77 rockchip,pins = 78 /* can_rxd_m1 */ 79 <3 RK_PA6 5 &pcfg_pull_none>, 80 /* can_txd_m1 */ 81 <3 RK_PA7 5 &pcfg_pull_none>; 82 }; 83 }; 84 cif { 85 /omit-if-no-ref/ 86 cifm0_dvp_ctl: cifm0-dvp-ctl { 87 rockchip,pins = 88 /* cif_clkin_m0 */ 89 <3 RK_PC5 1 &pcfg_pull_none>, 90 /* cif_clkout_m0 */ 91 <3 RK_PC6 1 &pcfg_pull_none>, 92 /* cif_d0_m0 */ 93 <3 RK_PA4 1 &pcfg_pull_none>, 94 /* cif_d10_m0 */ 95 <3 RK_PB6 1 &pcfg_pull_none>, 96 /* cif_d11_m0 */ 97 <3 RK_PB7 1 &pcfg_pull_none>, 98 /* cif_d12_m0 */ 99 <3 RK_PC0 1 &pcfg_pull_none>, 100 /* cif_d13_m0 */ 101 <3 RK_PC1 1 &pcfg_pull_none>, 102 /* cif_d14_m0 */ 103 <3 RK_PC2 1 &pcfg_pull_none>, 104 /* cif_d15_m0 */ 105 <3 RK_PC3 1 &pcfg_pull_none>, 106 /* cif_d1_m0 */ 107 <3 RK_PA5 1 &pcfg_pull_none>, 108 /* cif_d2_m0 */ 109 <3 RK_PA6 1 &pcfg_pull_none>, 110 /* cif_d3_m0 */ 111 <3 RK_PA7 1 &pcfg_pull_none>, 112 /* cif_d4_m0 */ 113 <3 RK_PB0 1 &pcfg_pull_none>, 114 /* cif_d5_m0 */ 115 <3 RK_PB1 1 &pcfg_pull_none>, 116 /* cif_d6_m0 */ 117 <3 RK_PB2 1 &pcfg_pull_none>, 118 /* cif_d7_m0 */ 119 <3 RK_PB3 1 &pcfg_pull_none>, 120 /* cif_d8_m0 */ 121 <3 RK_PB4 1 &pcfg_pull_none>, 122 /* cif_d9_m0 */ 123 <3 RK_PB5 1 &pcfg_pull_none>, 124 /* cif_hsync_m0 */ 125 <3 RK_PC7 1 &pcfg_pull_none>, 126 /* cif_vsync_m0 */ 127 <3 RK_PC4 1 &pcfg_pull_none>; 128 }; 129 /omit-if-no-ref/ 130 cifm1_dvp_ctl: cifm1-dvp-ctl { 131 rockchip,pins = 132 /* cif_clkin_m1 */ 133 <2 RK_PD2 3 &pcfg_pull_none>, 134 /* cif_clkout_m1 */ 135 <2 RK_PD1 3 &pcfg_pull_none>, 136 /* cif_d0_m1 */ 137 <2 RK_PA4 3 &pcfg_pull_none>, 138 /* cif_d10_m1 */ 139 <2 RK_PC2 3 &pcfg_pull_none>, 140 /* cif_d11_m1 */ 141 <2 RK_PC3 3 &pcfg_pull_none>, 142 /* cif_d12_m1 */ 143 <2 RK_PC4 3 &pcfg_pull_none>, 144 /* cif_d13_m1 */ 145 <2 RK_PC5 3 &pcfg_pull_none>, 146 /* cif_d14_m1 */ 147 <2 RK_PC6 3 &pcfg_pull_none>, 148 /* cif_d15_m1 */ 149 <2 RK_PC7 3 &pcfg_pull_none>, 150 /* cif_d1_m1 */ 151 <2 RK_PA5 3 &pcfg_pull_none>, 152 /* cif_d2_m1 */ 153 <2 RK_PA6 3 &pcfg_pull_none>, 154 /* cif_d3_m1 */ 155 <2 RK_PB3 3 &pcfg_pull_none>, 156 /* cif_d4_m1 */ 157 <2 RK_PB4 3 &pcfg_pull_none>, 158 /* cif_d5_m1 */ 159 <2 RK_PB5 3 &pcfg_pull_none>, 160 /* cif_d6_m1 */ 161 <2 RK_PB6 3 &pcfg_pull_none>, 162 /* cif_d7_m1 */ 163 <2 RK_PB7 3 &pcfg_pull_none>, 164 /* cif_d8_m1 */ 165 <2 RK_PC0 3 &pcfg_pull_none>, 166 /* cif_d9_m1 */ 167 <2 RK_PC1 3 &pcfg_pull_none>, 168 /* cif_hsync_m1 */ 169 <2 RK_PD3 3 &pcfg_pull_none>, 170 /* cif_vsync_m1 */ 171 <2 RK_PD0 3 &pcfg_pull_none>; 172 }; 173 }; 174 clk { 175 /omit-if-no-ref/ 176 clkm0_out_ethernet: clkm0-out-ethernet { 177 rockchip,pins = 178 /* clkm0_out_ethernet */ 179 <3 RK_PC5 2 &pcfg_pull_none>; 180 }; 181 /omit-if-no-ref/ 182 clkm1_out_ethernet: clkm1-out-ethernet { 183 rockchip,pins = 184 /* clkm1_out_ethernet */ 185 <2 RK_PC5 2 &pcfg_pull_none>; 186 }; 187 /omit-if-no-ref/ 188 clk_32k: clk-32k { 189 rockchip,pins = 190 /* clk_32k */ 191 <0 RK_PA2 1 &pcfg_pull_none>; 192 }; 193 /omit-if-no-ref/ 194 clk_ref: clk-ref { 195 rockchip,pins = 196 /* clk_ref */ 197 <0 RK_PA0 1 &pcfg_pull_none>; 198 }; 199 }; 200 emmc { 201 /omit-if-no-ref/ 202 emmc_rstnout: emmc-rstnout { 203 rockchip,pins = 204 /* emmc_rstn */ 205 <1 RK_PA3 2 &pcfg_pull_none>; 206 }; 207 /omit-if-no-ref/ 208 emmc_bus8: emmc-bus8 { 209 rockchip,pins = 210 /* emmc_d0 */ 211 <0 RK_PC4 2 &pcfg_pull_up_drv_level_2>, 212 /* emmc_d1 */ 213 <0 RK_PC5 2 &pcfg_pull_up_drv_level_2>, 214 /* emmc_d2 */ 215 <0 RK_PC6 2 &pcfg_pull_up_drv_level_2>, 216 /* emmc_d3 */ 217 <0 RK_PC7 2 &pcfg_pull_up_drv_level_2>, 218 /* emmc_d4 */ 219 <0 RK_PD0 2 &pcfg_pull_up_drv_level_2>, 220 /* emmc_d5 */ 221 <0 RK_PD1 2 &pcfg_pull_up_drv_level_2>, 222 /* emmc_d6 */ 223 <0 RK_PD2 2 &pcfg_pull_up_drv_level_2>, 224 /* emmc_d7 */ 225 <0 RK_PD3 2 &pcfg_pull_up_drv_level_2>; 226 }; 227 /omit-if-no-ref/ 228 emmc_clk: emmc-clk { 229 rockchip,pins = 230 /* emmc_clko */ 231 <0 RK_PD7 2 &pcfg_pull_up_drv_level_2>; 232 }; 233 /omit-if-no-ref/ 234 emmc_cmd: emmc-cmd { 235 rockchip,pins = 236 /* emmc_cmd */ 237 <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>; 238 }; 239 }; 240 flash { 241 /omit-if-no-ref/ 242 flash_pins: flash-pins { 243 rockchip,pins = 244 /* flash_ale */ 245 <1 RK_PA0 1 &pcfg_pull_none>, 246 /* flash_cle */ 247 <0 RK_PD7 1 &pcfg_pull_none>, 248 /* flash_cs0n */ 249 <0 RK_PD4 1 &pcfg_pull_none>, 250 /* flash_d0 */ 251 <0 RK_PC4 1 &pcfg_pull_none>, 252 /* flash_d1 */ 253 <0 RK_PC5 1 &pcfg_pull_none>, 254 /* flash_d2 */ 255 <0 RK_PC6 1 &pcfg_pull_none>, 256 /* flash_d3 */ 257 <0 RK_PC7 1 &pcfg_pull_none>, 258 /* flash_d4 */ 259 <0 RK_PD0 1 &pcfg_pull_none>, 260 /* flash_d5 */ 261 <0 RK_PD1 1 &pcfg_pull_none>, 262 /* flash_d6 */ 263 <0 RK_PD2 1 &pcfg_pull_none>, 264 /* flash_d7 */ 265 <0 RK_PD3 1 &pcfg_pull_none>, 266 /* flash_rdn */ 267 <1 RK_PA2 1 &pcfg_pull_none>, 268 /* flash_rdyn */ 269 <1 RK_PA1 1 &pcfg_pull_none>, 270 /* flash_trig_in */ 271 <1 RK_PC5 4 &pcfg_pull_none>, 272 /* flash_trig_out */ 273 <1 RK_PC4 4 &pcfg_pull_none>, 274 /* flash_vol_sel */ 275 <0 RK_PB3 1 &pcfg_pull_none>, 276 /* flash_wpn */ 277 <1 RK_PA3 1 &pcfg_pull_none>, 278 /* flash_wrn */ 279 <0 RK_PD5 1 &pcfg_pull_none>; 280 }; 281 }; 282 fspi { 283 /omit-if-no-ref/ 284 fspi_cs1: fspi-cs1 { 285 rockchip,pins = 286 /* fspi_cs1n */ 287 <0 RK_PD1 3 &pcfg_pull_up>; 288 }; 289 /omit-if-no-ref/ 290 fspi_pins: fspi-pins { 291 rockchip,pins = 292 /* fspi_clk */ 293 <1 RK_PA3 3 &pcfg_pull_down>, 294 /* fspi_cs0n */ 295 <0 RK_PD4 3 &pcfg_pull_up>, 296 /* fspi_d0 */ 297 <1 RK_PA0 3 &pcfg_pull_up>, 298 /* fspi_d1 */ 299 <1 RK_PA1 3 &pcfg_pull_up>, 300 /* fspi_d2 */ 301 <0 RK_PD6 3 &pcfg_pull_up>, 302 /* fspi_d3 */ 303 <1 RK_PA2 3 &pcfg_pull_up>; 304 }; 305 }; 306 i2c0 { 307 /omit-if-no-ref/ 308 i2c0_xfer: i2c0-xfer { 309 rockchip,pins = 310 /* i2c0_scl */ 311 <0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>, 312 /* i2c0_sda */ 313 <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>; 314 }; 315 }; 316 i2c1 { 317 /omit-if-no-ref/ 318 i2c1_xfer: i2c1-xfer { 319 rockchip,pins = 320 /* i2c1_scl */ 321 <1 RK_PD3 1 &pcfg_pull_none_drv_level_0_smt>, 322 /* i2c1_sda */ 323 <1 RK_PD2 1 &pcfg_pull_none_drv_level_0_smt>; 324 }; 325 }; 326 i2c2 { 327 /omit-if-no-ref/ 328 i2c2_xfer: i2c2-xfer { 329 rockchip,pins = 330 /* i2c2_scl */ 331 <0 RK_PC2 1 &pcfg_pull_none_drv_level_0_smt>, 332 /* i2c2_sda */ 333 <0 RK_PC3 1 &pcfg_pull_none_drv_level_0_smt>; 334 }; 335 }; 336 i2c3 { 337 /omit-if-no-ref/ 338 i2c3m0_xfer: i2c3m0-xfer { 339 rockchip,pins = 340 /* i2c3_scl_m0 */ 341 <3 RK_PA4 5 &pcfg_pull_none_drv_level_0_smt>, 342 /* i2c3_sda_m0 */ 343 <3 RK_PA5 5 &pcfg_pull_none_drv_level_0_smt>; 344 }; 345 /omit-if-no-ref/ 346 i2c3m1_xfer: i2c3m1-xfer { 347 rockchip,pins = 348 /* i2c3_scl_m1 */ 349 <2 RK_PD4 7 &pcfg_pull_none_drv_level_0_smt>, 350 /* i2c3_sda_m1 */ 351 <2 RK_PD5 7 &pcfg_pull_none_drv_level_0_smt>; 352 }; 353 /omit-if-no-ref/ 354 i2c3m2_xfer: i2c3m2-xfer { 355 rockchip,pins = 356 /* i2c3_scl_m2 */ 357 <1 RK_PD6 3 &pcfg_pull_none_drv_level_0_smt>, 358 /* i2c3_sda_m2 */ 359 <1 RK_PD7 3 &pcfg_pull_none_drv_level_0_smt>; 360 }; 361 }; 362 i2c4 { 363 /omit-if-no-ref/ 364 i2c4m0_xfer: i2c4m0-xfer { 365 rockchip,pins = 366 /* i2c4_scl_m0 */ 367 <3 RK_PA0 7 &pcfg_pull_none_drv_level_0_smt>, 368 /* i2c4_sda_m0 */ 369 <3 RK_PA1 7 &pcfg_pull_none_drv_level_0_smt>; 370 }; 371 /omit-if-no-ref/ 372 i2c4m1_xfer: i2c4m1-xfer { 373 rockchip,pins = 374 /* i2c4_scl_m1 */ 375 <4 RK_PA0 4 &pcfg_pull_none_drv_level_0_smt>, 376 /* i2c4_sda_m1 */ 377 <4 RK_PA1 4 &pcfg_pull_none_drv_level_0_smt>; 378 }; 379 }; 380 i2c5 { 381 /omit-if-no-ref/ 382 i2c5m0_xfer: i2c5m0-xfer { 383 rockchip,pins = 384 /* i2c5_scl_m0 */ 385 <2 RK_PA5 7 &pcfg_pull_none_drv_level_0_smt>, 386 /* i2c5_sda_m0 */ 387 <2 RK_PB3 7 &pcfg_pull_none_drv_level_0_smt>; 388 }; 389 /omit-if-no-ref/ 390 i2c5m1_xfer: i2c5m1-xfer { 391 rockchip,pins = 392 /* i2c5_scl_m1 */ 393 <3 RK_PB0 5 &pcfg_pull_none_drv_level_0_smt>, 394 /* i2c5_sda_m1 */ 395 <3 RK_PB1 5 &pcfg_pull_none_drv_level_0_smt>; 396 }; 397 /omit-if-no-ref/ 398 i2c5m2_xfer: i2c5m2-xfer { 399 rockchip,pins = 400 /* i2c5_scl_m2 */ 401 <1 RK_PD0 4 &pcfg_pull_none_drv_level_0_smt>, 402 /* i2c5_sda_m2 */ 403 <1 RK_PD1 4 &pcfg_pull_none_drv_level_0_smt>; 404 }; 405 }; 406 i2s0 { 407 /omit-if-no-ref/ 408 i2s0m0_lrck_rx: i2s0m0-lrck-rx { 409 rockchip,pins = 410 /* i2s0m0_lrck_rx */ 411 <3 RK_PD4 1 &pcfg_pull_none>; 412 }; 413 /omit-if-no-ref/ 414 i2s0m0_lrck_tx: i2s0m0-lrck-tx { 415 rockchip,pins = 416 /* i2s0m0_lrck_tx */ 417 <3 RK_PD3 1 &pcfg_pull_none>; 418 }; 419 /omit-if-no-ref/ 420 i2s0m0_mclk: i2s0m0-mclk { 421 rockchip,pins = 422 /* i2s0m0_mclk */ 423 <3 RK_PD2 1 &pcfg_pull_none>; 424 }; 425 /omit-if-no-ref/ 426 i2s0m0_sclk_rx: i2s0m0-sclk-rx { 427 rockchip,pins = 428 /* i2s0m0_sclk_rx */ 429 <3 RK_PD1 1 &pcfg_pull_none>; 430 }; 431 /omit-if-no-ref/ 432 i2s0m0_sclk_tx: i2s0m0-sclk-tx { 433 rockchip,pins = 434 /* i2s0m0_sclk_tx */ 435 <3 RK_PD0 1 &pcfg_pull_none>; 436 }; 437 /omit-if-no-ref/ 438 i2s0m0_sdi0: i2s0m0-sdi0 { 439 rockchip,pins = 440 /* i2s0m0_sdi0 */ 441 <3 RK_PD6 1 &pcfg_pull_none>; 442 }; 443 /omit-if-no-ref/ 444 i2s0m0_sdo0: i2s0m0-sdo0 { 445 rockchip,pins = 446 /* i2s0m0_sdo0 */ 447 <3 RK_PD5 1 &pcfg_pull_none>; 448 }; 449 /omit-if-no-ref/ 450 i2s0m0_sdo1_sdi3: i2s0m0-sdo1-sdi3 { 451 rockchip,pins = 452 /* i2s0m0_sdo1_sdi3 */ 453 <3 RK_PD7 1 &pcfg_pull_none>; 454 }; 455 /omit-if-no-ref/ 456 i2s0m0_sdo2_sdi2: i2s0m0-sdo2-sdi2 { 457 rockchip,pins = 458 /* i2s0m0_sdo2_sdi2 */ 459 <4 RK_PA0 1 &pcfg_pull_none>; 460 }; 461 /omit-if-no-ref/ 462 i2s0m0_sdo3_sdi1: i2s0m0-sdo3-sdi1 { 463 rockchip,pins = 464 /* i2s0m0_sdo3_sdi1 */ 465 <4 RK_PA1 1 &pcfg_pull_none>; 466 }; 467 /omit-if-no-ref/ 468 i2s0m1_lrck_rx: i2s0m1-lrck-rx { 469 rockchip,pins = 470 /* i2s0m1_lrck_rx */ 471 <3 RK_PB2 3 &pcfg_pull_none>; 472 }; 473 /omit-if-no-ref/ 474 i2s0m1_lrck_tx: i2s0m1-lrck-tx { 475 rockchip,pins = 476 /* i2s0m1_lrck_tx */ 477 <3 RK_PA5 3 &pcfg_pull_none>; 478 }; 479 /omit-if-no-ref/ 480 i2s0m1_mclk: i2s0m1-mclk { 481 rockchip,pins = 482 /* i2s0m1_mclk */ 483 <3 RK_PB0 3 &pcfg_pull_none>; 484 }; 485 /omit-if-no-ref/ 486 i2s0m1_sclk_rx: i2s0m1-sclk-rx { 487 rockchip,pins = 488 /* i2s0m1_sclk_rx */ 489 <3 RK_PB1 3 &pcfg_pull_none>; 490 }; 491 /omit-if-no-ref/ 492 i2s0m1_sclk_tx: i2s0m1-sclk-tx { 493 rockchip,pins = 494 /* i2s0m1_sclk_tx */ 495 <3 RK_PA4 3 &pcfg_pull_none>; 496 }; 497 /omit-if-no-ref/ 498 i2s0m1_sdi0: i2s0m1-sdi0 { 499 rockchip,pins = 500 /* i2s0m1_sdi0 */ 501 <3 RK_PA7 3 &pcfg_pull_none>; 502 }; 503 /omit-if-no-ref/ 504 i2s0m1_sdo0: i2s0m1-sdo0 { 505 rockchip,pins = 506 /* i2s0m1_sdo0 */ 507 <3 RK_PA6 3 &pcfg_pull_none>; 508 }; 509 /omit-if-no-ref/ 510 i2s0m1_sdo1_sdi3: i2s0m1-sdo1-sdi3 { 511 rockchip,pins = 512 /* i2s0m1_sdo1_sdi3 */ 513 <3 RK_PB3 3 &pcfg_pull_none>; 514 }; 515 /omit-if-no-ref/ 516 i2s0m1_sdo2_sdi2: i2s0m1-sdo2-sdi2 { 517 rockchip,pins = 518 /* i2s0m1_sdo2_sdi2 */ 519 <3 RK_PB4 3 &pcfg_pull_none>; 520 }; 521 /omit-if-no-ref/ 522 i2s0m1_sdo3_sdi1: i2s0m1-sdo3-sdi1 { 523 rockchip,pins = 524 /* i2s0m1_sdo3_sdi1 */ 525 <3 RK_PB5 3 &pcfg_pull_none>; 526 }; 527 }; 528 i2s1 { 529 /omit-if-no-ref/ 530 i2s1m0_lrck: i2s1m0-lrck { 531 rockchip,pins = 532 /* i2s1m0_lrck */ 533 <1 RK_PA0 4 &pcfg_pull_none>; 534 }; 535 /omit-if-no-ref/ 536 i2s1m0_mclk: i2s1m0-mclk { 537 rockchip,pins = 538 /* i2s1m0_mclk */ 539 <0 RK_PD4 4 &pcfg_pull_none>; 540 }; 541 /omit-if-no-ref/ 542 i2s1m0_sclk: i2s1m0-sclk { 543 rockchip,pins = 544 /* i2s1m0_sclk */ 545 <1 RK_PA1 4 &pcfg_pull_none>; 546 }; 547 /omit-if-no-ref/ 548 i2s1m0_sdi: i2s1m0-sdi { 549 rockchip,pins = 550 /* i2s1m0_sdi */ 551 <1 RK_PA2 4 &pcfg_pull_none>; 552 }; 553 /omit-if-no-ref/ 554 i2s1m0_sdo: i2s1m0-sdo { 555 rockchip,pins = 556 /* i2s1m0_sdo */ 557 <0 RK_PD6 4 &pcfg_pull_none>; 558 }; 559 /omit-if-no-ref/ 560 i2s1m1_lrck: i2s1m1-lrck { 561 rockchip,pins = 562 /* i2s1m1_lrck */ 563 <1 RK_PD7 2 &pcfg_pull_none>; 564 }; 565 /omit-if-no-ref/ 566 i2s1m1_mclk: i2s1m1-mclk { 567 rockchip,pins = 568 /* i2s1m1_mclk */ 569 <1 RK_PD5 2 &pcfg_pull_none>; 570 }; 571 /omit-if-no-ref/ 572 i2s1m1_sclk: i2s1m1-sclk { 573 rockchip,pins = 574 /* i2s1m1_sclk */ 575 <1 RK_PD6 2 &pcfg_pull_none>; 576 }; 577 /omit-if-no-ref/ 578 i2s1m1_sdi: i2s1m1-sdi { 579 rockchip,pins = 580 /* i2s1m1_sdi */ 581 <2 RK_PA0 2 &pcfg_pull_none>; 582 }; 583 /omit-if-no-ref/ 584 i2s1m1_sdo: i2s1m1-sdo { 585 rockchip,pins = 586 /* i2s1m1_sdo */ 587 <2 RK_PA1 2 &pcfg_pull_none>; 588 }; 589 /omit-if-no-ref/ 590 i2s1m2_lrck: i2s1m2-lrck { 591 rockchip,pins = 592 /* i2s1m2_lrck */ 593 <2 RK_PD2 6 &pcfg_pull_none>; 594 }; 595 /omit-if-no-ref/ 596 i2s1m2_mclk: i2s1m2-mclk { 597 rockchip,pins = 598 /* i2s1m2_mclk */ 599 <2 RK_PC7 6 &pcfg_pull_none>; 600 }; 601 /omit-if-no-ref/ 602 i2s1m2_sclk: i2s1m2-sclk { 603 rockchip,pins = 604 /* i2s1m2_sclk */ 605 <2 RK_PD1 6 &pcfg_pull_none>; 606 }; 607 /omit-if-no-ref/ 608 i2s1m2_sdi: i2s1m2-sdi { 609 rockchip,pins = 610 /* i2s1m2_sdi */ 611 <2 RK_PD3 6 &pcfg_pull_none>; 612 }; 613 /omit-if-no-ref/ 614 i2s1m2_sdo: i2s1m2-sdo { 615 rockchip,pins = 616 /* i2s1m2_sdo */ 617 <2 RK_PD0 6 &pcfg_pull_none>; 618 }; 619 }; 620 i2s2 { 621 /omit-if-no-ref/ 622 i2s2m0_lrck: i2s2m0-lrck { 623 rockchip,pins = 624 /* i2s2m0_lrck */ 625 <1 RK_PC7 1 &pcfg_pull_none>; 626 }; 627 /omit-if-no-ref/ 628 i2s2m0_mclk: i2s2m0-mclk { 629 rockchip,pins = 630 /* i2s2m0_mclk */ 631 <1 RK_PD0 1 &pcfg_pull_none>; 632 }; 633 /omit-if-no-ref/ 634 i2s2m0_sclk: i2s2m0-sclk { 635 rockchip,pins = 636 /* i2s2m0_sclk */ 637 <1 RK_PC6 1 &pcfg_pull_none>; 638 }; 639 /omit-if-no-ref/ 640 i2s2m0_sdi: i2s2m0-sdi { 641 rockchip,pins = 642 /* i2s2m0_sdi */ 643 <1 RK_PC5 1 &pcfg_pull_none>; 644 }; 645 /omit-if-no-ref/ 646 i2s2m0_sdo: i2s2m0-sdo { 647 rockchip,pins = 648 /* i2s2m0_sdo */ 649 <1 RK_PC4 1 &pcfg_pull_none>; 650 }; 651 /omit-if-no-ref/ 652 i2s2m1_lrck: i2s2m1-lrck { 653 rockchip,pins = 654 /* i2s2m1_lrck */ 655 <2 RK_PB2 2 &pcfg_pull_none>; 656 }; 657 /omit-if-no-ref/ 658 i2s2m1_mclk: i2s2m1-mclk { 659 rockchip,pins = 660 /* i2s2m1_mclk */ 661 <2 RK_PB3 2 &pcfg_pull_none>; 662 }; 663 /omit-if-no-ref/ 664 i2s2m1_sclk: i2s2m1-sclk { 665 rockchip,pins = 666 /* i2s2m1_sclk */ 667 <2 RK_PB1 2 &pcfg_pull_none>; 668 }; 669 /omit-if-no-ref/ 670 i2s2m1_sdi: i2s2m1-sdi { 671 rockchip,pins = 672 /* i2s2m1_sdi */ 673 <2 RK_PB0 2 &pcfg_pull_none>; 674 }; 675 /omit-if-no-ref/ 676 i2s2m1_sdo: i2s2m1-sdo { 677 rockchip,pins = 678 /* i2s2m1_sdo */ 679 <2 RK_PA7 2 &pcfg_pull_none>; 680 }; 681 }; 682 lcdc { 683 /omit-if-no-ref/ 684 lcdc_ctl: lcdc-ctl { 685 rockchip,pins = 686 /* lcdc_clk */ 687 <2 RK_PD7 1 &pcfg_pull_none_drv_level_8>, 688 /* lcdc_d0 */ 689 <2 RK_PA4 1 &pcfg_pull_none_drv_level_2>, 690 /* lcdc_d1 */ 691 <2 RK_PA5 1 &pcfg_pull_none_drv_level_2>, 692 /* lcdc_d2 */ 693 <2 RK_PA6 1 &pcfg_pull_none_drv_level_2>, 694 /* lcdc_d3 */ 695 <2 RK_PA7 1 &pcfg_pull_none_drv_level_2>, 696 /* lcdc_d4 */ 697 <2 RK_PB0 1 &pcfg_pull_none_drv_level_2>, 698 /* lcdc_d5 */ 699 <2 RK_PB1 1 &pcfg_pull_none_drv_level_2>, 700 /* lcdc_d6 */ 701 <2 RK_PB2 1 &pcfg_pull_none_drv_level_2>, 702 /* lcdc_d7 */ 703 <2 RK_PB3 1 &pcfg_pull_none_drv_level_2>, 704 /* lcdc_d8 */ 705 <2 RK_PB4 1 &pcfg_pull_none_drv_level_2>, 706 /* lcdc_d9 */ 707 <2 RK_PB5 1 &pcfg_pull_none_drv_level_2>, 708 /* lcdc_d10 */ 709 <2 RK_PB6 1 &pcfg_pull_none_drv_level_2>, 710 /* lcdc_d11 */ 711 <2 RK_PB7 1 &pcfg_pull_none_drv_level_2>, 712 /* lcdc_d12 */ 713 <2 RK_PC0 1 &pcfg_pull_none_drv_level_2>, 714 /* lcdc_d13 */ 715 <2 RK_PC1 1 &pcfg_pull_none_drv_level_2>, 716 /* lcdc_d14 */ 717 <2 RK_PC2 1 &pcfg_pull_none_drv_level_2>, 718 /* lcdc_d15 */ 719 <2 RK_PC3 1 &pcfg_pull_none_drv_level_2>, 720 /* lcdc_d16 */ 721 <2 RK_PC4 1 &pcfg_pull_none_drv_level_2>, 722 /* lcdc_d17 */ 723 <2 RK_PC5 1 &pcfg_pull_none_drv_level_2>, 724 /* lcdc_d18 */ 725 <2 RK_PC6 1 &pcfg_pull_none_drv_level_2>, 726 /* lcdc_d19 */ 727 <2 RK_PC7 1 &pcfg_pull_none_drv_level_2>, 728 /* lcdc_d20 */ 729 <2 RK_PD0 1 &pcfg_pull_none_drv_level_2>, 730 /* lcdc_d21 */ 731 <2 RK_PD1 1 &pcfg_pull_none_drv_level_2>, 732 /* lcdc_d22 */ 733 <2 RK_PD2 1 &pcfg_pull_none_drv_level_2>, 734 /* lcdc_d23 */ 735 <2 RK_PD3 1 &pcfg_pull_none_drv_level_2>, 736 /* lcdc_den */ 737 <2 RK_PD4 1 &pcfg_pull_none_drv_level_2>, 738 /* lcdc_hsync */ 739 <2 RK_PD5 1 &pcfg_pull_none_drv_level_2>, 740 /* lcdc_vsync */ 741 <2 RK_PD6 1 &pcfg_pull_none_drv_level_2>; 742 }; 743 }; 744 mcu { 745 /omit-if-no-ref/ 746 mcu_pins: mcu-pins { 747 rockchip,pins = 748 /* mcu_jtag_tck */ 749 <1 RK_PA6 4 &pcfg_pull_none>, 750 /* mcu_jtag_tdi */ 751 <1 RK_PB1 4 &pcfg_pull_none>, 752 /* mcu_jtag_tdo */ 753 <1 RK_PB0 4 &pcfg_pull_none>, 754 /* mcu_jtag_tms */ 755 <1 RK_PA7 4 &pcfg_pull_none>, 756 /* mcu_jtag_trstn */ 757 <1 RK_PA5 4 &pcfg_pull_none>; 758 }; 759 }; 760 mipicsi { 761 /omit-if-no-ref/ 762 mipicsi_clk0: mipicsi-clk0 { 763 rockchip,pins = 764 /* mipicsi_clk0 */ 765 <2 RK_PA3 1 &pcfg_pull_none>; 766 }; 767 /omit-if-no-ref/ 768 mipicsi_clk1: mipicsi-clk1 { 769 rockchip,pins = 770 /* mipicsi_clk1 */ 771 <2 RK_PA2 1 &pcfg_pull_none>; 772 }; 773 }; 774 pdm { 775 /omit-if-no-ref/ 776 pdmm0_clk: pdmm0-clk { 777 rockchip,pins = 778 /* pdm_clk0_m0 */ 779 <3 RK_PD4 2 &pcfg_pull_none>; 780 }; 781 /omit-if-no-ref/ 782 pdmm0_clk1: pdmm0-clk1 { 783 rockchip,pins = 784 /* pdmm0_clk1 */ 785 <3 RK_PD1 2 &pcfg_pull_none>; 786 }; 787 /omit-if-no-ref/ 788 pdmm0_sdi0: pdmm0-sdi0 { 789 rockchip,pins = 790 /* pdmm0_sdi0 */ 791 <3 RK_PD6 2 &pcfg_pull_none>; 792 }; 793 /omit-if-no-ref/ 794 pdmm0_sdi1: pdmm0-sdi1 { 795 rockchip,pins = 796 /* pdmm0_sdi1 */ 797 <4 RK_PA1 2 &pcfg_pull_none>; 798 }; 799 /omit-if-no-ref/ 800 pdmm0_sdi2: pdmm0-sdi2 { 801 rockchip,pins = 802 /* pdmm0_sdi2 */ 803 <4 RK_PA0 2 &pcfg_pull_none>; 804 }; 805 /omit-if-no-ref/ 806 pdmm0_sdi3: pdmm0-sdi3 { 807 rockchip,pins = 808 /* pdmm0_sdi3 */ 809 <3 RK_PD7 2 &pcfg_pull_none>; 810 }; 811 /omit-if-no-ref/ 812 pdmm1_clk: pdmm1-clk { 813 rockchip,pins = 814 /* pdm_clk0_m1 */ 815 <3 RK_PC0 3 &pcfg_pull_none>; 816 }; 817 /omit-if-no-ref/ 818 pdmm1_clk1: pdmm1-clk1 { 819 rockchip,pins = 820 /* pdmm1_clk1 */ 821 <3 RK_PC3 3 &pcfg_pull_none>; 822 }; 823 /omit-if-no-ref/ 824 pdmm1_sdi0: pdmm1-sdi0 { 825 rockchip,pins = 826 /* pdmm1_sdi0 */ 827 <3 RK_PC1 3 &pcfg_pull_none>; 828 }; 829 /omit-if-no-ref/ 830 pdmm1_sdi1: pdmm1-sdi1 { 831 rockchip,pins = 832 /* pdmm1_sdi1 */ 833 <3 RK_PC2 3 &pcfg_pull_none>; 834 }; 835 /omit-if-no-ref/ 836 pdmm1_sdi2: pdmm1-sdi2 { 837 rockchip,pins = 838 /* pdmm1_sdi2 */ 839 <3 RK_PB6 3 &pcfg_pull_none>; 840 }; 841 /omit-if-no-ref/ 842 pdmm1_sdi3: pdmm1-sdi3 { 843 rockchip,pins = 844 /* pdmm1_sdi3 */ 845 <3 RK_PB7 3 &pcfg_pull_none>; 846 }; 847 }; 848 pmic { 849 /omit-if-no-ref/ 850 pmic_pins: pmic-pins { 851 rockchip,pins = 852 /* pmic_int */ 853 <0 RK_PB1 1 &pcfg_pull_none>, 854 /* pmic_sleep */ 855 <0 RK_PB2 1 &pcfg_pull_none>; 856 }; 857 }; 858 pmu { 859 /omit-if-no-ref/ 860 pmu_pins: pmu-pins { 861 rockchip,pins = 862 /* pmu_debug */ 863 <0 RK_PC1 1 &pcfg_pull_none>; 864 }; 865 }; 866 prelight { 867 /omit-if-no-ref/ 868 prelight_pins: prelight-pins { 869 rockchip,pins = 870 /* prelight_trig_out */ 871 <1 RK_PC6 4 &pcfg_pull_none>; 872 }; 873 }; 874 pwm0 { 875 /omit-if-no-ref/ 876 pwm0m0_pins: pwm0m0-pins { 877 rockchip,pins = 878 /* pwm0_pin_m0 */ 879 <0 RK_PB6 3 &pcfg_pull_none>; 880 }; 881 /omit-if-no-ref/ 882 pwm0m1_pins: pwm0m1-pins { 883 rockchip,pins = 884 /* pwm0_pin_m1 */ 885 <2 RK_PB3 5 &pcfg_pull_none>; 886 }; 887 }; 888 pwm1 { 889 /omit-if-no-ref/ 890 pwm1m0_pins: pwm1m0-pins { 891 rockchip,pins = 892 /* pwm1_pin_m0 */ 893 <0 RK_PB7 3 &pcfg_pull_none>; 894 }; 895 /omit-if-no-ref/ 896 pwm1m1_pins: pwm1m1-pins { 897 rockchip,pins = 898 /* pwm1_pin_m1 */ 899 <2 RK_PB2 5 &pcfg_pull_none>; 900 }; 901 }; 902 pwm2 { 903 /omit-if-no-ref/ 904 pwm2m0_pins: pwm2m0-pins { 905 rockchip,pins = 906 /* pwm2_pin_m0 */ 907 <0 RK_PC0 3 &pcfg_pull_none>; 908 }; 909 /omit-if-no-ref/ 910 pwm2m1_pins: pwm2m1-pins { 911 rockchip,pins = 912 /* pwm2_pin_m1 */ 913 <2 RK_PB1 5 &pcfg_pull_none>; 914 }; 915 }; 916 pwm3 { 917 /omit-if-no-ref/ 918 pwm3m0_pins: pwm3m0-pins { 919 rockchip,pins = 920 /* pwm3_pin_m0 */ 921 <0 RK_PC1 3 &pcfg_pull_none>; 922 }; 923 /omit-if-no-ref/ 924 pwm3m1_pins: pwm3m1-pins { 925 rockchip,pins = 926 /* pwm3_pin_m1 */ 927 <2 RK_PB0 5 &pcfg_pull_none>; 928 }; 929 }; 930 pwm4 { 931 /omit-if-no-ref/ 932 pwm4m0_pins: pwm4m0-pins { 933 rockchip,pins = 934 /* pwm4_pin_m0 */ 935 <0 RK_PC2 3 &pcfg_pull_none>; 936 }; 937 /omit-if-no-ref/ 938 pwm4m1_pins: pwm4m1-pins { 939 rockchip,pins = 940 /* pwm4_pin_m1 */ 941 <2 RK_PA7 5 &pcfg_pull_none>; 942 }; 943 }; 944 pwm5 { 945 /omit-if-no-ref/ 946 pwm5m0_pins: pwm5m0-pins { 947 rockchip,pins = 948 /* pwm5_pin_m0 */ 949 <0 RK_PC3 3 &pcfg_pull_none>; 950 }; 951 /omit-if-no-ref/ 952 pwm5m1_pins: pwm5m1-pins { 953 rockchip,pins = 954 /* pwm5_pin_m1 */ 955 <2 RK_PA6 5 &pcfg_pull_none>; 956 }; 957 }; 958 pwm6 { 959 /omit-if-no-ref/ 960 pwm6m0_pins: pwm6m0-pins { 961 rockchip,pins = 962 /* pwm6_pin_m0 */ 963 <0 RK_PB2 3 &pcfg_pull_none>; 964 }; 965 /omit-if-no-ref/ 966 pwm6m1_pins: pwm6m1-pins { 967 rockchip,pins = 968 /* pwm6_pin_m1 */ 969 <2 RK_PD4 5 &pcfg_pull_none>; 970 }; 971 }; 972 pwm7 { 973 /omit-if-no-ref/ 974 pwm7m0_pins: pwm7m0-pins { 975 rockchip,pins = 976 /* pwm7_pin_m0 */ 977 <0 RK_PB1 3 &pcfg_pull_none>; 978 }; 979 /omit-if-no-ref/ 980 pwm7m1_pins: pwm7m1-pins { 981 rockchip,pins = 982 /* pwm7_pin_m1 */ 983 <3 RK_PA0 5 &pcfg_pull_none>; 984 }; 985 }; 986 pwm8 { 987 /omit-if-no-ref/ 988 pwm8m0_pins: pwm8m0-pins { 989 rockchip,pins = 990 /* pwm8_pin_m0 */ 991 <3 RK_PA4 6 &pcfg_pull_none>; 992 }; 993 /omit-if-no-ref/ 994 pwm8m1_pins: pwm8m1-pins { 995 rockchip,pins = 996 /* pwm8_pin_m1 */ 997 <2 RK_PD7 5 &pcfg_pull_none>; 998 }; 999 }; 1000 pwm9 { 1001 /omit-if-no-ref/ 1002 pwm9m0_pins: pwm9m0-pins { 1003 rockchip,pins = 1004 /* pwm9_pin_m0 */ 1005 <3 RK_PA5 6 &pcfg_pull_none>; 1006 }; 1007 /omit-if-no-ref/ 1008 pwm9m1_pins: pwm9m1-pins { 1009 rockchip,pins = 1010 /* pwm9_pin_m1 */ 1011 <2 RK_PD6 5 &pcfg_pull_none>; 1012 }; 1013 }; 1014 pwm10 { 1015 /omit-if-no-ref/ 1016 pwm10m0_pins: pwm10m0-pins { 1017 rockchip,pins = 1018 /* pwm10_pin_m0 */ 1019 <3 RK_PA6 6 &pcfg_pull_none>; 1020 }; 1021 /omit-if-no-ref/ 1022 pwm10m1_pins: pwm10m1-pins { 1023 rockchip,pins = 1024 /* pwm10_pin_m1 */ 1025 <2 RK_PD5 5 &pcfg_pull_none>; 1026 }; 1027 }; 1028 pwm11 { 1029 /omit-if-no-ref/ 1030 pwm11m0_pins: pwm11m0-pins { 1031 rockchip,pins = 1032 /* pwm11_pin_m0 */ 1033 <3 RK_PA7 6 &pcfg_pull_none>; 1034 }; 1035 /omit-if-no-ref/ 1036 pwm11m1_pins: pwm11m1-pins { 1037 rockchip,pins = 1038 /* pwm11_pin_m1 */ 1039 <3 RK_PA1 5 &pcfg_pull_none>; 1040 }; 1041 }; 1042 rgmii { 1043 /omit-if-no-ref/ 1044 rgmiim0_miim: rgmiim0-miim { 1045 rockchip,pins = 1046 /* rgmii_mdc_m0 */ 1047 <3 RK_PC4 2 &pcfg_pull_none>, 1048 /* rgmii_mdio_m0 */ 1049 <3 RK_PC3 2 &pcfg_pull_none>; 1050 }; 1051 /omit-if-no-ref/ 1052 rgmiim0_rxer: rgmiim0-rxer { 1053 rockchip,pins = 1054 /* rgmii_rxer_m0 */ 1055 <3 RK_PC2 2 &pcfg_pull_none>; 1056 }; 1057 /omit-if-no-ref/ 1058 rgmiim0_bus2: rgmiim0-bus2 { 1059 rockchip,pins = 1060 /* rgmii_rxd0_m0 */ 1061 <3 RK_PB6 2 &pcfg_pull_none>, 1062 /* rgmii_rxd1_m0 */ 1063 <3 RK_PB7 2 &pcfg_pull_none>, 1064 /* rgmii_rxdv_m0 */ 1065 <3 RK_PC1 2 &pcfg_pull_none>, 1066 /* rgmii_txd0_m0 */ 1067 <3 RK_PB3 2 &pcfg_pull_none_drv_level_3>, 1068 /* rgmii_txd1_m0 */ 1069 <3 RK_PB4 2 &pcfg_pull_none_drv_level_3>, 1070 /* rgmii_txen_m0 */ 1071 <3 RK_PB5 2 &pcfg_pull_none_drv_level_3>; 1072 }; 1073 /omit-if-no-ref/ 1074 rgmiim0_bus4: rgmiim0-bus4 { 1075 rockchip,pins = 1076 /* rgmii_rxclk_m0 */ 1077 <3 RK_PC7 2 &pcfg_pull_none>, 1078 /* rgmii_rxd2_m0 */ 1079 <3 RK_PA7 2 &pcfg_pull_none>, 1080 /* rgmii_rxd3_m0 */ 1081 <3 RK_PB0 2 &pcfg_pull_none>, 1082 /* rgmii_txclk_m0 */ 1083 <3 RK_PC6 2 &pcfg_pull_none_drv_level_3>, 1084 /* rgmii_txd2_m0 */ 1085 <3 RK_PB1 2 &pcfg_pull_none_drv_level_3>, 1086 /* rgmii_txd3_m0 */ 1087 <3 RK_PB2 2 &pcfg_pull_none_drv_level_3>; 1088 }; 1089 /omit-if-no-ref/ 1090 rgmiim0_mclkinout: rgmiim0-mclkinout { 1091 rockchip,pins = 1092 /* rgmii_clk_m0 */ 1093 <3 RK_PC0 2 &pcfg_pull_none>; 1094 }; 1095 /omit-if-no-ref/ 1096 rgmiim1_miim: rgmiim1-miim { 1097 rockchip,pins = 1098 /* rgmii_mdc_m1 */ 1099 <2 RK_PC2 2 &pcfg_pull_none>, 1100 /* rgmii_mdio_m1 */ 1101 <2 RK_PC1 2 &pcfg_pull_none>; 1102 }; 1103 /omit-if-no-ref/ 1104 rgmiim1_rxer: rgmiim1-rxer { 1105 rockchip,pins = 1106 /* rgmii_rxer_m1 */ 1107 <2 RK_PC0 2 &pcfg_pull_none>; 1108 }; 1109 /omit-if-no-ref/ 1110 rgmiim1_bus2: rgmiim1-bus2 { 1111 rockchip,pins = 1112 /* rgmii_rxd0_m1 */ 1113 <2 RK_PB5 2 &pcfg_pull_none>, 1114 /* rgmii_rxd1_m1 */ 1115 <2 RK_PB6 2 &pcfg_pull_none>, 1116 /* rgmii_rxdv_m1 */ 1117 <2 RK_PB4 2 &pcfg_pull_none>, 1118 /* rgmii_txd0_m1 */ 1119 <2 RK_PC3 2 &pcfg_pull_none_drv_level_3>, 1120 /* rgmii_txd1_m1 */ 1121 <2 RK_PC4 2 &pcfg_pull_none_drv_level_3>, 1122 /* rgmii_txen_m1 */ 1123 <2 RK_PC6 2 &pcfg_pull_none_drv_level_3>; 1124 }; 1125 /omit-if-no-ref/ 1126 rgmiim1_bus4: rgmiim1-bus4 { 1127 rockchip,pins = 1128 /* rgmii_rxclk_m1 */ 1129 <2 RK_PD3 2 &pcfg_pull_none>, 1130 /* rgmii_rxd2_m1 */ 1131 <2 RK_PC7 2 &pcfg_pull_none>, 1132 /* rgmii_rxd3_m1 */ 1133 <2 RK_PD0 2 &pcfg_pull_none>, 1134 /* rgmii_txclk_m1 */ 1135 <2 RK_PD2 2 &pcfg_pull_none_drv_level_3>, 1136 /* rgmii_txd2_m1 */ 1137 <2 RK_PD1 2 &pcfg_pull_none_drv_level_3>, 1138 /* rgmii_txd3_m1 */ 1139 <2 RK_PA4 2 &pcfg_pull_none_drv_level_3>; 1140 }; 1141 /omit-if-no-ref/ 1142 rgmiim1_mclkinout: rgmiim1-mclkinout { 1143 rockchip,pins = 1144 /* rgmii_clk_m1 */ 1145 <2 RK_PB7 2 &pcfg_pull_none>; 1146 }; 1147 }; 1148 sdio { 1149 /omit-if-no-ref/ 1150 sdio_bus4: sdio-bus4 { 1151 rockchip,pins = 1152 /* sdio_d0 */ 1153 <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, 1154 /* sdio_d1 */ 1155 <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, 1156 /* sdio_d2 */ 1157 <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>, 1158 /* sdio_d3 */ 1159 <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>; 1160 }; 1161 /omit-if-no-ref/ 1162 sdio_clk: sdio-clk { 1163 rockchip,pins = 1164 /* sdio_clk */ 1165 <1 RK_PB2 1 &pcfg_pull_up_drv_level_2>; 1166 }; 1167 /omit-if-no-ref/ 1168 sdio_cmd: sdio-cmd { 1169 rockchip,pins = 1170 /* sdio_cmd */ 1171 <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>; 1172 }; 1173 /omit-if-no-ref/ 1174 sdio_det: sdio-det { 1175 rockchip,pins = 1176 /* sdio_det */ 1177 <1 RK_PD0 2 &pcfg_pull_none>; 1178 }; 1179 /omit-if-no-ref/ 1180 sdio_pwr: sdio-pwr { 1181 rockchip,pins = 1182 /* sdio_pwr */ 1183 <1 RK_PD1 2 &pcfg_pull_none>; 1184 }; 1185 }; 1186 sdmmc0 { 1187 /omit-if-no-ref/ 1188 sdmmc0_bus4: sdmmc0-bus4 { 1189 rockchip,pins = 1190 /* sdmmc0_d0 */ 1191 <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>, 1192 /* sdmmc0_d1 */ 1193 <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>, 1194 /* sdmmc0_d2 */ 1195 <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>, 1196 /* sdmmc0_d3 */ 1197 <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>; 1198 }; 1199 /omit-if-no-ref/ 1200 sdmmc0_clk: sdmmc0-clk { 1201 rockchip,pins = 1202 /* sdmmc0_clk */ 1203 <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>; 1204 }; 1205 /omit-if-no-ref/ 1206 sdmmc0_cmd: sdmmc0-cmd { 1207 rockchip,pins = 1208 /* sdmmc0_cmd */ 1209 <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>; 1210 }; 1211 /omit-if-no-ref/ 1212 sdmmc0_det: sdmmc0-det { 1213 rockchip,pins = 1214 /* sdmmc0_det */ 1215 <0 RK_PA3 1 &pcfg_pull_none>; 1216 }; 1217 /omit-if-no-ref/ 1218 sdmmc0_pwr: sdmmc0-pwr { 1219 rockchip,pins = 1220 /* sdmmc0_pwr */ 1221 <0 RK_PC0 1 &pcfg_pull_none>; 1222 }; 1223 1224 /omit-if-no-ref/ 1225 sdmmc0_idle_pins: sdmmc0-idle-pins { 1226 rockchip,pins = 1227 <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>, 1228 <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>, 1229 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>, 1230 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>, 1231 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>, 1232 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; 1233 }; 1234 }; 1235 spi0 { 1236 /omit-if-no-ref/ 1237 spi0m0_pins: spi0m0-pins { 1238 rockchip,pins = 1239 /* spi0_clk_m0 */ 1240 <0 RK_PB0 1 &pcfg_pull_up_drv_level_0>, 1241 /* spi0_miso_m0 */ 1242 <0 RK_PA7 1 &pcfg_pull_up_drv_level_0>, 1243 /* spi0_mosi_m0 */ 1244 <0 RK_PA6 1 &pcfg_pull_up_drv_level_0>; 1245 }; 1246 /omit-if-no-ref/ 1247 spi0m0_cs0: spi0m0-cs0 { 1248 rockchip,pins = 1249 /* spi0_cs0n_m0 */ 1250 <0 RK_PA5 1 &pcfg_pull_up_drv_level_0>; 1251 }; 1252 /omit-if-no-ref/ 1253 spi0m0_cs1: spi0m0-cs1 { 1254 rockchip,pins = 1255 /* spi0_cs1n_m0 */ 1256 <0 RK_PA4 1 &pcfg_pull_up_drv_level_0>; 1257 }; 1258 /omit-if-no-ref/ 1259 spi0m1_pins: spi0m1-pins { 1260 rockchip,pins = 1261 /* spi0_clk_m1 */ 1262 <2 RK_PA1 1 &pcfg_pull_up_drv_level_0>, 1263 /* spi0_miso_m1 */ 1264 <1 RK_PD7 1 &pcfg_pull_up_drv_level_0>, 1265 /* spi0_mosi_m1 */ 1266 <1 RK_PD6 1 &pcfg_pull_up_drv_level_0>; 1267 }; 1268 /omit-if-no-ref/ 1269 spi0m1_cs0: spi0m1-cs0 { 1270 rockchip,pins = 1271 /* spi0_cs0n_m1 */ 1272 <2 RK_PA0 1 &pcfg_pull_up_drv_level_0>; 1273 }; 1274 /omit-if-no-ref/ 1275 spi0m1_cs1: spi0m1-cs1 { 1276 rockchip,pins = 1277 /* spi0_cs1n_m1 */ 1278 <1 RK_PD5 1 &pcfg_pull_up_drv_level_0>; 1279 }; 1280 /omit-if-no-ref/ 1281 spi0m2_pins: spi0m2-pins { 1282 rockchip,pins = 1283 /* spi0_clk_m2 */ 1284 <2 RK_PB2 6 &pcfg_pull_up_drv_level_0>, 1285 /* spi0_miso_m2 */ 1286 <2 RK_PB1 6 &pcfg_pull_up_drv_level_0>, 1287 /* spi0_mosi_m2 */ 1288 <2 RK_PB0 6 &pcfg_pull_up_drv_level_0>; 1289 }; 1290 /omit-if-no-ref/ 1291 spi0m2_cs0: spi0m2-cs0 { 1292 rockchip,pins = 1293 /* spi0_cs0n_m2 */ 1294 <2 RK_PA7 6 &pcfg_pull_up_drv_level_0>; 1295 }; 1296 /omit-if-no-ref/ 1297 spi0m2_cs1: spi0m2-cs1 { 1298 rockchip,pins = 1299 /* spi0_cs1n_m2 */ 1300 <2 RK_PB3 6 &pcfg_pull_up_drv_level_0>; 1301 }; 1302 }; 1303 spi1 { 1304 /omit-if-no-ref/ 1305 spi1m0_pins: spi1m0-pins { 1306 rockchip,pins = 1307 /* spi1_clk_m0 */ 1308 <3 RK_PC0 5 &pcfg_pull_up_drv_level_0>, 1309 /* spi1_miso_m0 */ 1310 <3 RK_PB7 5 &pcfg_pull_up_drv_level_0>, 1311 /* spi1_mosi_m0 */ 1312 <3 RK_PB6 5 &pcfg_pull_up_drv_level_0>; 1313 }; 1314 /omit-if-no-ref/ 1315 spi1m0_cs0: spi1m0-cs0 { 1316 rockchip,pins = 1317 /* spi1_cs0n_m0 */ 1318 <3 RK_PB5 5 &pcfg_pull_up_drv_level_0>; 1319 }; 1320 /omit-if-no-ref/ 1321 spi1m0_cs1: spi1m0-cs1 { 1322 rockchip,pins = 1323 /* spi1_cs1n_m0 */ 1324 <3 RK_PB4 5 &pcfg_pull_up_drv_level_0>; 1325 }; 1326 /omit-if-no-ref/ 1327 spi1m1_pins: spi1m1-pins { 1328 rockchip,pins = 1329 /* spi1_clk_m1 */ 1330 <1 RK_PC6 3 &pcfg_pull_up_drv_level_0>, 1331 /* spi1_miso_m1 */ 1332 <1 RK_PC5 3 &pcfg_pull_up_drv_level_0>, 1333 /* spi1_mosi_m1 */ 1334 <1 RK_PC4 3 &pcfg_pull_up_drv_level_0>; 1335 }; 1336 /omit-if-no-ref/ 1337 spi1m1_cs0: spi1m1-cs0 { 1338 rockchip,pins = 1339 /* spi1_cs0n_m1 */ 1340 <1 RK_PC7 3 &pcfg_pull_up_drv_level_0>; 1341 }; 1342 /omit-if-no-ref/ 1343 spi1m1_cs1: spi1m1-cs1 { 1344 rockchip,pins = 1345 /* spi1_cs1n_m1 */ 1346 <1 RK_PD0 3 &pcfg_pull_up_drv_level_0>; 1347 }; 1348 /omit-if-no-ref/ 1349 spi1m2_pins: spi1m2-pins { 1350 rockchip,pins = 1351 /* spi1_clk_m2 */ 1352 <2 RK_PD5 6 &pcfg_pull_up_drv_level_0>, 1353 /* spi1_miso_m2 */ 1354 <2 RK_PD7 6 &pcfg_pull_up_drv_level_0>, 1355 /* spi1_mosi_m2 */ 1356 <2 RK_PD6 6 &pcfg_pull_up_drv_level_0>; 1357 }; 1358 /omit-if-no-ref/ 1359 spi1m2_cs0: spi1m2-cs0 { 1360 rockchip,pins = 1361 /* spi1_cs0n_m2 */ 1362 <2 RK_PD4 6 &pcfg_pull_up_drv_level_0>; 1363 }; 1364 /omit-if-no-ref/ 1365 spi1m2_cs1: spi1m2-cs1 { 1366 rockchip,pins = 1367 /* spi1_cs1n_m2 */ 1368 <3 RK_PA0 6 &pcfg_pull_up_drv_level_0>; 1369 }; 1370 }; 1371 tsadc { 1372 /omit-if-no-ref/ 1373 tsadcm0_shut: tsadcm0-shut { 1374 rockchip,pins = 1375 /* tsadcm0_shut */ 1376 <0 RK_PA1 1 &pcfg_pull_none>; 1377 }; 1378 /omit-if-no-ref/ 1379 tsadcm1_shut: tsadcm1-shut { 1380 rockchip,pins = 1381 /* tsadcm1_shut */ 1382 <0 RK_PB2 2 &pcfg_pull_none>; 1383 }; 1384 /omit-if-no-ref/ 1385 tsadc_shutorg: tsadc-shutorg { 1386 rockchip,pins = 1387 /* tsadc_shutorg */ 1388 <0 RK_PA1 2 &pcfg_pull_none>; 1389 }; 1390 }; 1391 uart0 { 1392 /omit-if-no-ref/ 1393 uart0_xfer: uart0-xfer { 1394 rockchip,pins = 1395 /* uart0_rx */ 1396 <1 RK_PC2 1 &pcfg_pull_up>, 1397 /* uart0_tx */ 1398 <1 RK_PC3 1 &pcfg_pull_up>; 1399 }; 1400 /omit-if-no-ref/ 1401 uart0_ctsn: uart0-ctsn { 1402 rockchip,pins = 1403 /* uart0_ctsn */ 1404 <1 RK_PC1 1 &pcfg_pull_none>; 1405 }; 1406 /omit-if-no-ref/ 1407 uart0_rtsn: uart0-rtsn { 1408 rockchip,pins = 1409 /* uart0_rtsn */ 1410 <1 RK_PC0 1 &pcfg_pull_none>; 1411 }; 1412 }; 1413 uart1 { 1414 /omit-if-no-ref/ 1415 uart1m0_xfer: uart1m0-xfer { 1416 rockchip,pins = 1417 /* uart1_rx_m0 */ 1418 <0 RK_PB7 2 &pcfg_pull_up>, 1419 /* uart1_tx_m0 */ 1420 <0 RK_PB6 2 &pcfg_pull_up>; 1421 }; 1422 /omit-if-no-ref/ 1423 uart1m0_ctsn: uart1m0-ctsn { 1424 rockchip,pins = 1425 /* uart1m0_ctsn */ 1426 <0 RK_PC1 2 &pcfg_pull_none>; 1427 }; 1428 /omit-if-no-ref/ 1429 uart1m0_rtsn: uart1m0-rtsn { 1430 rockchip,pins = 1431 /* uart1m0_rtsn */ 1432 <0 RK_PC0 2 &pcfg_pull_none>; 1433 }; 1434 /omit-if-no-ref/ 1435 uart1m1_xfer: uart1m1-xfer { 1436 rockchip,pins = 1437 /* uart1_rx_m1 */ 1438 <1 RK_PD1 5 &pcfg_pull_up>, 1439 /* uart1_tx_m1 */ 1440 <1 RK_PD0 5 &pcfg_pull_up>; 1441 }; 1442 /omit-if-no-ref/ 1443 uart1m1_ctsn: uart1m1-ctsn { 1444 rockchip,pins = 1445 /* uart1m1_ctsn */ 1446 <1 RK_PC7 5 &pcfg_pull_none>; 1447 }; 1448 /omit-if-no-ref/ 1449 uart1m1_rtsn: uart1m1-rtsn { 1450 rockchip,pins = 1451 /* uart1m1_rtsn */ 1452 <1 RK_PC6 5 &pcfg_pull_none>; 1453 }; 1454 }; 1455 uart2 { 1456 /omit-if-no-ref/ 1457 uart2m0_xfer: uart2m0-xfer { 1458 rockchip,pins = 1459 /* uart2_rx_m0 */ 1460 <1 RK_PA4 3 &pcfg_pull_up>, 1461 /* uart2_tx_m0 */ 1462 <1 RK_PA5 3 &pcfg_pull_up>; 1463 }; 1464 /omit-if-no-ref/ 1465 uart2m1_xfer: uart2m1-xfer { 1466 rockchip,pins = 1467 /* uart2_rx_m1 */ 1468 <3 RK_PA3 1 &pcfg_pull_up>, 1469 /* uart2_tx_m1 */ 1470 <3 RK_PA2 1 &pcfg_pull_up>; 1471 }; 1472 }; 1473 uart3 { 1474 /omit-if-no-ref/ 1475 uart3m0_xfer: uart3m0-xfer { 1476 rockchip,pins = 1477 /* uart3_rx_m0 */ 1478 <3 RK_PC7 4 &pcfg_pull_up>, 1479 /* uart3_tx_m0 */ 1480 <3 RK_PC6 4 &pcfg_pull_up>; 1481 }; 1482 /omit-if-no-ref/ 1483 uart3m0_ctsn: uart3m0-ctsn { 1484 rockchip,pins = 1485 /* uart3m0_ctsn */ 1486 <3 RK_PC5 4 &pcfg_pull_none>; 1487 }; 1488 /omit-if-no-ref/ 1489 uart3m0_rtsn: uart3m0-rtsn { 1490 rockchip,pins = 1491 /* uart3m0_rtsn */ 1492 <3 RK_PC4 4 &pcfg_pull_none>; 1493 }; 1494 /omit-if-no-ref/ 1495 uart3m1_xfer: uart3m1-xfer { 1496 rockchip,pins = 1497 /* uart3_rx_m1 */ 1498 <1 RK_PA6 2 &pcfg_pull_up>, 1499 /* uart3_tx_m1 */ 1500 <1 RK_PA7 2 &pcfg_pull_up>; 1501 }; 1502 /omit-if-no-ref/ 1503 uart3m1_ctsn: uart3m1-ctsn { 1504 rockchip,pins = 1505 /* uart3m1_ctsn */ 1506 <1 RK_PB1 2 &pcfg_pull_none>; 1507 }; 1508 /omit-if-no-ref/ 1509 uart3m1_rtsn: uart3m1-rtsn { 1510 rockchip,pins = 1511 /* uart3m1_rtsn */ 1512 <1 RK_PB0 2 &pcfg_pull_none>; 1513 }; 1514 /omit-if-no-ref/ 1515 uart3m2_xfer: uart3m2-xfer { 1516 rockchip,pins = 1517 /* uart3_rx_m2 */ 1518 <3 RK_PA1 4 &pcfg_pull_up>, 1519 /* uart3_tx_m2 */ 1520 <3 RK_PA0 4 &pcfg_pull_up>; 1521 }; 1522 /omit-if-no-ref/ 1523 uart3m2_ctsn: uart3m2-ctsn { 1524 rockchip,pins = 1525 /* uart3m2_ctsn */ 1526 <2 RK_PD7 4 &pcfg_pull_none>; 1527 }; 1528 /omit-if-no-ref/ 1529 uart3m2_rtsn: uart3m2-rtsn { 1530 rockchip,pins = 1531 /* uart3m2_rtsn */ 1532 <2 RK_PD6 4 &pcfg_pull_none>; 1533 }; 1534 }; 1535 uart4 { 1536 /omit-if-no-ref/ 1537 uart4m0_xfer: uart4m0-xfer { 1538 rockchip,pins = 1539 /* uart4_rx_m0 */ 1540 <3 RK_PA5 4 &pcfg_pull_up>, 1541 /* uart4_tx_m0 */ 1542 <3 RK_PA4 4 &pcfg_pull_up>; 1543 }; 1544 /omit-if-no-ref/ 1545 uart4m0_ctsn: uart4m0-ctsn { 1546 rockchip,pins = 1547 /* uart4m0_ctsn */ 1548 <3 RK_PB3 4 &pcfg_pull_none>; 1549 }; 1550 /omit-if-no-ref/ 1551 uart4m0_rtsn: uart4m0-rtsn { 1552 rockchip,pins = 1553 /* uart4m0_rtsn */ 1554 <3 RK_PB2 4 &pcfg_pull_none>; 1555 }; 1556 /omit-if-no-ref/ 1557 uart4m1_xfer: uart4m1-xfer { 1558 rockchip,pins = 1559 /* uart4_rx_m1 */ 1560 <2 RK_PA7 4 &pcfg_pull_up>, 1561 /* uart4_tx_m1 */ 1562 <2 RK_PA6 4 &pcfg_pull_up>; 1563 }; 1564 /omit-if-no-ref/ 1565 uart4m1_ctsn: uart4m1-ctsn { 1566 rockchip,pins = 1567 /* uart4m1_ctsn */ 1568 <2 RK_PA5 4 &pcfg_pull_none>; 1569 }; 1570 /omit-if-no-ref/ 1571 uart4m1_rtsn: uart4m1-rtsn { 1572 rockchip,pins = 1573 /* uart4m1_rtsn */ 1574 <2 RK_PA4 4 &pcfg_pull_none>; 1575 }; 1576 /omit-if-no-ref/ 1577 uart4m2_xfer: uart4m2-xfer { 1578 rockchip,pins = 1579 /* uart4_rx_m2 */ 1580 <1 RK_PD4 3 &pcfg_pull_up>, 1581 /* uart4_tx_m2 */ 1582 <1 RK_PD5 3 &pcfg_pull_up>; 1583 }; 1584 /omit-if-no-ref/ 1585 uart4m2_ctsn: uart4m2-ctsn { 1586 rockchip,pins = 1587 /* uart4m2_ctsn */ 1588 <1 RK_PD3 3 &pcfg_pull_none>; 1589 }; 1590 /omit-if-no-ref/ 1591 uart4m2_rtsn: uart4m2-rtsn { 1592 rockchip,pins = 1593 /* uart4m2_rtsn */ 1594 <1 RK_PD2 3 &pcfg_pull_none>; 1595 }; 1596 }; 1597 uart5 { 1598 /omit-if-no-ref/ 1599 uart5m0_xfer: uart5m0-xfer { 1600 rockchip,pins = 1601 /* uart5_rx_m0 */ 1602 <3 RK_PA7 4 &pcfg_pull_up>, 1603 /* uart5_tx_m0 */ 1604 <3 RK_PA6 4 &pcfg_pull_up>; 1605 }; 1606 /omit-if-no-ref/ 1607 uart5m0_ctsn: uart5m0-ctsn { 1608 rockchip,pins = 1609 /* uart5m0_ctsn */ 1610 <3 RK_PB1 4 &pcfg_pull_none>; 1611 }; 1612 /omit-if-no-ref/ 1613 uart5m0_rtsn: uart5m0-rtsn { 1614 rockchip,pins = 1615 /* uart5m0_rtsn */ 1616 <3 RK_PB0 4 &pcfg_pull_none>; 1617 }; 1618 /omit-if-no-ref/ 1619 uart5m1_xfer: uart5m1-xfer { 1620 rockchip,pins = 1621 /* uart5_rx_m1 */ 1622 <2 RK_PB1 4 &pcfg_pull_up>, 1623 /* uart5_tx_m1 */ 1624 <2 RK_PB0 4 &pcfg_pull_up>; 1625 }; 1626 /omit-if-no-ref/ 1627 uart5m1_ctsn: uart5m1-ctsn { 1628 rockchip,pins = 1629 /* uart5m1_ctsn */ 1630 <2 RK_PB3 4 &pcfg_pull_none>; 1631 }; 1632 /omit-if-no-ref/ 1633 uart5m1_rtsn: uart5m1-rtsn { 1634 rockchip,pins = 1635 /* uart5m1_rtsn */ 1636 <2 RK_PB2 4 &pcfg_pull_none>; 1637 }; 1638 /omit-if-no-ref/ 1639 uart5m2_xfer: uart5m2-xfer { 1640 rockchip,pins = 1641 /* uart5_rx_m2 */ 1642 <2 RK_PA1 3 &pcfg_pull_up>, 1643 /* uart5_tx_m2 */ 1644 <2 RK_PA0 3 &pcfg_pull_up>; 1645 }; 1646 /omit-if-no-ref/ 1647 uart5m2_ctsn: uart5m2-ctsn { 1648 rockchip,pins = 1649 /* uart5m2_ctsn */ 1650 <2 RK_PA3 3 &pcfg_pull_none>; 1651 }; 1652 /omit-if-no-ref/ 1653 uart5m2_rtsn: uart5m2-rtsn { 1654 rockchip,pins = 1655 /* uart5m2_rtsn */ 1656 <2 RK_PA2 3 &pcfg_pull_none>; 1657 }; 1658 }; 1659}; 1660&pinctrl { 1661 gpio { 1662 /omit-if-no-ref/ 1663 uart0_rtsn_gpio: uart0-rts-pin { 1664 rockchip,pins = 1665 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; 1666 }; 1667 }; 1668 pwm-pull-down { 1669 /omit-if-no-ref/ 1670 pwm0m0_pins_pull_down: pwm0m0-pins { 1671 rockchip,pins = 1672 /* pwm0_pin_m0 */ 1673 <0 RK_PB6 3 &pcfg_pull_down>; 1674 }; 1675 /omit-if-no-ref/ 1676 pwm0m1_pins_pull_down: pwm0m1-pins { 1677 rockchip,pins = 1678 /* pwm0_pin_m1 */ 1679 <2 RK_PB3 5 &pcfg_pull_down>; 1680 }; 1681 /omit-if-no-ref/ 1682 pwm1m0_pins_pull_down: pwm1m0-pins { 1683 rockchip,pins = 1684 /* pwm1_pin_m0 */ 1685 <0 RK_PB7 3 &pcfg_pull_down>; 1686 }; 1687 /omit-if-no-ref/ 1688 pwm1m1_pins_pull_down: pwm1m1-pins { 1689 rockchip,pins = 1690 /* pwm1_pin_m1 */ 1691 <2 RK_PB2 5 &pcfg_pull_down>; 1692 }; 1693 /omit-if-no-ref/ 1694 pwm2m0_pins_pull_down: pwm2m0-pins { 1695 rockchip,pins = 1696 /* pwm2_pin_m0 */ 1697 <0 RK_PC0 3 &pcfg_pull_down>; 1698 }; 1699 /omit-if-no-ref/ 1700 pwm2m1_pins_pull_down: pwm2m1-pins { 1701 rockchip,pins = 1702 /* pwm2_pin_m1 */ 1703 <2 RK_PB1 5 &pcfg_pull_down>; 1704 }; 1705 /omit-if-no-ref/ 1706 pwm3m0_pins_pull_down: pwm3m0-pins { 1707 rockchip,pins = 1708 /* pwm3_pin_m0 */ 1709 <0 RK_PC1 3 &pcfg_pull_down>; 1710 }; 1711 /omit-if-no-ref/ 1712 pwm3m1_pins_pull_down: pwm3m1-pins { 1713 rockchip,pins = 1714 /* pwm3_pin_m1 */ 1715 <2 RK_PB0 5 &pcfg_pull_down>; 1716 }; 1717 /omit-if-no-ref/ 1718 pwm4m0_pins_pull_down: pwm4m0-pins { 1719 rockchip,pins = 1720 /* pwm4_pin_m0 */ 1721 <0 RK_PC2 3 &pcfg_pull_down>; 1722 }; 1723 /omit-if-no-ref/ 1724 pwm4m1_pins_pull_down: pwm4m1-pins { 1725 rockchip,pins = 1726 /* pwm4_pin_m1 */ 1727 <2 RK_PA7 5 &pcfg_pull_down>; 1728 }; 1729 /omit-if-no-ref/ 1730 pwm5m0_pins_pull_down: pwm5m0-pins { 1731 rockchip,pins = 1732 /* pwm5_pin_m0 */ 1733 <0 RK_PC3 3 &pcfg_pull_down>; 1734 }; 1735 /omit-if-no-ref/ 1736 pwm5m1_pins_pull_down: pwm5m1-pins { 1737 rockchip,pins = 1738 /* pwm5_pin_m1 */ 1739 <2 RK_PA6 5 &pcfg_pull_down>; 1740 }; 1741 /omit-if-no-ref/ 1742 pwm6m0_pins_pull_down: pwm6m0-pins { 1743 rockchip,pins = 1744 /* pwm6_pin_m0 */ 1745 <0 RK_PB2 3 &pcfg_pull_down>; 1746 }; 1747 /omit-if-no-ref/ 1748 pwm6m1_pins_pull_up: pwm6m1-pins-pull-up { 1749 rockchip,pins = 1750 /* pwm6_pin_m1 */ 1751 <2 RK_PD4 5 &pcfg_pull_up>; 1752 }; 1753 /omit-if-no-ref/ 1754 pwm7m0_pins_pull_down: pwm7m0-pins { 1755 rockchip,pins = 1756 /* pwm7_pin_m0 */ 1757 <0 RK_PB1 3 &pcfg_pull_down>; 1758 }; 1759 /omit-if-no-ref/ 1760 pwm7m1_pins_pull_up: pwm7m1-pins-pull-up { 1761 rockchip,pins = 1762 /* pwm7_pin_m1 */ 1763 <3 RK_PA0 5 &pcfg_pull_up>; 1764 }; 1765 /omit-if-no-ref/ 1766 pwm8m0_pins_pull_down: pwm8m0-pins { 1767 rockchip,pins = 1768 /* pwm8_pin_m0 */ 1769 <3 RK_PA4 6 &pcfg_pull_down>; 1770 }; 1771 /omit-if-no-ref/ 1772 pwm8m1_pins_pull_down: pwm8m1-pins { 1773 rockchip,pins = 1774 /* pwm8_pin_m1 */ 1775 <2 RK_PD7 5 &pcfg_pull_down>; 1776 }; 1777 /omit-if-no-ref/ 1778 pwm9m0_pins_pull_down: pwm9m0-pins { 1779 rockchip,pins = 1780 /* pwm9_pin_m0 */ 1781 <3 RK_PA5 6 &pcfg_pull_down>; 1782 }; 1783 /omit-if-no-ref/ 1784 pwm9m1_pins_pull_down: pwm9m1-pins { 1785 rockchip,pins = 1786 /* pwm9_pin_m1 */ 1787 <2 RK_PD6 5 &pcfg_pull_down>; 1788 }; 1789 /omit-if-no-ref/ 1790 pwm10m0_pins_pull_down: pwm10m0-pins { 1791 rockchip,pins = 1792 /* pwm10_pin_m0 */ 1793 <3 RK_PA6 6 &pcfg_pull_down>; 1794 }; 1795 /omit-if-no-ref/ 1796 pwm10m1_pins_pull_down: pwm10m1-pins { 1797 rockchip,pins = 1798 /* pwm10_pin_m1 */ 1799 <2 RK_PD5 5 &pcfg_pull_down>; 1800 }; 1801 /omit-if-no-ref/ 1802 pwm11m0_pins_pull_down: pwm11m0-pins { 1803 rockchip,pins = 1804 /* pwm11_pin_m0 */ 1805 <3 RK_PA7 6 &pcfg_pull_down>; 1806 }; 1807 /omit-if-no-ref/ 1808 pwm11m1_pins_pull_down: pwm11m1-pins { 1809 rockchip,pins = 1810 /* pwm11_pin_m1 */ 1811 <3 RK_PA1 5 &pcfg_pull_down>; 1812 }; 1813 }; 1814 spi0-hs { 1815 /omit-if-no-ref/ 1816 spi0m0_pins_hs: spi0m0-pins { 1817 rockchip,pins = 1818 /* spi0_clk_m0 */ 1819 <0 RK_PB0 1 &pcfg_pull_up_drv_level_1>, 1820 /* spi0_miso_m0 */ 1821 <0 RK_PA7 1 &pcfg_pull_up_drv_level_1>, 1822 /* spi0_mosi_m0 */ 1823 <0 RK_PA6 1 &pcfg_pull_up_drv_level_1>; 1824 }; 1825 /omit-if-no-ref/ 1826 spi0m1_pins_hs: spi0m1-pins { 1827 rockchip,pins = 1828 /* spi0_clk_m1 */ 1829 <2 RK_PA1 1 &pcfg_pull_up_drv_level_1>, 1830 /* spi0_miso_m1 */ 1831 <1 RK_PD7 1 &pcfg_pull_up_drv_level_1>, 1832 /* spi0_mosi_m1 */ 1833 <1 RK_PD6 1 &pcfg_pull_up_drv_level_1>; 1834 }; 1835 /omit-if-no-ref/ 1836 spi0m2_pins_hs: spi0m2-pins { 1837 rockchip,pins = 1838 /* spi0_clk_m2 */ 1839 <2 RK_PB2 6 &pcfg_pull_up_drv_level_1>, 1840 /* spi0_miso_m2 */ 1841 <2 RK_PB1 6 &pcfg_pull_up_drv_level_1>, 1842 /* spi0_mosi_m2 */ 1843 <2 RK_PB0 6 &pcfg_pull_up_drv_level_1>; 1844 }; 1845 }; 1846 spi1-hs { 1847 /omit-if-no-ref/ 1848 spi1m0_pins_hs: spi1m0-pins { 1849 rockchip,pins = 1850 /* spi1_clk_m0 */ 1851 <3 RK_PC0 5 &pcfg_pull_up_drv_level_1>, 1852 /* spi1_miso_m0 */ 1853 <3 RK_PB7 5 &pcfg_pull_up_drv_level_1>, 1854 /* spi1_mosi_m0 */ 1855 <3 RK_PB6 5 &pcfg_pull_up_drv_level_1>; 1856 }; 1857 /omit-if-no-ref/ 1858 spi1m1_pins_hs: spi1m1-pins { 1859 rockchip,pins = 1860 /* spi1_clk_m1 */ 1861 <1 RK_PC6 3 &pcfg_pull_up_drv_level_1>, 1862 /* spi1_miso_m1 */ 1863 <1 RK_PC5 3 &pcfg_pull_up_drv_level_1>, 1864 /* spi1_mosi_m1 */ 1865 <1 RK_PC4 3 &pcfg_pull_up_drv_level_1>; 1866 }; 1867 /omit-if-no-ref/ 1868 spi1m2_pins_hs: spi1m2-pins { 1869 rockchip,pins = 1870 /* spi1_clk_m2 */ 1871 <2 RK_PD5 6 &pcfg_pull_up_drv_level_1>, 1872 /* spi1_miso_m2 */ 1873 <2 RK_PD7 6 &pcfg_pull_up_drv_level_1>, 1874 /* spi1_mosi_m2 */ 1875 <2 RK_PD6 6 &pcfg_pull_up_drv_level_1>; 1876 }; 1877 }; 1878 gmac_clk { 1879 /omit-if-no-ref/ 1880 rgmiim0_mclkinout_level0: rgmiim0_mclkinout-level0 { 1881 rockchip,pins = 1882 /* rgmiim0_clk */ 1883 <3 RK_PC0 2 &pcfg_pull_none_drv_level_0>; 1884 }; 1885 /omit-if-no-ref/ 1886 rgmiim0_mclkinout_level3: rgmiim0_mclkinout-level3 { 1887 rockchip,pins = 1888 /* rgmiim0_clk */ 1889 <3 RK_PC0 2 &pcfg_pull_none_drv_level_3>; 1890 }; 1891 /omit-if-no-ref/ 1892 rgmiim1_mclkinout_level0: rgmiim1_mclkinout-level0 { 1893 rockchip,pins = 1894 /* rgmiim1_clk */ 1895 <2 RK_PB7 2 &pcfg_pull_none_drv_level_0>; 1896 }; 1897 /omit-if-no-ref/ 1898 rgmiim1_mclkinout_level3: rgmiim1_mclkinout-level3 { 1899 rockchip,pins = 1900 /* rgmiim1_clk */ 1901 <2 RK_PB7 2 &pcfg_pull_none_drv_level_3>; 1902 }; 1903 }; 1904 rmii { 1905 /omit-if-no-ref/ 1906 rmiim0_miim: rmiim0-miim { 1907 rockchip,pins = 1908 /* rgmii_mdc_m0 */ 1909 <3 RK_PC4 2 &pcfg_pull_none_drv_level_0>, 1910 /* rgmii_mdio_m0 */ 1911 <3 RK_PC3 2 &pcfg_pull_none>; 1912 }; 1913 1914 /omit-if-no-ref/ 1915 rmiim0_bus2: rmiim0-bus2 { 1916 rockchip,pins = 1917 /* rgmii_rxd0_m0 */ 1918 <3 RK_PB6 2 &pcfg_pull_none>, 1919 /* rgmii_rxd1_m0 */ 1920 <3 RK_PB7 2 &pcfg_pull_none>, 1921 /* rgmii_rxdv_m0 */ 1922 <3 RK_PC1 2 &pcfg_pull_none>, 1923 /* rgmii_txd0_m0 */ 1924 <3 RK_PB3 2 &pcfg_pull_none_drv_level_0>, 1925 /* rgmii_txd1_m0 */ 1926 <3 RK_PB4 2 &pcfg_pull_none_drv_level_0>, 1927 /* rgmii_txen_m0 */ 1928 <3 RK_PB5 2 &pcfg_pull_none_drv_level_0>; 1929 }; 1930 /omit-if-no-ref/ 1931 rmiim1_miim: rmiim1-miim { 1932 rockchip,pins = 1933 /* rgmii_mdc_m1 */ 1934 <2 RK_PC2 2 &pcfg_pull_none_drv_level_0>, 1935 /* rgmii_mdio_m1 */ 1936 <2 RK_PC1 2 &pcfg_pull_none>; 1937 }; 1938 /omit-if-no-ref/ 1939 rmiim1_bus2: rmiim1-bus2 { 1940 rockchip,pins = 1941 /* rgmii_rxd0_m1 */ 1942 <2 RK_PB5 2 &pcfg_pull_none>, 1943 /* rgmii_rxd1_m1 */ 1944 <2 RK_PB6 2 &pcfg_pull_none>, 1945 /* rgmii_rxdv_m1 */ 1946 <2 RK_PB4 2 &pcfg_pull_none>, 1947 /* rgmii_txd0_m1 */ 1948 <2 RK_PC3 2 &pcfg_pull_none_drv_level_0>, 1949 /* rgmii_txd1_m1 */ 1950 <2 RK_PC4 2 &pcfg_pull_none_drv_level_0>, 1951 /* rgmii_txen_m1 */ 1952 <2 RK_PC6 2 &pcfg_pull_none_drv_level_0>; 1953 }; 1954 }; 1955}; 1956