1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/ { 7*4882a593Smuzhiyun chosen { 8*4882a593Smuzhiyun bootargs = "earlycon=uart8250,mmio32,0xff570000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait snd_aloop.index=7"; 9*4882a593Smuzhiyun }; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun vcc5v0_sys: vccsys { 12*4882a593Smuzhiyun compatible = "regulator-fixed"; 13*4882a593Smuzhiyun regulator-name = "vcc5v0_sys"; 14*4882a593Smuzhiyun regulator-always-on; 15*4882a593Smuzhiyun regulator-boot-on; 16*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 17*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun vdd_npu: vdd-npu { 21*4882a593Smuzhiyun compatible = "pwm-regulator"; 22*4882a593Smuzhiyun pwms = <&pwm0 0 5000 1>; 23*4882a593Smuzhiyun regulator-name = "vdd_npu"; 24*4882a593Smuzhiyun regulator-min-microvolt = <650000>; 25*4882a593Smuzhiyun regulator-max-microvolt = <950000>; 26*4882a593Smuzhiyun regulator-init-microvolt = <800000>; 27*4882a593Smuzhiyun regulator-always-on; 28*4882a593Smuzhiyun regulator-boot-on; 29*4882a593Smuzhiyun regulator-settling-time-up-us = <250>; 30*4882a593Smuzhiyun pwm-supply = <&vcc5v0_sys>; 31*4882a593Smuzhiyun status = "okay"; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun vdd_vepu: vdd-vepu { 35*4882a593Smuzhiyun compatible = "pwm-regulator"; 36*4882a593Smuzhiyun pwms = <&pwm1 0 5000 1>; 37*4882a593Smuzhiyun regulator-name = "vdd_vepu"; 38*4882a593Smuzhiyun regulator-min-microvolt = <650000>; 39*4882a593Smuzhiyun regulator-max-microvolt = <950000>; 40*4882a593Smuzhiyun regulator-init-microvolt = <800000>; 41*4882a593Smuzhiyun regulator-always-on; 42*4882a593Smuzhiyun regulator-boot-on; 43*4882a593Smuzhiyun regulator-settling-time-up-us = <250>; 44*4882a593Smuzhiyun pwm-supply = <&vcc5v0_sys>; 45*4882a593Smuzhiyun status = "okay"; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun}; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun&cpu0 { 50*4882a593Smuzhiyun cpu-supply = <&vdd_arm>; 51*4882a593Smuzhiyun}; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun&cpu_tsadc { 54*4882a593Smuzhiyun status = "okay"; 55*4882a593Smuzhiyun}; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun&display_subsystem { 58*4882a593Smuzhiyun status = "okay"; 59*4882a593Smuzhiyun}; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun&fiq_debugger { 62*4882a593Smuzhiyun status = "okay"; 63*4882a593Smuzhiyun}; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun&mpp_srv { 66*4882a593Smuzhiyun status = "okay"; 67*4882a593Smuzhiyun}; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun&nandc { 70*4882a593Smuzhiyun /delete-property/ pinctrl-names; 71*4882a593Smuzhiyun /delete-property/ pinctrl-0; 72*4882a593Smuzhiyun status = "disabled"; 73*4882a593Smuzhiyun #address-cells = <1>; 74*4882a593Smuzhiyun #size-cells = <0>; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun nand@0 { 77*4882a593Smuzhiyun reg = <0>; 78*4882a593Smuzhiyun nand-bus-width = <8>; 79*4882a593Smuzhiyun nand-ecc-mode = "hw"; 80*4882a593Smuzhiyun nand-ecc-strength = <16>; 81*4882a593Smuzhiyun nand-ecc-step-size = <1024>; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun}; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun&npu { 86*4882a593Smuzhiyun npu-supply = <&vdd_npu>; 87*4882a593Smuzhiyun status = "okay"; 88*4882a593Smuzhiyun}; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun&npu_tsadc { 91*4882a593Smuzhiyun status = "okay"; 92*4882a593Smuzhiyun}; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun&optee { 95*4882a593Smuzhiyun status = "disabled"; 96*4882a593Smuzhiyun}; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun&otp { 99*4882a593Smuzhiyun status = "okay"; 100*4882a593Smuzhiyun}; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun&pinctrl { 103*4882a593Smuzhiyun pmic { 104*4882a593Smuzhiyun /omit-if-no-ref/ 105*4882a593Smuzhiyun pmic_int: pmic_int { 106*4882a593Smuzhiyun rockchip,pins = 107*4882a593Smuzhiyun <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /omit-if-no-ref/ 111*4882a593Smuzhiyun soc_slppin_gpio: soc_slppin_gpio { 112*4882a593Smuzhiyun rockchip,pins = 113*4882a593Smuzhiyun <0 RK_PB2 RK_FUNC_GPIO &pcfg_output_low>; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun /omit-if-no-ref/ 117*4882a593Smuzhiyun soc_slppin_slp: soc_slppin_slp { 118*4882a593Smuzhiyun rockchip,pins = 119*4882a593Smuzhiyun <0 RK_PB2 1 &pcfg_pull_none>; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun /omit-if-no-ref/ 123*4882a593Smuzhiyun soc_slppin_rst: soc_slppin_rst { 124*4882a593Smuzhiyun rockchip,pins = 125*4882a593Smuzhiyun <0 RK_PB2 2 &pcfg_pull_none>; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun}; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun&pwm0 { 131*4882a593Smuzhiyun status = "okay"; 132*4882a593Smuzhiyun pinctrl-names = "active"; 133*4882a593Smuzhiyun pinctrl-0 = <&pwm0m0_pins_pull_down>; 134*4882a593Smuzhiyun}; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun&pwm1 { 137*4882a593Smuzhiyun status = "okay"; 138*4882a593Smuzhiyun pinctrl-names = "active"; 139*4882a593Smuzhiyun pinctrl-0 = <&pwm1m0_pins_pull_down>; 140*4882a593Smuzhiyun}; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun&ramoops { 143*4882a593Smuzhiyun status = "okay"; 144*4882a593Smuzhiyun}; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun&rk_rga { 147*4882a593Smuzhiyun status = "okay"; 148*4882a593Smuzhiyun}; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun&rkisp { 151*4882a593Smuzhiyun status = "okay"; 152*4882a593Smuzhiyun}; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun&rkisp_vir0 { 155*4882a593Smuzhiyun status = "okay"; 156*4882a593Smuzhiyun}; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun&rkisp_mmu { 159*4882a593Smuzhiyun status = "disabled"; 160*4882a593Smuzhiyun}; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun&rkispp { 163*4882a593Smuzhiyun rockchip,restart-monitor-en; 164*4882a593Smuzhiyun status = "okay"; 165*4882a593Smuzhiyun}; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun&rkispp_vir0 { 168*4882a593Smuzhiyun status = "okay"; 169*4882a593Smuzhiyun}; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun&rkispp_mmu { 172*4882a593Smuzhiyun status = "okay"; 173*4882a593Smuzhiyun}; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun&rkvdec { 176*4882a593Smuzhiyun status = "okay"; 177*4882a593Smuzhiyun}; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun&rkvdec_mmu { 180*4882a593Smuzhiyun status = "okay"; 181*4882a593Smuzhiyun}; 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun&rkvenc { 184*4882a593Smuzhiyun venc-supply = <&vdd_vepu>; 185*4882a593Smuzhiyun status = "okay"; 186*4882a593Smuzhiyun}; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun&rkvenc_mmu { 189*4882a593Smuzhiyun status = "okay"; 190*4882a593Smuzhiyun}; 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun&rng { 193*4882a593Smuzhiyun status = "okay"; 194*4882a593Smuzhiyun}; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun&sfc { 197*4882a593Smuzhiyun /delete-property/ pinctrl-names; 198*4882a593Smuzhiyun /delete-property/ pinctrl-0; 199*4882a593Smuzhiyun status = "disabled"; 200*4882a593Smuzhiyun}; 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun&u2phy0 { 203*4882a593Smuzhiyun status = "okay"; 204*4882a593Smuzhiyun u2phy_otg: otg-port { 205*4882a593Smuzhiyun status = "okay"; 206*4882a593Smuzhiyun }; 207*4882a593Smuzhiyun}; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun&usbdrd { 210*4882a593Smuzhiyun status = "okay"; 211*4882a593Smuzhiyun}; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun&usbdrd_dwc3 { 214*4882a593Smuzhiyun status = "okay"; 215*4882a593Smuzhiyun extcon = <&u2phy0>; 216*4882a593Smuzhiyun}; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun&vdpu { 219*4882a593Smuzhiyun status = "okay"; 220*4882a593Smuzhiyun}; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun&vepu { 223*4882a593Smuzhiyun status = "okay"; 224*4882a593Smuzhiyun}; 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun&vpu_mmu { 227*4882a593Smuzhiyun status = "okay"; 228*4882a593Smuzhiyun}; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun&vop { 231*4882a593Smuzhiyun status = "okay"; 232*4882a593Smuzhiyun}; 233