1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h> 7*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun adc-keys { 11*4882a593Smuzhiyun compatible = "adc-keys"; 12*4882a593Smuzhiyun io-channels = <&saradc 0>; 13*4882a593Smuzhiyun io-channel-names = "buttons"; 14*4882a593Smuzhiyun poll-interval = <100>; 15*4882a593Smuzhiyun keyup-threshold-microvolt = <1800000>; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun esc-key { 18*4882a593Smuzhiyun label = "esc"; 19*4882a593Smuzhiyun linux,code = <KEY_ESC>; 20*4882a593Smuzhiyun press-threshold-microvolt = <0>; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun right-key { 24*4882a593Smuzhiyun label = "right"; 25*4882a593Smuzhiyun linux,code = <KEY_RIGHT>; 26*4882a593Smuzhiyun press-threshold-microvolt = <400781>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun left-key { 30*4882a593Smuzhiyun label = "left"; 31*4882a593Smuzhiyun linux,code = <KEY_LEFT>; 32*4882a593Smuzhiyun press-threshold-microvolt = <801562>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun menu-key { 36*4882a593Smuzhiyun label = "menu"; 37*4882a593Smuzhiyun linux,code = <KEY_MENU>; 38*4882a593Smuzhiyun press-threshold-microvolt = <1198828>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun backlight: backlight { 43*4882a593Smuzhiyun compatible = "pwm-backlight"; 44*4882a593Smuzhiyun pwms = <&pwm3 0 25000 0>; 45*4882a593Smuzhiyun brightness-levels = < 46*4882a593Smuzhiyun 0 1 2 3 4 5 6 7 47*4882a593Smuzhiyun 8 9 10 11 12 13 14 15 48*4882a593Smuzhiyun 16 17 18 19 20 21 22 23 49*4882a593Smuzhiyun 24 25 26 27 28 29 30 31 50*4882a593Smuzhiyun 32 33 34 35 36 37 38 39 51*4882a593Smuzhiyun 40 41 42 43 44 45 46 47 52*4882a593Smuzhiyun 48 49 50 51 52 53 54 55 53*4882a593Smuzhiyun 56 57 58 59 60 61 62 63 54*4882a593Smuzhiyun 64 65 66 67 68 69 70 71 55*4882a593Smuzhiyun 72 73 74 75 76 77 78 79 56*4882a593Smuzhiyun 80 81 82 83 84 85 86 87 57*4882a593Smuzhiyun 88 89 90 91 92 93 94 95 58*4882a593Smuzhiyun 96 97 98 99 100 101 102 103 59*4882a593Smuzhiyun 104 105 106 107 108 109 110 111 60*4882a593Smuzhiyun 112 113 114 115 116 117 118 119 61*4882a593Smuzhiyun 120 121 122 123 124 125 126 127 62*4882a593Smuzhiyun 128 129 130 131 132 133 134 135 63*4882a593Smuzhiyun 136 137 138 139 140 141 142 143 64*4882a593Smuzhiyun 144 145 146 147 148 149 150 151 65*4882a593Smuzhiyun 152 153 154 155 156 157 158 159 66*4882a593Smuzhiyun 160 161 162 163 164 165 166 167 67*4882a593Smuzhiyun 168 169 170 171 172 173 174 175 68*4882a593Smuzhiyun 176 177 178 179 180 181 182 183 69*4882a593Smuzhiyun 184 185 186 187 188 189 190 191 70*4882a593Smuzhiyun 192 193 194 195 196 197 198 199 71*4882a593Smuzhiyun 200 201 202 203 204 205 206 207 72*4882a593Smuzhiyun 208 209 210 211 212 213 214 215 73*4882a593Smuzhiyun 216 217 218 219 220 221 222 223 74*4882a593Smuzhiyun 224 225 226 227 228 229 230 231 75*4882a593Smuzhiyun 232 233 234 235 236 237 238 239 76*4882a593Smuzhiyun 240 241 242 243 244 245 246 247 77*4882a593Smuzhiyun 248 249 250 251 252 253 254 255>; 78*4882a593Smuzhiyun default-brightness-level = <200>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun cam_ircut0: cam_ircut { 82*4882a593Smuzhiyun status = "okay"; 83*4882a593Smuzhiyun compatible = "rockchip,ircut"; 84*4882a593Smuzhiyun ircut-open-gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_HIGH>; 85*4882a593Smuzhiyun ircut-close-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; 86*4882a593Smuzhiyun rockchip,camera-module-index = <1>; 87*4882a593Smuzhiyun rockchip,camera-module-facing = "front"; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun dummy_codec: dummy-codec { 91*4882a593Smuzhiyun compatible = "rockchip,dummy-codec"; 92*4882a593Smuzhiyun #sound-dai-cells = <0>; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun pdm_mic_array: pdm-mic_array { 96*4882a593Smuzhiyun status = "disabled"; 97*4882a593Smuzhiyun compatible = "simple-audio-card"; 98*4882a593Smuzhiyun simple-audio-card,name = "rockchip,pdm-mic-array"; 99*4882a593Smuzhiyun simple-audio-card,cpu { 100*4882a593Smuzhiyun sound-dai = <&pdm>; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun simple-audio-card,codec { 103*4882a593Smuzhiyun sound-dai = <&dummy_codec>; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun rk809_sound: rk809-sound { 108*4882a593Smuzhiyun compatible = "simple-audio-card"; 109*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 110*4882a593Smuzhiyun simple-audio-card,name = "rockchip,rk809-codec"; 111*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 112*4882a593Smuzhiyun simple-audio-card,cpu { 113*4882a593Smuzhiyun sound-dai = <&i2s0_8ch>; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun simple-audio-card,codec { 116*4882a593Smuzhiyun sound-dai = <&rk809_codec>; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun sdio_pwrseq: sdio-pwrseq { 121*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 122*4882a593Smuzhiyun pinctrl-names = "default"; 123*4882a593Smuzhiyun pinctrl-0 = <&wifi_enable_h>; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun /* 126*4882a593Smuzhiyun * On the module itself this is one of these (depending 127*4882a593Smuzhiyun * on the actual card populated): 128*4882a593Smuzhiyun * - SDIO_RESET_L_WL_REG_ON 129*4882a593Smuzhiyun * - PDN (power down when low) 130*4882a593Smuzhiyun */ 131*4882a593Smuzhiyun reset-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun vcc18_lcd_n: vcc18-lcd-n { 135*4882a593Smuzhiyun compatible = "regulator-fixed"; 136*4882a593Smuzhiyun regulator-name = "vcc18_lcd_n"; 137*4882a593Smuzhiyun gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; 138*4882a593Smuzhiyun enable-active-high; 139*4882a593Smuzhiyun regulator-boot-on; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun vcc5v0_sys: vccsys { 143*4882a593Smuzhiyun compatible = "regulator-fixed"; 144*4882a593Smuzhiyun regulator-name = "vcc5v0_sys"; 145*4882a593Smuzhiyun regulator-always-on; 146*4882a593Smuzhiyun regulator-boot-on; 147*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 148*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun vdd_npu: vdd-npu { 152*4882a593Smuzhiyun compatible = "pwm-regulator"; 153*4882a593Smuzhiyun pwms = <&pwm0 0 5000 1>; 154*4882a593Smuzhiyun regulator-name = "vdd_npu"; 155*4882a593Smuzhiyun regulator-min-microvolt = <650000>; 156*4882a593Smuzhiyun regulator-max-microvolt = <950000>; 157*4882a593Smuzhiyun regulator-init-microvolt = <800000>; 158*4882a593Smuzhiyun regulator-always-on; 159*4882a593Smuzhiyun regulator-boot-on; 160*4882a593Smuzhiyun regulator-settling-time-up-us = <250>; 161*4882a593Smuzhiyun pwm-supply = <&vcc5v0_sys>; 162*4882a593Smuzhiyun status = "okay"; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun vdd_vepu: vdd-vepu { 166*4882a593Smuzhiyun compatible = "pwm-regulator"; 167*4882a593Smuzhiyun pwms = <&pwm1 0 5000 1>; 168*4882a593Smuzhiyun regulator-name = "vdd_vepu"; 169*4882a593Smuzhiyun regulator-min-microvolt = <650000>; 170*4882a593Smuzhiyun regulator-max-microvolt = <950000>; 171*4882a593Smuzhiyun regulator-init-microvolt = <800000>; 172*4882a593Smuzhiyun regulator-always-on; 173*4882a593Smuzhiyun regulator-boot-on; 174*4882a593Smuzhiyun regulator-settling-time-up-us = <250>; 175*4882a593Smuzhiyun pwm-supply = <&vcc5v0_sys>; 176*4882a593Smuzhiyun status = "okay"; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun wireless-bluetooth { 180*4882a593Smuzhiyun compatible = "bluetooth-platdata"; 181*4882a593Smuzhiyun uart_rts_gpios = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>; 182*4882a593Smuzhiyun pinctrl-names = "default", "rts_gpio"; 183*4882a593Smuzhiyun pinctrl-0 = <&uart0_rtsn>; 184*4882a593Smuzhiyun pinctrl-1 = <&uart0_rtsn_gpio>; 185*4882a593Smuzhiyun BT,power_gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>; 186*4882a593Smuzhiyun BT,wake_host_irq = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; 187*4882a593Smuzhiyun status = "okay"; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun wireless_wlan: wireless-wlan { 191*4882a593Smuzhiyun compatible = "wlan-platdata"; 192*4882a593Smuzhiyun rockchip,grf = <&grf>; 193*4882a593Smuzhiyun clocks = <&rk809 1>; 194*4882a593Smuzhiyun clock-names = "clk_wifi"; 195*4882a593Smuzhiyun pinctrl-names = "default"; 196*4882a593Smuzhiyun pinctrl-0 = <&wifi_wake_host>; 197*4882a593Smuzhiyun wifi_chip_type = "ap6255"; 198*4882a593Smuzhiyun /* WIFI,poweren_gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; */ 199*4882a593Smuzhiyun WIFI,host_wake_irq = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; 200*4882a593Smuzhiyun status = "okay"; 201*4882a593Smuzhiyun }; 202*4882a593Smuzhiyun}; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun&cpu0 { 205*4882a593Smuzhiyun cpu-supply = <&vdd_arm>; 206*4882a593Smuzhiyun}; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun&cpu_tsadc { 209*4882a593Smuzhiyun status = "okay"; 210*4882a593Smuzhiyun}; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun&display_subsystem { 213*4882a593Smuzhiyun status = "okay"; 214*4882a593Smuzhiyun}; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun&dsi { 217*4882a593Smuzhiyun status = "okay"; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun rockchip,lane-rate = <480>; 220*4882a593Smuzhiyun panel@0 { 221*4882a593Smuzhiyun compatible = "ilitek,ili9881d", "simple-panel-dsi"; 222*4882a593Smuzhiyun reg = <0>; 223*4882a593Smuzhiyun backlight = <&backlight>; 224*4882a593Smuzhiyun power-supply = <&vcc18_lcd_n>; 225*4882a593Smuzhiyun prepare-delay-ms = <5>; 226*4882a593Smuzhiyun reset-delay-ms = <1>; 227*4882a593Smuzhiyun init-delay-ms = <80>; 228*4882a593Smuzhiyun disable-delay-ms = <10>; 229*4882a593Smuzhiyun unprepare-delay-ms = <5>; 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun width-mm = <68>; 232*4882a593Smuzhiyun height-mm = <121>; 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 235*4882a593Smuzhiyun MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; 236*4882a593Smuzhiyun dsi,format = <MIPI_DSI_FMT_RGB888>; 237*4882a593Smuzhiyun dsi,lanes = <4>; 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun panel-init-sequence = [ 240*4882a593Smuzhiyun 39 00 04 ff 98 81 03 241*4882a593Smuzhiyun 15 00 02 01 00 242*4882a593Smuzhiyun 15 00 02 02 00 243*4882a593Smuzhiyun 15 00 02 03 53 244*4882a593Smuzhiyun 15 00 02 04 53 245*4882a593Smuzhiyun 15 00 02 05 13 246*4882a593Smuzhiyun 15 00 02 06 04 247*4882a593Smuzhiyun 15 00 02 07 02 248*4882a593Smuzhiyun 15 00 02 08 02 249*4882a593Smuzhiyun 15 00 02 09 00 250*4882a593Smuzhiyun 15 00 02 0a 00 251*4882a593Smuzhiyun 15 00 02 0b 00 252*4882a593Smuzhiyun 15 00 02 0c 00 253*4882a593Smuzhiyun 15 00 02 0d 00 254*4882a593Smuzhiyun 15 00 02 0e 00 255*4882a593Smuzhiyun 15 00 02 0f 00 256*4882a593Smuzhiyun 15 00 02 10 00 257*4882a593Smuzhiyun 15 00 02 11 00 258*4882a593Smuzhiyun 15 00 02 12 00 259*4882a593Smuzhiyun 15 00 02 13 00 260*4882a593Smuzhiyun 15 00 02 14 00 261*4882a593Smuzhiyun 15 00 02 15 08 262*4882a593Smuzhiyun 15 00 02 16 10 263*4882a593Smuzhiyun 15 00 02 17 00 264*4882a593Smuzhiyun 15 00 02 18 08 265*4882a593Smuzhiyun 15 00 02 19 00 266*4882a593Smuzhiyun 15 00 02 1a 00 267*4882a593Smuzhiyun 15 00 02 1b 00 268*4882a593Smuzhiyun 15 00 02 1c 00 269*4882a593Smuzhiyun 15 00 02 1d 00 270*4882a593Smuzhiyun 15 00 02 1e c0 271*4882a593Smuzhiyun 15 00 02 1f 80 272*4882a593Smuzhiyun 15 00 02 20 02 273*4882a593Smuzhiyun 15 00 02 21 09 274*4882a593Smuzhiyun 15 00 02 22 00 275*4882a593Smuzhiyun 15 00 02 23 00 276*4882a593Smuzhiyun 15 00 02 24 00 277*4882a593Smuzhiyun 15 00 02 25 00 278*4882a593Smuzhiyun 15 00 02 26 00 279*4882a593Smuzhiyun 15 00 02 27 00 280*4882a593Smuzhiyun 15 00 02 28 55 281*4882a593Smuzhiyun 15 00 02 29 03 282*4882a593Smuzhiyun 15 00 02 2a 00 283*4882a593Smuzhiyun 15 00 02 2b 00 284*4882a593Smuzhiyun 15 00 02 2c 00 285*4882a593Smuzhiyun 15 00 02 2d 00 286*4882a593Smuzhiyun 15 00 02 2e 00 287*4882a593Smuzhiyun 15 00 02 2f 00 288*4882a593Smuzhiyun 15 00 02 30 00 289*4882a593Smuzhiyun 15 00 02 31 00 290*4882a593Smuzhiyun 15 00 02 32 00 291*4882a593Smuzhiyun 15 00 02 33 00 292*4882a593Smuzhiyun 15 00 02 34 04 293*4882a593Smuzhiyun 15 00 02 35 05 294*4882a593Smuzhiyun 15 00 02 36 05 295*4882a593Smuzhiyun 15 00 02 37 00 296*4882a593Smuzhiyun 15 00 02 38 3c 297*4882a593Smuzhiyun 15 00 02 39 35 298*4882a593Smuzhiyun 15 00 02 3a 00 299*4882a593Smuzhiyun 15 00 02 3b 40 300*4882a593Smuzhiyun 15 00 02 3c 00 301*4882a593Smuzhiyun 15 00 02 3d 00 302*4882a593Smuzhiyun 15 00 02 3e 00 303*4882a593Smuzhiyun 15 00 02 3f 00 304*4882a593Smuzhiyun 15 00 02 40 00 305*4882a593Smuzhiyun 15 00 02 41 88 306*4882a593Smuzhiyun 15 00 02 42 00 307*4882a593Smuzhiyun 15 00 02 43 00 308*4882a593Smuzhiyun 15 00 02 44 1f 309*4882a593Smuzhiyun 15 00 02 50 01 310*4882a593Smuzhiyun 15 00 02 51 23 311*4882a593Smuzhiyun 15 00 02 52 45 312*4882a593Smuzhiyun 15 00 02 53 67 313*4882a593Smuzhiyun 15 00 02 54 89 314*4882a593Smuzhiyun 15 00 02 55 ab 315*4882a593Smuzhiyun 15 00 02 56 01 316*4882a593Smuzhiyun 15 00 02 57 23 317*4882a593Smuzhiyun 15 00 02 58 45 318*4882a593Smuzhiyun 15 00 02 59 67 319*4882a593Smuzhiyun 15 00 02 5a 89 320*4882a593Smuzhiyun 15 00 02 5b ab 321*4882a593Smuzhiyun 15 00 02 5c cd 322*4882a593Smuzhiyun 15 00 02 5d ef 323*4882a593Smuzhiyun 15 00 02 5e 03 324*4882a593Smuzhiyun 15 00 02 5f 14 325*4882a593Smuzhiyun 15 00 02 60 15 326*4882a593Smuzhiyun 15 00 02 61 0c 327*4882a593Smuzhiyun 15 00 02 62 0d 328*4882a593Smuzhiyun 15 00 02 63 0e 329*4882a593Smuzhiyun 15 00 02 64 0f 330*4882a593Smuzhiyun 15 00 02 65 10 331*4882a593Smuzhiyun 15 00 02 66 11 332*4882a593Smuzhiyun 15 00 02 67 08 333*4882a593Smuzhiyun 15 00 02 68 02 334*4882a593Smuzhiyun 15 00 02 69 0a 335*4882a593Smuzhiyun 15 00 02 6a 02 336*4882a593Smuzhiyun 15 00 02 6b 02 337*4882a593Smuzhiyun 15 00 02 6c 02 338*4882a593Smuzhiyun 15 00 02 6d 02 339*4882a593Smuzhiyun 15 00 02 6e 02 340*4882a593Smuzhiyun 15 00 02 6f 02 341*4882a593Smuzhiyun 15 00 02 70 02 342*4882a593Smuzhiyun 15 00 02 71 02 343*4882a593Smuzhiyun 15 00 02 72 06 344*4882a593Smuzhiyun 15 00 02 73 02 345*4882a593Smuzhiyun 15 00 02 74 02 346*4882a593Smuzhiyun 15 00 02 75 14 347*4882a593Smuzhiyun 15 00 02 76 15 348*4882a593Smuzhiyun 15 00 02 77 0f 349*4882a593Smuzhiyun 15 00 02 78 0e 350*4882a593Smuzhiyun 15 00 02 79 0d 351*4882a593Smuzhiyun 15 00 02 7a 0c 352*4882a593Smuzhiyun 15 00 02 7b 11 353*4882a593Smuzhiyun 15 00 02 7c 10 354*4882a593Smuzhiyun 15 00 02 7d 06 355*4882a593Smuzhiyun 15 00 02 7e 02 356*4882a593Smuzhiyun 15 00 02 7f 0a 357*4882a593Smuzhiyun 15 00 02 80 02 358*4882a593Smuzhiyun 15 00 02 81 02 359*4882a593Smuzhiyun 15 00 02 82 02 360*4882a593Smuzhiyun 15 00 02 83 02 361*4882a593Smuzhiyun 15 00 02 84 02 362*4882a593Smuzhiyun 15 00 02 85 02 363*4882a593Smuzhiyun 15 00 02 86 02 364*4882a593Smuzhiyun 15 00 02 87 02 365*4882a593Smuzhiyun 15 00 02 88 08 366*4882a593Smuzhiyun 15 00 02 89 02 367*4882a593Smuzhiyun 15 00 02 8a 02 368*4882a593Smuzhiyun 39 00 04 ff 98 81 04 369*4882a593Smuzhiyun 15 00 02 00 80 370*4882a593Smuzhiyun 15 00 02 70 00 371*4882a593Smuzhiyun 15 00 02 71 00 372*4882a593Smuzhiyun 15 00 02 66 fe 373*4882a593Smuzhiyun 15 00 02 82 15 374*4882a593Smuzhiyun 15 00 02 84 15 375*4882a593Smuzhiyun 15 00 02 85 15 376*4882a593Smuzhiyun 15 00 02 3a 24 377*4882a593Smuzhiyun 15 00 02 32 ac 378*4882a593Smuzhiyun 15 00 02 8c 80 379*4882a593Smuzhiyun 15 00 02 3c f5 380*4882a593Smuzhiyun 15 00 02 88 33 381*4882a593Smuzhiyun 39 00 04 ff 98 81 01 382*4882a593Smuzhiyun 15 00 02 22 0a 383*4882a593Smuzhiyun 15 00 02 31 00 384*4882a593Smuzhiyun 15 00 02 53 78 385*4882a593Smuzhiyun 15 00 02 55 7b 386*4882a593Smuzhiyun 15 00 02 60 20 387*4882a593Smuzhiyun 15 00 02 61 00 388*4882a593Smuzhiyun 15 00 02 62 0d 389*4882a593Smuzhiyun 15 00 02 63 00 390*4882a593Smuzhiyun 15 00 02 a0 00 391*4882a593Smuzhiyun 15 00 02 a1 10 392*4882a593Smuzhiyun 15 00 02 a2 1c 393*4882a593Smuzhiyun 15 00 02 a3 13 394*4882a593Smuzhiyun 15 00 02 a4 15 395*4882a593Smuzhiyun 15 00 02 a5 26 396*4882a593Smuzhiyun 15 00 02 a6 1a 397*4882a593Smuzhiyun 15 00 02 a7 1d 398*4882a593Smuzhiyun 15 00 02 a8 67 399*4882a593Smuzhiyun 15 00 02 a9 1c 400*4882a593Smuzhiyun 15 00 02 aa 29 401*4882a593Smuzhiyun 15 00 02 ab 5b 402*4882a593Smuzhiyun 15 00 02 ac 26 403*4882a593Smuzhiyun 15 00 02 ad 28 404*4882a593Smuzhiyun 15 00 02 ae 5c 405*4882a593Smuzhiyun 15 00 02 af 30 406*4882a593Smuzhiyun 15 00 02 b0 31 407*4882a593Smuzhiyun 15 00 02 b1 32 408*4882a593Smuzhiyun 15 00 02 b2 00 409*4882a593Smuzhiyun 15 00 02 b1 2e 410*4882a593Smuzhiyun 15 00 02 b2 32 411*4882a593Smuzhiyun 15 00 02 b3 00 412*4882a593Smuzhiyun 15 00 02 c0 00 413*4882a593Smuzhiyun 15 00 02 c1 10 414*4882a593Smuzhiyun 15 00 02 c2 1c 415*4882a593Smuzhiyun 15 00 02 c3 13 416*4882a593Smuzhiyun 15 00 02 c4 15 417*4882a593Smuzhiyun 15 00 02 c5 26 418*4882a593Smuzhiyun 15 00 02 c6 1a 419*4882a593Smuzhiyun 15 00 02 c7 1d 420*4882a593Smuzhiyun 15 00 02 c8 67 421*4882a593Smuzhiyun 15 00 02 c9 1c 422*4882a593Smuzhiyun 15 00 02 ca 29 423*4882a593Smuzhiyun 15 00 02 cb 5b 424*4882a593Smuzhiyun 15 00 02 cc 26 425*4882a593Smuzhiyun 15 00 02 cd 28 426*4882a593Smuzhiyun 15 00 02 ce 5c 427*4882a593Smuzhiyun 15 00 02 cf 30 428*4882a593Smuzhiyun 15 00 02 d0 31 429*4882a593Smuzhiyun 15 00 02 d1 2e 430*4882a593Smuzhiyun 15 00 02 d2 32 431*4882a593Smuzhiyun 15 00 02 d3 00 432*4882a593Smuzhiyun 39 00 04 ff 98 81 00 433*4882a593Smuzhiyun 05 00 01 11 434*4882a593Smuzhiyun 05 01 01 29 435*4882a593Smuzhiyun ]; 436*4882a593Smuzhiyun 437*4882a593Smuzhiyun display-timings { 438*4882a593Smuzhiyun native-mode = <&timing0>; 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun timing0: timing0 { 441*4882a593Smuzhiyun clock-frequency = <65000000>; 442*4882a593Smuzhiyun hactive = <720>; 443*4882a593Smuzhiyun vactive = <1280>; 444*4882a593Smuzhiyun hfront-porch = <48>; 445*4882a593Smuzhiyun hsync-len = <8>; 446*4882a593Smuzhiyun hback-porch = <52>; 447*4882a593Smuzhiyun vfront-porch = <16>; 448*4882a593Smuzhiyun vsync-len = <6>; 449*4882a593Smuzhiyun vback-porch = <15>; 450*4882a593Smuzhiyun hsync-active = <0>; 451*4882a593Smuzhiyun vsync-active = <0>; 452*4882a593Smuzhiyun de-active = <0>; 453*4882a593Smuzhiyun pixelclk-active = <0>; 454*4882a593Smuzhiyun }; 455*4882a593Smuzhiyun }; 456*4882a593Smuzhiyun 457*4882a593Smuzhiyun ports { 458*4882a593Smuzhiyun #address-cells = <1>; 459*4882a593Smuzhiyun #size-cells = <0>; 460*4882a593Smuzhiyun 461*4882a593Smuzhiyun port@0 { 462*4882a593Smuzhiyun reg = <0>; 463*4882a593Smuzhiyun panel_in_dsi: endpoint { 464*4882a593Smuzhiyun remote-endpoint = <&dsi_out_panel>; 465*4882a593Smuzhiyun }; 466*4882a593Smuzhiyun }; 467*4882a593Smuzhiyun }; 468*4882a593Smuzhiyun }; 469*4882a593Smuzhiyun 470*4882a593Smuzhiyun ports { 471*4882a593Smuzhiyun #address-cells = <1>; 472*4882a593Smuzhiyun #size-cells = <0>; 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun port@1 { 475*4882a593Smuzhiyun reg = <1>; 476*4882a593Smuzhiyun dsi_out_panel: endpoint { 477*4882a593Smuzhiyun remote-endpoint = <&panel_in_dsi>; 478*4882a593Smuzhiyun }; 479*4882a593Smuzhiyun }; 480*4882a593Smuzhiyun }; 481*4882a593Smuzhiyun}; 482*4882a593Smuzhiyun 483*4882a593Smuzhiyun&csi_dphy0 { 484*4882a593Smuzhiyun status = "okay"; 485*4882a593Smuzhiyun 486*4882a593Smuzhiyun ports { 487*4882a593Smuzhiyun #address-cells = <1>; 488*4882a593Smuzhiyun #size-cells = <0>; 489*4882a593Smuzhiyun port@0 { 490*4882a593Smuzhiyun reg = <0>; 491*4882a593Smuzhiyun #address-cells = <1>; 492*4882a593Smuzhiyun #size-cells = <0>; 493*4882a593Smuzhiyun 494*4882a593Smuzhiyun mipi_in_ucam0: endpoint@1 { 495*4882a593Smuzhiyun reg = <1>; 496*4882a593Smuzhiyun remote-endpoint = <&ucam_out0>; 497*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 498*4882a593Smuzhiyun }; 499*4882a593Smuzhiyun }; 500*4882a593Smuzhiyun port@1 { 501*4882a593Smuzhiyun reg = <1>; 502*4882a593Smuzhiyun #address-cells = <1>; 503*4882a593Smuzhiyun #size-cells = <0>; 504*4882a593Smuzhiyun 505*4882a593Smuzhiyun csidphy0_out: endpoint@0 { 506*4882a593Smuzhiyun reg = <0>; 507*4882a593Smuzhiyun remote-endpoint = <&mipi_csi2_input>; 508*4882a593Smuzhiyun }; 509*4882a593Smuzhiyun }; 510*4882a593Smuzhiyun }; 511*4882a593Smuzhiyun}; 512*4882a593Smuzhiyun 513*4882a593Smuzhiyun&csi_dphy1 { 514*4882a593Smuzhiyun status = "okay"; 515*4882a593Smuzhiyun 516*4882a593Smuzhiyun ports { 517*4882a593Smuzhiyun #address-cells = <1>; 518*4882a593Smuzhiyun #size-cells = <0>; 519*4882a593Smuzhiyun 520*4882a593Smuzhiyun port@0 { 521*4882a593Smuzhiyun reg = <0>; 522*4882a593Smuzhiyun #address-cells = <1>; 523*4882a593Smuzhiyun #size-cells = <0>; 524*4882a593Smuzhiyun 525*4882a593Smuzhiyun csi_dphy1_input: endpoint@1 { 526*4882a593Smuzhiyun reg = <1>; 527*4882a593Smuzhiyun remote-endpoint = <&ucam_out1>; 528*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 529*4882a593Smuzhiyun }; 530*4882a593Smuzhiyun }; 531*4882a593Smuzhiyun 532*4882a593Smuzhiyun port@1 { 533*4882a593Smuzhiyun reg = <1>; 534*4882a593Smuzhiyun #address-cells = <1>; 535*4882a593Smuzhiyun #size-cells = <0>; 536*4882a593Smuzhiyun 537*4882a593Smuzhiyun csi_dphy1_output: endpoint@0 { 538*4882a593Smuzhiyun reg = <0>; 539*4882a593Smuzhiyun /*remote-endpoint = <&mipi_csi2_input>;*/ 540*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 541*4882a593Smuzhiyun }; 542*4882a593Smuzhiyun }; 543*4882a593Smuzhiyun }; 544*4882a593Smuzhiyun}; 545*4882a593Smuzhiyun 546*4882a593Smuzhiyun&emmc { 547*4882a593Smuzhiyun bus-width = <8>; 548*4882a593Smuzhiyun cap-mmc-highspeed; 549*4882a593Smuzhiyun non-removable; 550*4882a593Smuzhiyun mmc-hs200-1_8v; 551*4882a593Smuzhiyun rockchip,default-sample-phase = <90>; 552*4882a593Smuzhiyun no-sdio; 553*4882a593Smuzhiyun no-sd; 554*4882a593Smuzhiyun /delete-property/ pinctrl-names; 555*4882a593Smuzhiyun /delete-property/ pinctrl-0; 556*4882a593Smuzhiyun status = "okay"; 557*4882a593Smuzhiyun}; 558*4882a593Smuzhiyun 559*4882a593Smuzhiyun&fiq_debugger { 560*4882a593Smuzhiyun status = "okay"; 561*4882a593Smuzhiyun}; 562*4882a593Smuzhiyun 563*4882a593Smuzhiyun&gmac { 564*4882a593Smuzhiyun phy-mode = "rgmii"; 565*4882a593Smuzhiyun clock_in_out = "input"; 566*4882a593Smuzhiyun 567*4882a593Smuzhiyun snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>; 568*4882a593Smuzhiyun snps,reset-active-low; 569*4882a593Smuzhiyun /* Reset time is 20ms, 100ms for rtl8211f */ 570*4882a593Smuzhiyun snps,reset-delays-us = <0 20000 100000>; 571*4882a593Smuzhiyun 572*4882a593Smuzhiyun assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_ETHERNET_OUT>; 573*4882a593Smuzhiyun assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>; 574*4882a593Smuzhiyun assigned-clock-rates = <125000000>, <0>, <25000000>; 575*4882a593Smuzhiyun 576*4882a593Smuzhiyun pinctrl-names = "default"; 577*4882a593Smuzhiyun pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4 &clkm1_out_ethernet>; 578*4882a593Smuzhiyun 579*4882a593Smuzhiyun tx_delay = <0x2a>; 580*4882a593Smuzhiyun rx_delay = <0x1a>; 581*4882a593Smuzhiyun 582*4882a593Smuzhiyun phy-handle = <&phy>; 583*4882a593Smuzhiyun status = "okay"; 584*4882a593Smuzhiyun}; 585*4882a593Smuzhiyun 586*4882a593Smuzhiyun&i2c0 { 587*4882a593Smuzhiyun status = "okay"; 588*4882a593Smuzhiyun clock-frequency = <400000>; 589*4882a593Smuzhiyun 590*4882a593Smuzhiyun rk809: pmic@20 { 591*4882a593Smuzhiyun compatible = "rockchip,rk809"; 592*4882a593Smuzhiyun reg = <0x20>; 593*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 594*4882a593Smuzhiyun interrupts = <9 IRQ_TYPE_LEVEL_LOW>; 595*4882a593Smuzhiyun pinctrl-names = "default", "pmic-sleep", 596*4882a593Smuzhiyun "pmic-power-off", "pmic-reset"; 597*4882a593Smuzhiyun pinctrl-0 = <&pmic_int>; 598*4882a593Smuzhiyun pinctrl-1 = <&soc_slppin_gpio>, <&rk817_slppin_slp>; 599*4882a593Smuzhiyun pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; 600*4882a593Smuzhiyun pinctrl-3 = <&soc_slppin_slp>, <&rk817_slppin_rst>; 601*4882a593Smuzhiyun rockchip,system-power-controller; 602*4882a593Smuzhiyun wakeup-source; 603*4882a593Smuzhiyun #clock-cells = <1>; 604*4882a593Smuzhiyun clock-output-names = "rk808-clkout1", "rk808-clkout2"; 605*4882a593Smuzhiyun /* 0: rst the pmic, 1: rst regs (default in codes) */ 606*4882a593Smuzhiyun pmic-reset-func = <0>; 607*4882a593Smuzhiyun 608*4882a593Smuzhiyun vcc1-supply = <&vcc5v0_sys>; 609*4882a593Smuzhiyun vcc2-supply = <&vcc5v0_sys>; 610*4882a593Smuzhiyun vcc3-supply = <&vcc5v0_sys>; 611*4882a593Smuzhiyun vcc4-supply = <&vcc5v0_sys>; 612*4882a593Smuzhiyun vcc5-supply = <&vcc_buck5>; 613*4882a593Smuzhiyun vcc6-supply = <&vcc_buck5>; 614*4882a593Smuzhiyun vcc7-supply = <&vcc5v0_sys>; 615*4882a593Smuzhiyun vcc8-supply = <&vcc3v3_sys>; 616*4882a593Smuzhiyun vcc9-supply = <&vcc5v0_sys>; 617*4882a593Smuzhiyun 618*4882a593Smuzhiyun pwrkey { 619*4882a593Smuzhiyun status = "okay"; 620*4882a593Smuzhiyun }; 621*4882a593Smuzhiyun 622*4882a593Smuzhiyun pinctrl_rk8xx: pinctrl_rk8xx { 623*4882a593Smuzhiyun gpio-controller; 624*4882a593Smuzhiyun #gpio-cells = <2>; 625*4882a593Smuzhiyun 626*4882a593Smuzhiyun /omit-if-no-ref/ 627*4882a593Smuzhiyun rk817_slppin_null: rk817_slppin_null { 628*4882a593Smuzhiyun pins = "gpio_slp"; 629*4882a593Smuzhiyun function = "pin_fun0"; 630*4882a593Smuzhiyun }; 631*4882a593Smuzhiyun 632*4882a593Smuzhiyun /omit-if-no-ref/ 633*4882a593Smuzhiyun rk817_slppin_slp: rk817_slppin_slp { 634*4882a593Smuzhiyun pins = "gpio_slp"; 635*4882a593Smuzhiyun function = "pin_fun1"; 636*4882a593Smuzhiyun }; 637*4882a593Smuzhiyun 638*4882a593Smuzhiyun /omit-if-no-ref/ 639*4882a593Smuzhiyun rk817_slppin_pwrdn: rk817_slppin_pwrdn { 640*4882a593Smuzhiyun pins = "gpio_slp"; 641*4882a593Smuzhiyun function = "pin_fun2"; 642*4882a593Smuzhiyun }; 643*4882a593Smuzhiyun 644*4882a593Smuzhiyun /omit-if-no-ref/ 645*4882a593Smuzhiyun rk817_slppin_rst: rk817_slppin_rst { 646*4882a593Smuzhiyun pins = "gpio_slp"; 647*4882a593Smuzhiyun function = "pin_fun3"; 648*4882a593Smuzhiyun }; 649*4882a593Smuzhiyun }; 650*4882a593Smuzhiyun 651*4882a593Smuzhiyun regulators { 652*4882a593Smuzhiyun vdd_logic: DCDC_REG1 { 653*4882a593Smuzhiyun regulator-always-on; 654*4882a593Smuzhiyun regulator-boot-on; 655*4882a593Smuzhiyun regulator-min-microvolt = <725000>; 656*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 657*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 658*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 659*4882a593Smuzhiyun regulator-name = "vdd_logic"; 660*4882a593Smuzhiyun regulator-state-mem { 661*4882a593Smuzhiyun regulator-on-in-suspend; 662*4882a593Smuzhiyun regulator-suspend-microvolt = <800000>; 663*4882a593Smuzhiyun }; 664*4882a593Smuzhiyun }; 665*4882a593Smuzhiyun 666*4882a593Smuzhiyun vdd_arm: DCDC_REG2 { 667*4882a593Smuzhiyun regulator-always-on; 668*4882a593Smuzhiyun regulator-boot-on; 669*4882a593Smuzhiyun regulator-min-microvolt = <725000>; 670*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 671*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 672*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 673*4882a593Smuzhiyun regulator-name = "vdd_arm"; 674*4882a593Smuzhiyun regulator-state-mem { 675*4882a593Smuzhiyun regulator-off-in-suspend; 676*4882a593Smuzhiyun }; 677*4882a593Smuzhiyun }; 678*4882a593Smuzhiyun 679*4882a593Smuzhiyun vcc_ddr: DCDC_REG3 { 680*4882a593Smuzhiyun regulator-always-on; 681*4882a593Smuzhiyun regulator-boot-on; 682*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 683*4882a593Smuzhiyun regulator-name = "vcc_ddr"; 684*4882a593Smuzhiyun regulator-state-mem { 685*4882a593Smuzhiyun regulator-on-in-suspend; 686*4882a593Smuzhiyun }; 687*4882a593Smuzhiyun }; 688*4882a593Smuzhiyun 689*4882a593Smuzhiyun vcc3v3_sys: DCDC_REG4 { 690*4882a593Smuzhiyun regulator-always-on; 691*4882a593Smuzhiyun regulator-boot-on; 692*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 693*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 694*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 695*4882a593Smuzhiyun regulator-name = "vcc3v3_sys"; 696*4882a593Smuzhiyun regulator-state-mem { 697*4882a593Smuzhiyun regulator-on-in-suspend; 698*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 699*4882a593Smuzhiyun }; 700*4882a593Smuzhiyun }; 701*4882a593Smuzhiyun 702*4882a593Smuzhiyun vcc_buck5: DCDC_REG5 { 703*4882a593Smuzhiyun regulator-always-on; 704*4882a593Smuzhiyun regulator-boot-on; 705*4882a593Smuzhiyun regulator-min-microvolt = <2200000>; 706*4882a593Smuzhiyun regulator-max-microvolt = <2200000>; 707*4882a593Smuzhiyun regulator-name = "vcc_buck5"; 708*4882a593Smuzhiyun regulator-state-mem { 709*4882a593Smuzhiyun regulator-on-in-suspend; 710*4882a593Smuzhiyun regulator-suspend-microvolt = <2200000>; 711*4882a593Smuzhiyun }; 712*4882a593Smuzhiyun }; 713*4882a593Smuzhiyun 714*4882a593Smuzhiyun vcc_0v8: LDO_REG1 { 715*4882a593Smuzhiyun regulator-always-on; 716*4882a593Smuzhiyun regulator-boot-on; 717*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 718*4882a593Smuzhiyun regulator-max-microvolt = <800000>; 719*4882a593Smuzhiyun regulator-name = "vcc_0v8"; 720*4882a593Smuzhiyun regulator-state-mem { 721*4882a593Smuzhiyun regulator-off-in-suspend; 722*4882a593Smuzhiyun }; 723*4882a593Smuzhiyun }; 724*4882a593Smuzhiyun 725*4882a593Smuzhiyun vcc1v8_pmu: LDO_REG2 { 726*4882a593Smuzhiyun regulator-always-on; 727*4882a593Smuzhiyun regulator-boot-on; 728*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 729*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 730*4882a593Smuzhiyun regulator-name = "vcc1v8_pmu"; 731*4882a593Smuzhiyun regulator-state-mem { 732*4882a593Smuzhiyun regulator-on-in-suspend; 733*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 734*4882a593Smuzhiyun }; 735*4882a593Smuzhiyun }; 736*4882a593Smuzhiyun 737*4882a593Smuzhiyun vdd0v8_pmu: LDO_REG3 { 738*4882a593Smuzhiyun regulator-always-on; 739*4882a593Smuzhiyun regulator-boot-on; 740*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 741*4882a593Smuzhiyun regulator-max-microvolt = <800000>; 742*4882a593Smuzhiyun regulator-name = "vcc0v8_pmu"; 743*4882a593Smuzhiyun regulator-state-mem { 744*4882a593Smuzhiyun regulator-on-in-suspend; 745*4882a593Smuzhiyun regulator-suspend-microvolt = <800000>; 746*4882a593Smuzhiyun }; 747*4882a593Smuzhiyun }; 748*4882a593Smuzhiyun 749*4882a593Smuzhiyun vcc_1v8: LDO_REG4 { 750*4882a593Smuzhiyun regulator-always-on; 751*4882a593Smuzhiyun regulator-boot-on; 752*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 753*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 754*4882a593Smuzhiyun regulator-name = "vcc_1v8"; 755*4882a593Smuzhiyun regulator-state-mem { 756*4882a593Smuzhiyun regulator-on-in-suspend; 757*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 758*4882a593Smuzhiyun }; 759*4882a593Smuzhiyun }; 760*4882a593Smuzhiyun 761*4882a593Smuzhiyun vcc_dovdd: LDO_REG5 { 762*4882a593Smuzhiyun regulator-boot-on; 763*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 764*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 765*4882a593Smuzhiyun regulator-name = "vcc_dovdd"; 766*4882a593Smuzhiyun regulator-state-mem { 767*4882a593Smuzhiyun regulator-off-in-suspend; 768*4882a593Smuzhiyun }; 769*4882a593Smuzhiyun }; 770*4882a593Smuzhiyun 771*4882a593Smuzhiyun vcc_dvdd: LDO_REG6 { 772*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 773*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 774*4882a593Smuzhiyun regulator-name = "vcc_dvdd"; 775*4882a593Smuzhiyun regulator-state-mem { 776*4882a593Smuzhiyun regulator-off-in-suspend; 777*4882a593Smuzhiyun }; 778*4882a593Smuzhiyun }; 779*4882a593Smuzhiyun 780*4882a593Smuzhiyun vcc_avdd: LDO_REG7 { 781*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 782*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 783*4882a593Smuzhiyun regulator-name = "vcc_avdd"; 784*4882a593Smuzhiyun regulator-state-mem { 785*4882a593Smuzhiyun regulator-off-in-suspend; 786*4882a593Smuzhiyun }; 787*4882a593Smuzhiyun }; 788*4882a593Smuzhiyun 789*4882a593Smuzhiyun vccio_sd: LDO_REG8 { 790*4882a593Smuzhiyun regulator-always-on; 791*4882a593Smuzhiyun regulator-boot-on; 792*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 793*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 794*4882a593Smuzhiyun regulator-name = "vccio_sd"; 795*4882a593Smuzhiyun regulator-state-mem { 796*4882a593Smuzhiyun regulator-off-in-suspend; 797*4882a593Smuzhiyun }; 798*4882a593Smuzhiyun }; 799*4882a593Smuzhiyun 800*4882a593Smuzhiyun vcc3v3_sd: LDO_REG9 { 801*4882a593Smuzhiyun regulator-always-on; 802*4882a593Smuzhiyun regulator-boot-on; 803*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 804*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 805*4882a593Smuzhiyun regulator-name = "vcc3v3_sd"; 806*4882a593Smuzhiyun regulator-state-mem { 807*4882a593Smuzhiyun regulator-off-in-suspend; 808*4882a593Smuzhiyun }; 809*4882a593Smuzhiyun }; 810*4882a593Smuzhiyun 811*4882a593Smuzhiyun vcc5v0_host: SWITCH_REG1 { 812*4882a593Smuzhiyun regulator-name = "vcc5v0_host"; 813*4882a593Smuzhiyun }; 814*4882a593Smuzhiyun 815*4882a593Smuzhiyun vcc_3v3: SWITCH_REG2 { 816*4882a593Smuzhiyun regulator-always-on; 817*4882a593Smuzhiyun regulator-boot-on; 818*4882a593Smuzhiyun regulator-name = "vcc_3v3"; 819*4882a593Smuzhiyun }; 820*4882a593Smuzhiyun }; 821*4882a593Smuzhiyun 822*4882a593Smuzhiyun rk809_codec: codec { 823*4882a593Smuzhiyun #sound-dai-cells = <0>; 824*4882a593Smuzhiyun compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; 825*4882a593Smuzhiyun clocks = <&cru MCLK_I2S0_TX_OUT2IO>; 826*4882a593Smuzhiyun clock-names = "mclk"; 827*4882a593Smuzhiyun pinctrl-names = "default"; 828*4882a593Smuzhiyun assigned-clocks = <&cru MCLK_I2S0_TX_OUT2IO>; 829*4882a593Smuzhiyun assigned-clock-parents = <&cru MCLK_I2S0_TX>; 830*4882a593Smuzhiyun pinctrl-0 = <&i2s0m0_mclk>; 831*4882a593Smuzhiyun hp-volume = <20>; 832*4882a593Smuzhiyun spk-volume = <3>; 833*4882a593Smuzhiyun }; 834*4882a593Smuzhiyun }; 835*4882a593Smuzhiyun}; 836*4882a593Smuzhiyun 837*4882a593Smuzhiyun&i2c1 { 838*4882a593Smuzhiyun status = "okay"; 839*4882a593Smuzhiyun clock-frequency = <400000>; 840*4882a593Smuzhiyun 841*4882a593Smuzhiyun ar0230: ar0230@10 { 842*4882a593Smuzhiyun compatible = "aptina,ar0230"; 843*4882a593Smuzhiyun reg = <0x10>; 844*4882a593Smuzhiyun clocks = <&cru CLK_CIF_OUT>; 845*4882a593Smuzhiyun clock-names = "xvclk"; 846*4882a593Smuzhiyun avdd-supply = <&vcc_avdd>; 847*4882a593Smuzhiyun dovdd-supply = <&vcc_dovdd>; 848*4882a593Smuzhiyun dvdd-supply = <&vcc_dvdd>; 849*4882a593Smuzhiyun power-domains = <&power RV1126_PD_VI>; 850*4882a593Smuzhiyun pwdn-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; 851*4882a593Smuzhiyun /*reset-gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;*/ 852*4882a593Smuzhiyun rockchip,grf = <&grf>; 853*4882a593Smuzhiyun pinctrl-names = "default"; 854*4882a593Smuzhiyun pinctrl-0 = <&cifm0_dvp_ctl>; 855*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 856*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 857*4882a593Smuzhiyun rockchip,camera-module-name = "CMK-OT0836-PT2"; 858*4882a593Smuzhiyun rockchip,camera-module-lens-name = "YT-2929"; 859*4882a593Smuzhiyun port { 860*4882a593Smuzhiyun cam_para_out1: endpoint { 861*4882a593Smuzhiyun /* remote-endpoint = <&cif_para_in>; */ 862*4882a593Smuzhiyun }; 863*4882a593Smuzhiyun }; 864*4882a593Smuzhiyun }; 865*4882a593Smuzhiyun 866*4882a593Smuzhiyun ov4689: ov4689@36 { 867*4882a593Smuzhiyun compatible = "ovti,ov4689"; 868*4882a593Smuzhiyun reg = <0x36>; 869*4882a593Smuzhiyun clocks = <&cru CLK_MIPICSI_OUT>; 870*4882a593Smuzhiyun clock-names = "xvclk"; 871*4882a593Smuzhiyun power-domains = <&power RV1126_PD_VI>; 872*4882a593Smuzhiyun pinctrl-names = "rockchip,camera_default"; 873*4882a593Smuzhiyun pinctrl-0 = <&mipicsi_clk1>; 874*4882a593Smuzhiyun /*pinctrl-0 = <&mipicsi_clk0>;*/ 875*4882a593Smuzhiyun avdd-supply = <&vcc_avdd>; 876*4882a593Smuzhiyun dovdd-supply = <&vcc_dovdd>; 877*4882a593Smuzhiyun dvdd-supply = <&vcc_dvdd>; 878*4882a593Smuzhiyun pwdn-gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_HIGH>; 879*4882a593Smuzhiyun /*pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;*/ 880*4882a593Smuzhiyun rockchip,camera-module-index = <1>; 881*4882a593Smuzhiyun rockchip,camera-module-facing = "front"; 882*4882a593Smuzhiyun rockchip,camera-module-name = "JSD3425-C1"; 883*4882a593Smuzhiyun rockchip,camera-module-lens-name = "JSD3425-C1"; 884*4882a593Smuzhiyun /* NO_HDR:0 HDR_X2:5 HDR_X3:6 */ 885*4882a593Smuzhiyun rockchip,camera-hdr-mode = <0>; 886*4882a593Smuzhiyun port { 887*4882a593Smuzhiyun ucam_out1: endpoint { 888*4882a593Smuzhiyun remote-endpoint = <&csi_dphy1_input>; 889*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 890*4882a593Smuzhiyun }; 891*4882a593Smuzhiyun }; 892*4882a593Smuzhiyun 893*4882a593Smuzhiyun }; 894*4882a593Smuzhiyun 895*4882a593Smuzhiyun os04a10: os04a10@36 { 896*4882a593Smuzhiyun compatible = "ovti,os04a10"; 897*4882a593Smuzhiyun reg = <0x36>; 898*4882a593Smuzhiyun clocks = <&cru CLK_MIPICSI_OUT>; 899*4882a593Smuzhiyun clock-names = "xvclk"; 900*4882a593Smuzhiyun power-domains = <&power RV1126_PD_VI>; 901*4882a593Smuzhiyun pinctrl-names = "rockchip,camera_default"; 902*4882a593Smuzhiyun pinctrl-0 = <&mipicsi_clk0>; 903*4882a593Smuzhiyun avdd-supply = <&vcc_avdd>; 904*4882a593Smuzhiyun dovdd-supply = <&vcc_dovdd>; 905*4882a593Smuzhiyun dvdd-supply = <&vcc_dvdd>; 906*4882a593Smuzhiyun pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; 907*4882a593Smuzhiyun rockchip,camera-module-index = <1>; 908*4882a593Smuzhiyun rockchip,camera-module-facing = "front"; 909*4882a593Smuzhiyun rockchip,camera-module-name = "CMK-OT1607-FV1"; 910*4882a593Smuzhiyun rockchip,camera-module-lens-name = "M12-40IRC-4MP-F16"; 911*4882a593Smuzhiyun ir-cut = <&cam_ircut0>; 912*4882a593Smuzhiyun port { 913*4882a593Smuzhiyun ucam_out0: endpoint { 914*4882a593Smuzhiyun remote-endpoint = <&mipi_in_ucam0>; 915*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 916*4882a593Smuzhiyun }; 917*4882a593Smuzhiyun }; 918*4882a593Smuzhiyun }; 919*4882a593Smuzhiyun}; 920*4882a593Smuzhiyun 921*4882a593Smuzhiyun&i2c5 { 922*4882a593Smuzhiyun status = "okay"; 923*4882a593Smuzhiyun clock-frequency = <400000>; 924*4882a593Smuzhiyun 925*4882a593Smuzhiyun gt1x: gt1x@14 { 926*4882a593Smuzhiyun compatible = "goodix,gt1x"; 927*4882a593Smuzhiyun reg = <0x14>; 928*4882a593Smuzhiyun gtp_ics_slot_report; 929*4882a593Smuzhiyun power-supply = <&vcc18_lcd_n>; 930*4882a593Smuzhiyun goodix,rst-gpio = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>; 931*4882a593Smuzhiyun goodix,irq-gpio = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>; 932*4882a593Smuzhiyun }; 933*4882a593Smuzhiyun}; 934*4882a593Smuzhiyun 935*4882a593Smuzhiyun&i2s0_8ch { 936*4882a593Smuzhiyun status = "okay"; 937*4882a593Smuzhiyun #sound-dai-cells = <0>; 938*4882a593Smuzhiyun rockchip,clk-trcm = <1>; 939*4882a593Smuzhiyun rockchip,i2s-rx-route = <3 1 2 0>; 940*4882a593Smuzhiyun pinctrl-names = "default"; 941*4882a593Smuzhiyun pinctrl-0 = <&i2s0m0_sclk_tx 942*4882a593Smuzhiyun &i2s0m0_lrck_tx 943*4882a593Smuzhiyun &i2s0m0_sdo0 944*4882a593Smuzhiyun &i2s0m0_sdo1_sdi3>; 945*4882a593Smuzhiyun}; 946*4882a593Smuzhiyun 947*4882a593Smuzhiyun&iep { 948*4882a593Smuzhiyun status = "okay"; 949*4882a593Smuzhiyun}; 950*4882a593Smuzhiyun 951*4882a593Smuzhiyun&iep_mmu { 952*4882a593Smuzhiyun status = "okay"; 953*4882a593Smuzhiyun}; 954*4882a593Smuzhiyun 955*4882a593Smuzhiyun&mdio { 956*4882a593Smuzhiyun phy: phy@0 { 957*4882a593Smuzhiyun compatible = "ethernet-phy-ieee802.3-c22"; 958*4882a593Smuzhiyun reg = <0x0>; 959*4882a593Smuzhiyun clocks = <&cru CLK_GMAC_ETHERNET_OUT>; 960*4882a593Smuzhiyun }; 961*4882a593Smuzhiyun}; 962*4882a593Smuzhiyun 963*4882a593Smuzhiyun&mipi_csi2 { 964*4882a593Smuzhiyun status = "okay"; 965*4882a593Smuzhiyun 966*4882a593Smuzhiyun ports { 967*4882a593Smuzhiyun #address-cells = <1>; 968*4882a593Smuzhiyun #size-cells = <0>; 969*4882a593Smuzhiyun 970*4882a593Smuzhiyun port@0 { 971*4882a593Smuzhiyun reg = <0>; 972*4882a593Smuzhiyun #address-cells = <1>; 973*4882a593Smuzhiyun #size-cells = <0>; 974*4882a593Smuzhiyun 975*4882a593Smuzhiyun mipi_csi2_input: endpoint@1 { 976*4882a593Smuzhiyun reg = <1>; 977*4882a593Smuzhiyun remote-endpoint = <&csidphy0_out>; 978*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 979*4882a593Smuzhiyun }; 980*4882a593Smuzhiyun }; 981*4882a593Smuzhiyun 982*4882a593Smuzhiyun port@1 { 983*4882a593Smuzhiyun reg = <1>; 984*4882a593Smuzhiyun #address-cells = <1>; 985*4882a593Smuzhiyun #size-cells = <0>; 986*4882a593Smuzhiyun 987*4882a593Smuzhiyun mipi_csi2_output: endpoint@0 { 988*4882a593Smuzhiyun reg = <0>; 989*4882a593Smuzhiyun remote-endpoint = <&cif_mipi_in>; 990*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 991*4882a593Smuzhiyun }; 992*4882a593Smuzhiyun }; 993*4882a593Smuzhiyun }; 994*4882a593Smuzhiyun}; 995*4882a593Smuzhiyun 996*4882a593Smuzhiyun&mipi_dphy { 997*4882a593Smuzhiyun status = "okay"; 998*4882a593Smuzhiyun}; 999*4882a593Smuzhiyun 1000*4882a593Smuzhiyun&mpp_srv { 1001*4882a593Smuzhiyun status = "okay"; 1002*4882a593Smuzhiyun}; 1003*4882a593Smuzhiyun 1004*4882a593Smuzhiyun&nandc { 1005*4882a593Smuzhiyun /delete-property/ pinctrl-names; 1006*4882a593Smuzhiyun /delete-property/ pinctrl-0; 1007*4882a593Smuzhiyun #address-cells = <1>; 1008*4882a593Smuzhiyun #size-cells = <0>; 1009*4882a593Smuzhiyun 1010*4882a593Smuzhiyun nand@0 { 1011*4882a593Smuzhiyun reg = <0>; 1012*4882a593Smuzhiyun nand-bus-width = <8>; 1013*4882a593Smuzhiyun nand-ecc-mode = "hw"; 1014*4882a593Smuzhiyun nand-ecc-strength = <16>; 1015*4882a593Smuzhiyun nand-ecc-step-size = <1024>; 1016*4882a593Smuzhiyun }; 1017*4882a593Smuzhiyun}; 1018*4882a593Smuzhiyun 1019*4882a593Smuzhiyun&npu { 1020*4882a593Smuzhiyun npu-supply = <&vdd_npu>; 1021*4882a593Smuzhiyun status = "okay"; 1022*4882a593Smuzhiyun}; 1023*4882a593Smuzhiyun 1024*4882a593Smuzhiyun&npu_tsadc { 1025*4882a593Smuzhiyun status = "okay"; 1026*4882a593Smuzhiyun}; 1027*4882a593Smuzhiyun 1028*4882a593Smuzhiyun&optee { 1029*4882a593Smuzhiyun status = "disabled"; 1030*4882a593Smuzhiyun}; 1031*4882a593Smuzhiyun 1032*4882a593Smuzhiyun&otp { 1033*4882a593Smuzhiyun status = "okay"; 1034*4882a593Smuzhiyun}; 1035*4882a593Smuzhiyun 1036*4882a593Smuzhiyun&pdm { 1037*4882a593Smuzhiyun status = "disabled"; 1038*4882a593Smuzhiyun #sound-dai-cells = <0>; 1039*4882a593Smuzhiyun pinctrl-names = "default"; 1040*4882a593Smuzhiyun pinctrl-0 = <&pdmm0_clk 1041*4882a593Smuzhiyun &pdmm0_clk1 1042*4882a593Smuzhiyun &pdmm0_sdi0 1043*4882a593Smuzhiyun &pdmm0_sdi1 1044*4882a593Smuzhiyun &pdmm0_sdi2>; 1045*4882a593Smuzhiyun}; 1046*4882a593Smuzhiyun 1047*4882a593Smuzhiyun&pinctrl { 1048*4882a593Smuzhiyun pmic { 1049*4882a593Smuzhiyun /omit-if-no-ref/ 1050*4882a593Smuzhiyun pmic_int: pmic_int { 1051*4882a593Smuzhiyun rockchip,pins = 1052*4882a593Smuzhiyun <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; 1053*4882a593Smuzhiyun }; 1054*4882a593Smuzhiyun 1055*4882a593Smuzhiyun /omit-if-no-ref/ 1056*4882a593Smuzhiyun soc_slppin_gpio: soc_slppin_gpio { 1057*4882a593Smuzhiyun rockchip,pins = 1058*4882a593Smuzhiyun <0 RK_PB2 RK_FUNC_GPIO &pcfg_output_low>; 1059*4882a593Smuzhiyun }; 1060*4882a593Smuzhiyun 1061*4882a593Smuzhiyun /omit-if-no-ref/ 1062*4882a593Smuzhiyun soc_slppin_slp: soc_slppin_slp { 1063*4882a593Smuzhiyun rockchip,pins = 1064*4882a593Smuzhiyun <0 RK_PB2 1 &pcfg_pull_none>; 1065*4882a593Smuzhiyun }; 1066*4882a593Smuzhiyun 1067*4882a593Smuzhiyun /omit-if-no-ref/ 1068*4882a593Smuzhiyun soc_slppin_rst: soc_slppin_rst { 1069*4882a593Smuzhiyun rockchip,pins = 1070*4882a593Smuzhiyun <0 RK_PB2 2 &pcfg_pull_none>; 1071*4882a593Smuzhiyun }; 1072*4882a593Smuzhiyun }; 1073*4882a593Smuzhiyun 1074*4882a593Smuzhiyun sdio-pwrseq { 1075*4882a593Smuzhiyun /omit-if-no-ref/ 1076*4882a593Smuzhiyun wifi_enable_h: wifi-enable-h { 1077*4882a593Smuzhiyun rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1078*4882a593Smuzhiyun }; 1079*4882a593Smuzhiyun }; 1080*4882a593Smuzhiyun 1081*4882a593Smuzhiyun wireless-wlan { 1082*4882a593Smuzhiyun /omit-if-no-ref/ 1083*4882a593Smuzhiyun wifi_wake_host: wifi-wake-host { 1084*4882a593Smuzhiyun rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; 1085*4882a593Smuzhiyun }; 1086*4882a593Smuzhiyun }; 1087*4882a593Smuzhiyun}; 1088*4882a593Smuzhiyun 1089*4882a593Smuzhiyun&pmu_io_domains { 1090*4882a593Smuzhiyun status = "okay"; 1091*4882a593Smuzhiyun 1092*4882a593Smuzhiyun pmuio0-supply = <&vcc1v8_pmu>; 1093*4882a593Smuzhiyun pmuio1-supply = <&vcc3v3_sys>; 1094*4882a593Smuzhiyun vccio2-supply = <&vccio_sd>; 1095*4882a593Smuzhiyun vccio3-supply = <&vcc_1v8>; 1096*4882a593Smuzhiyun vccio4-supply = <&vcc_1v8>; 1097*4882a593Smuzhiyun vccio5-supply = <&vcc_3v3>; 1098*4882a593Smuzhiyun vccio6-supply = <&vcc_1v8>; 1099*4882a593Smuzhiyun vccio7-supply = <&vcc_1v8>; 1100*4882a593Smuzhiyun}; 1101*4882a593Smuzhiyun 1102*4882a593Smuzhiyun&pwm0 { 1103*4882a593Smuzhiyun status = "okay"; 1104*4882a593Smuzhiyun pinctrl-names = "active"; 1105*4882a593Smuzhiyun pinctrl-0 = <&pwm0m0_pins_pull_down>; 1106*4882a593Smuzhiyun}; 1107*4882a593Smuzhiyun 1108*4882a593Smuzhiyun&pwm1 { 1109*4882a593Smuzhiyun status = "okay"; 1110*4882a593Smuzhiyun pinctrl-names = "active"; 1111*4882a593Smuzhiyun pinctrl-0 = <&pwm1m0_pins_pull_down>; 1112*4882a593Smuzhiyun}; 1113*4882a593Smuzhiyun 1114*4882a593Smuzhiyun&pwm3 { 1115*4882a593Smuzhiyun status = "okay"; 1116*4882a593Smuzhiyun}; 1117*4882a593Smuzhiyun 1118*4882a593Smuzhiyun&ramoops { 1119*4882a593Smuzhiyun status = "okay"; 1120*4882a593Smuzhiyun}; 1121*4882a593Smuzhiyun 1122*4882a593Smuzhiyun&rk_rga { 1123*4882a593Smuzhiyun status = "okay"; 1124*4882a593Smuzhiyun}; 1125*4882a593Smuzhiyun 1126*4882a593Smuzhiyun&rkcif { 1127*4882a593Smuzhiyun status = "okay"; 1128*4882a593Smuzhiyun}; 1129*4882a593Smuzhiyun 1130*4882a593Smuzhiyun&rkcif_mmu { 1131*4882a593Smuzhiyun status = "disabled"; 1132*4882a593Smuzhiyun}; 1133*4882a593Smuzhiyun 1134*4882a593Smuzhiyun&rkcif_dvp { 1135*4882a593Smuzhiyun status = "okay"; 1136*4882a593Smuzhiyun 1137*4882a593Smuzhiyun port { 1138*4882a593Smuzhiyun /* Parallel bus endpoint */ 1139*4882a593Smuzhiyun /* 1140*4882a593Smuzhiyun cif_para_in: endpoint { 1141*4882a593Smuzhiyun remote-endpoint = <&cam_para_out1>; 1142*4882a593Smuzhiyun bus-width = <12>; 1143*4882a593Smuzhiyun hsync-active = <1>; 1144*4882a593Smuzhiyun vsync-active = <0>; 1145*4882a593Smuzhiyun }; 1146*4882a593Smuzhiyun */ 1147*4882a593Smuzhiyun }; 1148*4882a593Smuzhiyun}; 1149*4882a593Smuzhiyun 1150*4882a593Smuzhiyun&rkcif_mipi_lvds { 1151*4882a593Smuzhiyun status = "okay"; 1152*4882a593Smuzhiyun 1153*4882a593Smuzhiyun port { 1154*4882a593Smuzhiyun /* MIPI CSI-2 endpoint */ 1155*4882a593Smuzhiyun cif_mipi_in: endpoint { 1156*4882a593Smuzhiyun remote-endpoint = <&mipi_csi2_output>; 1157*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 1158*4882a593Smuzhiyun }; 1159*4882a593Smuzhiyun }; 1160*4882a593Smuzhiyun}; 1161*4882a593Smuzhiyun 1162*4882a593Smuzhiyun&rkcif_mipi_lvds_sditf { 1163*4882a593Smuzhiyun status = "okay"; 1164*4882a593Smuzhiyun 1165*4882a593Smuzhiyun port { 1166*4882a593Smuzhiyun /* MIPI CSI-2 endpoint */ 1167*4882a593Smuzhiyun mipi_lvds_sditf: endpoint { 1168*4882a593Smuzhiyun remote-endpoint = <&isp_in>; 1169*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 1170*4882a593Smuzhiyun }; 1171*4882a593Smuzhiyun }; 1172*4882a593Smuzhiyun}; 1173*4882a593Smuzhiyun 1174*4882a593Smuzhiyun&rkisp { 1175*4882a593Smuzhiyun status = "okay"; 1176*4882a593Smuzhiyun}; 1177*4882a593Smuzhiyun 1178*4882a593Smuzhiyun&rkisp_vir0 { 1179*4882a593Smuzhiyun status = "okay"; 1180*4882a593Smuzhiyun 1181*4882a593Smuzhiyun ports { 1182*4882a593Smuzhiyun port@0 { 1183*4882a593Smuzhiyun reg = <0>; 1184*4882a593Smuzhiyun #address-cells = <1>; 1185*4882a593Smuzhiyun #size-cells = <0>; 1186*4882a593Smuzhiyun 1187*4882a593Smuzhiyun isp_in: endpoint@0 { 1188*4882a593Smuzhiyun reg = <0>; 1189*4882a593Smuzhiyun remote-endpoint = <&mipi_lvds_sditf>; 1190*4882a593Smuzhiyun }; 1191*4882a593Smuzhiyun }; 1192*4882a593Smuzhiyun }; 1193*4882a593Smuzhiyun}; 1194*4882a593Smuzhiyun 1195*4882a593Smuzhiyun&rkisp_mmu { 1196*4882a593Smuzhiyun status = "disabled"; 1197*4882a593Smuzhiyun}; 1198*4882a593Smuzhiyun 1199*4882a593Smuzhiyun&rkispp { 1200*4882a593Smuzhiyun status = "okay"; 1201*4882a593Smuzhiyun /* the max input w h and fps of mulit sensor */ 1202*4882a593Smuzhiyun //max-input = <2688 1520 30>; 1203*4882a593Smuzhiyun}; 1204*4882a593Smuzhiyun 1205*4882a593Smuzhiyun&rkispp_vir0 { 1206*4882a593Smuzhiyun status = "okay"; 1207*4882a593Smuzhiyun}; 1208*4882a593Smuzhiyun 1209*4882a593Smuzhiyun&rkispp_mmu { 1210*4882a593Smuzhiyun status = "okay"; 1211*4882a593Smuzhiyun}; 1212*4882a593Smuzhiyun 1213*4882a593Smuzhiyun&rkvdec { 1214*4882a593Smuzhiyun status = "okay"; 1215*4882a593Smuzhiyun}; 1216*4882a593Smuzhiyun 1217*4882a593Smuzhiyun&rkvdec_mmu { 1218*4882a593Smuzhiyun status = "okay"; 1219*4882a593Smuzhiyun}; 1220*4882a593Smuzhiyun 1221*4882a593Smuzhiyun&rkvenc { 1222*4882a593Smuzhiyun venc-supply = <&vdd_vepu>; 1223*4882a593Smuzhiyun status = "okay"; 1224*4882a593Smuzhiyun}; 1225*4882a593Smuzhiyun 1226*4882a593Smuzhiyun&rkvenc_mmu { 1227*4882a593Smuzhiyun status = "okay"; 1228*4882a593Smuzhiyun}; 1229*4882a593Smuzhiyun 1230*4882a593Smuzhiyun&rng { 1231*4882a593Smuzhiyun status = "okay"; 1232*4882a593Smuzhiyun}; 1233*4882a593Smuzhiyun 1234*4882a593Smuzhiyun&rockchip_suspend { 1235*4882a593Smuzhiyun status = "okay"; 1236*4882a593Smuzhiyun rockchip,sleep-debug-en = <1>; 1237*4882a593Smuzhiyun rockchip,sleep-mode-config = < 1238*4882a593Smuzhiyun (0 1239*4882a593Smuzhiyun | RKPM_SLP_ARMOFF 1240*4882a593Smuzhiyun | RKPM_SLP_PMU_PMUALIVE_32K 1241*4882a593Smuzhiyun | RKPM_SLP_PMU_DIS_OSC 1242*4882a593Smuzhiyun | RKPM_SLP_PMIC_LP 1243*4882a593Smuzhiyun ) 1244*4882a593Smuzhiyun >; 1245*4882a593Smuzhiyun rockchip,wakeup-config = < 1246*4882a593Smuzhiyun (0 1247*4882a593Smuzhiyun | RKPM_GPIO_WKUP_EN 1248*4882a593Smuzhiyun ) 1249*4882a593Smuzhiyun >; 1250*4882a593Smuzhiyun}; 1251*4882a593Smuzhiyun 1252*4882a593Smuzhiyun&route_dsi { 1253*4882a593Smuzhiyun status = "okay"; 1254*4882a593Smuzhiyun}; 1255*4882a593Smuzhiyun 1256*4882a593Smuzhiyun&saradc { 1257*4882a593Smuzhiyun status = "okay"; 1258*4882a593Smuzhiyun vref-supply = <&vcc_1v8>; 1259*4882a593Smuzhiyun}; 1260*4882a593Smuzhiyun 1261*4882a593Smuzhiyun&sdmmc { 1262*4882a593Smuzhiyun bus-width = <4>; 1263*4882a593Smuzhiyun cap-mmc-highspeed; 1264*4882a593Smuzhiyun cap-sd-highspeed; 1265*4882a593Smuzhiyun card-detect-delay = <200>; 1266*4882a593Smuzhiyun rockchip,default-sample-phase = <90>; 1267*4882a593Smuzhiyun no-sdio; 1268*4882a593Smuzhiyun no-mmc; 1269*4882a593Smuzhiyun sd-uhs-sdr12; 1270*4882a593Smuzhiyun sd-uhs-sdr25; 1271*4882a593Smuzhiyun sd-uhs-sdr104; 1272*4882a593Smuzhiyun vqmmc-supply = <&vccio_sd>; 1273*4882a593Smuzhiyun vmmc-supply = <&vcc3v3_sd>; 1274*4882a593Smuzhiyun status = "okay"; 1275*4882a593Smuzhiyun}; 1276*4882a593Smuzhiyun 1277*4882a593Smuzhiyun&sdio { 1278*4882a593Smuzhiyun max-frequency = <200000000>; 1279*4882a593Smuzhiyun bus-width = <4>; 1280*4882a593Smuzhiyun cap-sd-highspeed; 1281*4882a593Smuzhiyun cap-sdio-irq; 1282*4882a593Smuzhiyun keep-power-in-suspend; 1283*4882a593Smuzhiyun non-removable; 1284*4882a593Smuzhiyun rockchip,default-sample-phase = <90>; 1285*4882a593Smuzhiyun sd-uhs-sdr104; 1286*4882a593Smuzhiyun no-sd; 1287*4882a593Smuzhiyun no-mmc; 1288*4882a593Smuzhiyun mmc-pwrseq = <&sdio_pwrseq>; 1289*4882a593Smuzhiyun status = "okay"; 1290*4882a593Smuzhiyun}; 1291*4882a593Smuzhiyun 1292*4882a593Smuzhiyun&sfc { 1293*4882a593Smuzhiyun /delete-property/ pinctrl-names; 1294*4882a593Smuzhiyun /delete-property/ pinctrl-0; 1295*4882a593Smuzhiyun status = "okay"; 1296*4882a593Smuzhiyun 1297*4882a593Smuzhiyun flash@0 { 1298*4882a593Smuzhiyun compatible = "spi-nand"; 1299*4882a593Smuzhiyun reg = <0>; 1300*4882a593Smuzhiyun spi-max-frequency = <80000000>; 1301*4882a593Smuzhiyun spi-rx-bus-width = <4>; 1302*4882a593Smuzhiyun spi-tx-bus-width = <1>; 1303*4882a593Smuzhiyun }; 1304*4882a593Smuzhiyun}; 1305*4882a593Smuzhiyun 1306*4882a593Smuzhiyun&u2phy0 { 1307*4882a593Smuzhiyun status = "okay"; 1308*4882a593Smuzhiyun vup-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_LOW>; 1309*4882a593Smuzhiyun u2phy_otg: otg-port { 1310*4882a593Smuzhiyun status = "okay"; 1311*4882a593Smuzhiyun }; 1312*4882a593Smuzhiyun}; 1313*4882a593Smuzhiyun 1314*4882a593Smuzhiyun&u2phy1 { 1315*4882a593Smuzhiyun status = "okay"; 1316*4882a593Smuzhiyun u2phy_host: host-port { 1317*4882a593Smuzhiyun status = "okay"; 1318*4882a593Smuzhiyun phy-supply = <&vcc5v0_host>; 1319*4882a593Smuzhiyun }; 1320*4882a593Smuzhiyun}; 1321*4882a593Smuzhiyun 1322*4882a593Smuzhiyun&uart0 { 1323*4882a593Smuzhiyun pinctrl-names = "default"; 1324*4882a593Smuzhiyun pinctrl-0 = <&uart0_xfer &uart0_ctsn>; 1325*4882a593Smuzhiyun status = "okay"; 1326*4882a593Smuzhiyun}; 1327*4882a593Smuzhiyun 1328*4882a593Smuzhiyun&usb_host0_ehci { 1329*4882a593Smuzhiyun status = "okay"; 1330*4882a593Smuzhiyun}; 1331*4882a593Smuzhiyun 1332*4882a593Smuzhiyun&usb_host0_ohci { 1333*4882a593Smuzhiyun status = "okay"; 1334*4882a593Smuzhiyun}; 1335*4882a593Smuzhiyun 1336*4882a593Smuzhiyun&usbdrd { 1337*4882a593Smuzhiyun status = "okay"; 1338*4882a593Smuzhiyun}; 1339*4882a593Smuzhiyun 1340*4882a593Smuzhiyun&usbdrd_dwc3 { 1341*4882a593Smuzhiyun status = "okay"; 1342*4882a593Smuzhiyun extcon = <&u2phy0>; 1343*4882a593Smuzhiyun}; 1344*4882a593Smuzhiyun 1345*4882a593Smuzhiyun&vdpu { 1346*4882a593Smuzhiyun status = "okay"; 1347*4882a593Smuzhiyun}; 1348*4882a593Smuzhiyun 1349*4882a593Smuzhiyun&vepu { 1350*4882a593Smuzhiyun status = "okay"; 1351*4882a593Smuzhiyun}; 1352*4882a593Smuzhiyun 1353*4882a593Smuzhiyun&vpu_mmu { 1354*4882a593Smuzhiyun status = "okay"; 1355*4882a593Smuzhiyun}; 1356*4882a593Smuzhiyun 1357*4882a593Smuzhiyun&vop { 1358*4882a593Smuzhiyun status = "okay"; 1359*4882a593Smuzhiyun}; 1360*4882a593Smuzhiyun 1361*4882a593Smuzhiyun&vop_mmu { 1362*4882a593Smuzhiyun status = "okay"; 1363*4882a593Smuzhiyun}; 1364