1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/display/drm_mipi_dsi.h> 7#include <dt-bindings/input/input.h> 8 9/ { 10 adc-keys { 11 compatible = "adc-keys"; 12 io-channels = <&saradc 0>; 13 io-channel-names = "buttons"; 14 poll-interval = <100>; 15 keyup-threshold-microvolt = <1800000>; 16 17 esc-key { 18 label = "esc"; 19 linux,code = <KEY_ESC>; 20 press-threshold-microvolt = <0>; 21 }; 22 23 right-key { 24 label = "right"; 25 linux,code = <KEY_RIGHT>; 26 press-threshold-microvolt = <400781>; 27 }; 28 29 left-key { 30 label = "left"; 31 linux,code = <KEY_LEFT>; 32 press-threshold-microvolt = <801562>; 33 }; 34 35 menu-key { 36 label = "menu"; 37 linux,code = <KEY_MENU>; 38 press-threshold-microvolt = <1198828>; 39 }; 40 }; 41 42 backlight: backlight { 43 compatible = "pwm-backlight"; 44 pwms = <&pwm3 0 25000 0>; 45 brightness-levels = < 46 0 1 2 3 4 5 6 7 47 8 9 10 11 12 13 14 15 48 16 17 18 19 20 21 22 23 49 24 25 26 27 28 29 30 31 50 32 33 34 35 36 37 38 39 51 40 41 42 43 44 45 46 47 52 48 49 50 51 52 53 54 55 53 56 57 58 59 60 61 62 63 54 64 65 66 67 68 69 70 71 55 72 73 74 75 76 77 78 79 56 80 81 82 83 84 85 86 87 57 88 89 90 91 92 93 94 95 58 96 97 98 99 100 101 102 103 59 104 105 106 107 108 109 110 111 60 112 113 114 115 116 117 118 119 61 120 121 122 123 124 125 126 127 62 128 129 130 131 132 133 134 135 63 136 137 138 139 140 141 142 143 64 144 145 146 147 148 149 150 151 65 152 153 154 155 156 157 158 159 66 160 161 162 163 164 165 166 167 67 168 169 170 171 172 173 174 175 68 176 177 178 179 180 181 182 183 69 184 185 186 187 188 189 190 191 70 192 193 194 195 196 197 198 199 71 200 201 202 203 204 205 206 207 72 208 209 210 211 212 213 214 215 73 216 217 218 219 220 221 222 223 74 224 225 226 227 228 229 230 231 75 232 233 234 235 236 237 238 239 76 240 241 242 243 244 245 246 247 77 248 249 250 251 252 253 254 255>; 78 default-brightness-level = <200>; 79 }; 80 81 cam_ircut0: cam_ircut { 82 status = "okay"; 83 compatible = "rockchip,ircut"; 84 ircut-open-gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_HIGH>; 85 ircut-close-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; 86 rockchip,camera-module-index = <1>; 87 rockchip,camera-module-facing = "front"; 88 }; 89 90 dummy_codec: dummy-codec { 91 compatible = "rockchip,dummy-codec"; 92 #sound-dai-cells = <0>; 93 }; 94 95 pdm_mic_array: pdm-mic_array { 96 status = "disabled"; 97 compatible = "simple-audio-card"; 98 simple-audio-card,name = "rockchip,pdm-mic-array"; 99 simple-audio-card,cpu { 100 sound-dai = <&pdm>; 101 }; 102 simple-audio-card,codec { 103 sound-dai = <&dummy_codec>; 104 }; 105 }; 106 107 rk809_sound: rk809-sound { 108 compatible = "simple-audio-card"; 109 simple-audio-card,format = "i2s"; 110 simple-audio-card,name = "rockchip,rk809-codec"; 111 simple-audio-card,mclk-fs = <256>; 112 simple-audio-card,cpu { 113 sound-dai = <&i2s0_8ch>; 114 }; 115 simple-audio-card,codec { 116 sound-dai = <&rk809_codec>; 117 }; 118 }; 119 120 sdio_pwrseq: sdio-pwrseq { 121 compatible = "mmc-pwrseq-simple"; 122 pinctrl-names = "default"; 123 pinctrl-0 = <&wifi_enable_h>; 124 125 /* 126 * On the module itself this is one of these (depending 127 * on the actual card populated): 128 * - SDIO_RESET_L_WL_REG_ON 129 * - PDN (power down when low) 130 */ 131 reset-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; 132 }; 133 134 vcc18_lcd_n: vcc18-lcd-n { 135 compatible = "regulator-fixed"; 136 regulator-name = "vcc18_lcd_n"; 137 gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; 138 enable-active-high; 139 regulator-boot-on; 140 }; 141 142 vcc5v0_sys: vccsys { 143 compatible = "regulator-fixed"; 144 regulator-name = "vcc5v0_sys"; 145 regulator-always-on; 146 regulator-boot-on; 147 regulator-min-microvolt = <5000000>; 148 regulator-max-microvolt = <5000000>; 149 }; 150 151 vdd_npu: vdd-npu { 152 compatible = "pwm-regulator"; 153 pwms = <&pwm0 0 5000 1>; 154 regulator-name = "vdd_npu"; 155 regulator-min-microvolt = <650000>; 156 regulator-max-microvolt = <950000>; 157 regulator-init-microvolt = <800000>; 158 regulator-always-on; 159 regulator-boot-on; 160 regulator-settling-time-up-us = <250>; 161 pwm-supply = <&vcc5v0_sys>; 162 status = "okay"; 163 }; 164 165 vdd_vepu: vdd-vepu { 166 compatible = "pwm-regulator"; 167 pwms = <&pwm1 0 5000 1>; 168 regulator-name = "vdd_vepu"; 169 regulator-min-microvolt = <650000>; 170 regulator-max-microvolt = <950000>; 171 regulator-init-microvolt = <800000>; 172 regulator-always-on; 173 regulator-boot-on; 174 regulator-settling-time-up-us = <250>; 175 pwm-supply = <&vcc5v0_sys>; 176 status = "okay"; 177 }; 178 179 wireless-bluetooth { 180 compatible = "bluetooth-platdata"; 181 uart_rts_gpios = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>; 182 pinctrl-names = "default", "rts_gpio"; 183 pinctrl-0 = <&uart0_rtsn>; 184 pinctrl-1 = <&uart0_rtsn_gpio>; 185 BT,power_gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>; 186 BT,wake_host_irq = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; 187 status = "okay"; 188 }; 189 190 wireless_wlan: wireless-wlan { 191 compatible = "wlan-platdata"; 192 rockchip,grf = <&grf>; 193 clocks = <&rk809 1>; 194 clock-names = "clk_wifi"; 195 pinctrl-names = "default"; 196 pinctrl-0 = <&wifi_wake_host>; 197 wifi_chip_type = "ap6255"; 198 /* WIFI,poweren_gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; */ 199 WIFI,host_wake_irq = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; 200 status = "okay"; 201 }; 202}; 203 204&cpu0 { 205 cpu-supply = <&vdd_arm>; 206}; 207 208&cpu_tsadc { 209 status = "okay"; 210}; 211 212&display_subsystem { 213 status = "okay"; 214}; 215 216&dsi { 217 status = "okay"; 218 219 rockchip,lane-rate = <480>; 220 panel@0 { 221 compatible = "ilitek,ili9881d", "simple-panel-dsi"; 222 reg = <0>; 223 backlight = <&backlight>; 224 power-supply = <&vcc18_lcd_n>; 225 prepare-delay-ms = <5>; 226 reset-delay-ms = <1>; 227 init-delay-ms = <80>; 228 disable-delay-ms = <10>; 229 unprepare-delay-ms = <5>; 230 231 width-mm = <68>; 232 height-mm = <121>; 233 234 dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 235 MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; 236 dsi,format = <MIPI_DSI_FMT_RGB888>; 237 dsi,lanes = <4>; 238 239 panel-init-sequence = [ 240 39 00 04 ff 98 81 03 241 15 00 02 01 00 242 15 00 02 02 00 243 15 00 02 03 53 244 15 00 02 04 53 245 15 00 02 05 13 246 15 00 02 06 04 247 15 00 02 07 02 248 15 00 02 08 02 249 15 00 02 09 00 250 15 00 02 0a 00 251 15 00 02 0b 00 252 15 00 02 0c 00 253 15 00 02 0d 00 254 15 00 02 0e 00 255 15 00 02 0f 00 256 15 00 02 10 00 257 15 00 02 11 00 258 15 00 02 12 00 259 15 00 02 13 00 260 15 00 02 14 00 261 15 00 02 15 08 262 15 00 02 16 10 263 15 00 02 17 00 264 15 00 02 18 08 265 15 00 02 19 00 266 15 00 02 1a 00 267 15 00 02 1b 00 268 15 00 02 1c 00 269 15 00 02 1d 00 270 15 00 02 1e c0 271 15 00 02 1f 80 272 15 00 02 20 02 273 15 00 02 21 09 274 15 00 02 22 00 275 15 00 02 23 00 276 15 00 02 24 00 277 15 00 02 25 00 278 15 00 02 26 00 279 15 00 02 27 00 280 15 00 02 28 55 281 15 00 02 29 03 282 15 00 02 2a 00 283 15 00 02 2b 00 284 15 00 02 2c 00 285 15 00 02 2d 00 286 15 00 02 2e 00 287 15 00 02 2f 00 288 15 00 02 30 00 289 15 00 02 31 00 290 15 00 02 32 00 291 15 00 02 33 00 292 15 00 02 34 04 293 15 00 02 35 05 294 15 00 02 36 05 295 15 00 02 37 00 296 15 00 02 38 3c 297 15 00 02 39 35 298 15 00 02 3a 00 299 15 00 02 3b 40 300 15 00 02 3c 00 301 15 00 02 3d 00 302 15 00 02 3e 00 303 15 00 02 3f 00 304 15 00 02 40 00 305 15 00 02 41 88 306 15 00 02 42 00 307 15 00 02 43 00 308 15 00 02 44 1f 309 15 00 02 50 01 310 15 00 02 51 23 311 15 00 02 52 45 312 15 00 02 53 67 313 15 00 02 54 89 314 15 00 02 55 ab 315 15 00 02 56 01 316 15 00 02 57 23 317 15 00 02 58 45 318 15 00 02 59 67 319 15 00 02 5a 89 320 15 00 02 5b ab 321 15 00 02 5c cd 322 15 00 02 5d ef 323 15 00 02 5e 03 324 15 00 02 5f 14 325 15 00 02 60 15 326 15 00 02 61 0c 327 15 00 02 62 0d 328 15 00 02 63 0e 329 15 00 02 64 0f 330 15 00 02 65 10 331 15 00 02 66 11 332 15 00 02 67 08 333 15 00 02 68 02 334 15 00 02 69 0a 335 15 00 02 6a 02 336 15 00 02 6b 02 337 15 00 02 6c 02 338 15 00 02 6d 02 339 15 00 02 6e 02 340 15 00 02 6f 02 341 15 00 02 70 02 342 15 00 02 71 02 343 15 00 02 72 06 344 15 00 02 73 02 345 15 00 02 74 02 346 15 00 02 75 14 347 15 00 02 76 15 348 15 00 02 77 0f 349 15 00 02 78 0e 350 15 00 02 79 0d 351 15 00 02 7a 0c 352 15 00 02 7b 11 353 15 00 02 7c 10 354 15 00 02 7d 06 355 15 00 02 7e 02 356 15 00 02 7f 0a 357 15 00 02 80 02 358 15 00 02 81 02 359 15 00 02 82 02 360 15 00 02 83 02 361 15 00 02 84 02 362 15 00 02 85 02 363 15 00 02 86 02 364 15 00 02 87 02 365 15 00 02 88 08 366 15 00 02 89 02 367 15 00 02 8a 02 368 39 00 04 ff 98 81 04 369 15 00 02 00 80 370 15 00 02 70 00 371 15 00 02 71 00 372 15 00 02 66 fe 373 15 00 02 82 15 374 15 00 02 84 15 375 15 00 02 85 15 376 15 00 02 3a 24 377 15 00 02 32 ac 378 15 00 02 8c 80 379 15 00 02 3c f5 380 15 00 02 88 33 381 39 00 04 ff 98 81 01 382 15 00 02 22 0a 383 15 00 02 31 00 384 15 00 02 53 78 385 15 00 02 55 7b 386 15 00 02 60 20 387 15 00 02 61 00 388 15 00 02 62 0d 389 15 00 02 63 00 390 15 00 02 a0 00 391 15 00 02 a1 10 392 15 00 02 a2 1c 393 15 00 02 a3 13 394 15 00 02 a4 15 395 15 00 02 a5 26 396 15 00 02 a6 1a 397 15 00 02 a7 1d 398 15 00 02 a8 67 399 15 00 02 a9 1c 400 15 00 02 aa 29 401 15 00 02 ab 5b 402 15 00 02 ac 26 403 15 00 02 ad 28 404 15 00 02 ae 5c 405 15 00 02 af 30 406 15 00 02 b0 31 407 15 00 02 b1 32 408 15 00 02 b2 00 409 15 00 02 b1 2e 410 15 00 02 b2 32 411 15 00 02 b3 00 412 15 00 02 c0 00 413 15 00 02 c1 10 414 15 00 02 c2 1c 415 15 00 02 c3 13 416 15 00 02 c4 15 417 15 00 02 c5 26 418 15 00 02 c6 1a 419 15 00 02 c7 1d 420 15 00 02 c8 67 421 15 00 02 c9 1c 422 15 00 02 ca 29 423 15 00 02 cb 5b 424 15 00 02 cc 26 425 15 00 02 cd 28 426 15 00 02 ce 5c 427 15 00 02 cf 30 428 15 00 02 d0 31 429 15 00 02 d1 2e 430 15 00 02 d2 32 431 15 00 02 d3 00 432 39 00 04 ff 98 81 00 433 05 00 01 11 434 05 01 01 29 435 ]; 436 437 display-timings { 438 native-mode = <&timing0>; 439 440 timing0: timing0 { 441 clock-frequency = <65000000>; 442 hactive = <720>; 443 vactive = <1280>; 444 hfront-porch = <48>; 445 hsync-len = <8>; 446 hback-porch = <52>; 447 vfront-porch = <16>; 448 vsync-len = <6>; 449 vback-porch = <15>; 450 hsync-active = <0>; 451 vsync-active = <0>; 452 de-active = <0>; 453 pixelclk-active = <0>; 454 }; 455 }; 456 457 ports { 458 #address-cells = <1>; 459 #size-cells = <0>; 460 461 port@0 { 462 reg = <0>; 463 panel_in_dsi: endpoint { 464 remote-endpoint = <&dsi_out_panel>; 465 }; 466 }; 467 }; 468 }; 469 470 ports { 471 #address-cells = <1>; 472 #size-cells = <0>; 473 474 port@1 { 475 reg = <1>; 476 dsi_out_panel: endpoint { 477 remote-endpoint = <&panel_in_dsi>; 478 }; 479 }; 480 }; 481}; 482 483&csi_dphy0 { 484 status = "okay"; 485 486 ports { 487 #address-cells = <1>; 488 #size-cells = <0>; 489 port@0 { 490 reg = <0>; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 494 mipi_in_ucam0: endpoint@1 { 495 reg = <1>; 496 remote-endpoint = <&ucam_out0>; 497 data-lanes = <1 2 3 4>; 498 }; 499 }; 500 port@1 { 501 reg = <1>; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 505 csidphy0_out: endpoint@0 { 506 reg = <0>; 507 remote-endpoint = <&mipi_csi2_input>; 508 }; 509 }; 510 }; 511}; 512 513&csi_dphy1 { 514 status = "okay"; 515 516 ports { 517 #address-cells = <1>; 518 #size-cells = <0>; 519 520 port@0 { 521 reg = <0>; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 525 csi_dphy1_input: endpoint@1 { 526 reg = <1>; 527 remote-endpoint = <&ucam_out1>; 528 data-lanes = <1 2 3 4>; 529 }; 530 }; 531 532 port@1 { 533 reg = <1>; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 537 csi_dphy1_output: endpoint@0 { 538 reg = <0>; 539 /*remote-endpoint = <&mipi_csi2_input>;*/ 540 data-lanes = <1 2 3 4>; 541 }; 542 }; 543 }; 544}; 545 546&emmc { 547 bus-width = <8>; 548 cap-mmc-highspeed; 549 non-removable; 550 mmc-hs200-1_8v; 551 rockchip,default-sample-phase = <90>; 552 no-sdio; 553 no-sd; 554 /delete-property/ pinctrl-names; 555 /delete-property/ pinctrl-0; 556 status = "okay"; 557}; 558 559&fiq_debugger { 560 status = "okay"; 561}; 562 563&gmac { 564 phy-mode = "rgmii"; 565 clock_in_out = "input"; 566 567 snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>; 568 snps,reset-active-low; 569 /* Reset time is 20ms, 100ms for rtl8211f */ 570 snps,reset-delays-us = <0 20000 100000>; 571 572 assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_ETHERNET_OUT>; 573 assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>; 574 assigned-clock-rates = <125000000>, <0>, <25000000>; 575 576 pinctrl-names = "default"; 577 pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4 &clkm1_out_ethernet>; 578 579 tx_delay = <0x2a>; 580 rx_delay = <0x1a>; 581 582 phy-handle = <&phy>; 583 status = "okay"; 584}; 585 586&i2c0 { 587 status = "okay"; 588 clock-frequency = <400000>; 589 590 rk809: pmic@20 { 591 compatible = "rockchip,rk809"; 592 reg = <0x20>; 593 interrupt-parent = <&gpio0>; 594 interrupts = <9 IRQ_TYPE_LEVEL_LOW>; 595 pinctrl-names = "default", "pmic-sleep", 596 "pmic-power-off", "pmic-reset"; 597 pinctrl-0 = <&pmic_int>; 598 pinctrl-1 = <&soc_slppin_gpio>, <&rk817_slppin_slp>; 599 pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; 600 pinctrl-3 = <&soc_slppin_slp>, <&rk817_slppin_rst>; 601 rockchip,system-power-controller; 602 wakeup-source; 603 #clock-cells = <1>; 604 clock-output-names = "rk808-clkout1", "rk808-clkout2"; 605 /* 0: rst the pmic, 1: rst regs (default in codes) */ 606 pmic-reset-func = <0>; 607 608 vcc1-supply = <&vcc5v0_sys>; 609 vcc2-supply = <&vcc5v0_sys>; 610 vcc3-supply = <&vcc5v0_sys>; 611 vcc4-supply = <&vcc5v0_sys>; 612 vcc5-supply = <&vcc_buck5>; 613 vcc6-supply = <&vcc_buck5>; 614 vcc7-supply = <&vcc5v0_sys>; 615 vcc8-supply = <&vcc3v3_sys>; 616 vcc9-supply = <&vcc5v0_sys>; 617 618 pwrkey { 619 status = "okay"; 620 }; 621 622 pinctrl_rk8xx: pinctrl_rk8xx { 623 gpio-controller; 624 #gpio-cells = <2>; 625 626 /omit-if-no-ref/ 627 rk817_slppin_null: rk817_slppin_null { 628 pins = "gpio_slp"; 629 function = "pin_fun0"; 630 }; 631 632 /omit-if-no-ref/ 633 rk817_slppin_slp: rk817_slppin_slp { 634 pins = "gpio_slp"; 635 function = "pin_fun1"; 636 }; 637 638 /omit-if-no-ref/ 639 rk817_slppin_pwrdn: rk817_slppin_pwrdn { 640 pins = "gpio_slp"; 641 function = "pin_fun2"; 642 }; 643 644 /omit-if-no-ref/ 645 rk817_slppin_rst: rk817_slppin_rst { 646 pins = "gpio_slp"; 647 function = "pin_fun3"; 648 }; 649 }; 650 651 regulators { 652 vdd_logic: DCDC_REG1 { 653 regulator-always-on; 654 regulator-boot-on; 655 regulator-min-microvolt = <725000>; 656 regulator-max-microvolt = <1350000>; 657 regulator-ramp-delay = <6001>; 658 regulator-initial-mode = <0x2>; 659 regulator-name = "vdd_logic"; 660 regulator-state-mem { 661 regulator-on-in-suspend; 662 regulator-suspend-microvolt = <800000>; 663 }; 664 }; 665 666 vdd_arm: DCDC_REG2 { 667 regulator-always-on; 668 regulator-boot-on; 669 regulator-min-microvolt = <725000>; 670 regulator-max-microvolt = <1350000>; 671 regulator-ramp-delay = <6001>; 672 regulator-initial-mode = <0x2>; 673 regulator-name = "vdd_arm"; 674 regulator-state-mem { 675 regulator-off-in-suspend; 676 }; 677 }; 678 679 vcc_ddr: DCDC_REG3 { 680 regulator-always-on; 681 regulator-boot-on; 682 regulator-initial-mode = <0x2>; 683 regulator-name = "vcc_ddr"; 684 regulator-state-mem { 685 regulator-on-in-suspend; 686 }; 687 }; 688 689 vcc3v3_sys: DCDC_REG4 { 690 regulator-always-on; 691 regulator-boot-on; 692 regulator-min-microvolt = <3300000>; 693 regulator-max-microvolt = <3300000>; 694 regulator-initial-mode = <0x2>; 695 regulator-name = "vcc3v3_sys"; 696 regulator-state-mem { 697 regulator-on-in-suspend; 698 regulator-suspend-microvolt = <3300000>; 699 }; 700 }; 701 702 vcc_buck5: DCDC_REG5 { 703 regulator-always-on; 704 regulator-boot-on; 705 regulator-min-microvolt = <2200000>; 706 regulator-max-microvolt = <2200000>; 707 regulator-name = "vcc_buck5"; 708 regulator-state-mem { 709 regulator-on-in-suspend; 710 regulator-suspend-microvolt = <2200000>; 711 }; 712 }; 713 714 vcc_0v8: LDO_REG1 { 715 regulator-always-on; 716 regulator-boot-on; 717 regulator-min-microvolt = <800000>; 718 regulator-max-microvolt = <800000>; 719 regulator-name = "vcc_0v8"; 720 regulator-state-mem { 721 regulator-off-in-suspend; 722 }; 723 }; 724 725 vcc1v8_pmu: LDO_REG2 { 726 regulator-always-on; 727 regulator-boot-on; 728 regulator-min-microvolt = <1800000>; 729 regulator-max-microvolt = <1800000>; 730 regulator-name = "vcc1v8_pmu"; 731 regulator-state-mem { 732 regulator-on-in-suspend; 733 regulator-suspend-microvolt = <1800000>; 734 }; 735 }; 736 737 vdd0v8_pmu: LDO_REG3 { 738 regulator-always-on; 739 regulator-boot-on; 740 regulator-min-microvolt = <800000>; 741 regulator-max-microvolt = <800000>; 742 regulator-name = "vcc0v8_pmu"; 743 regulator-state-mem { 744 regulator-on-in-suspend; 745 regulator-suspend-microvolt = <800000>; 746 }; 747 }; 748 749 vcc_1v8: LDO_REG4 { 750 regulator-always-on; 751 regulator-boot-on; 752 regulator-min-microvolt = <1800000>; 753 regulator-max-microvolt = <1800000>; 754 regulator-name = "vcc_1v8"; 755 regulator-state-mem { 756 regulator-on-in-suspend; 757 regulator-suspend-microvolt = <1800000>; 758 }; 759 }; 760 761 vcc_dovdd: LDO_REG5 { 762 regulator-boot-on; 763 regulator-min-microvolt = <1800000>; 764 regulator-max-microvolt = <1800000>; 765 regulator-name = "vcc_dovdd"; 766 regulator-state-mem { 767 regulator-off-in-suspend; 768 }; 769 }; 770 771 vcc_dvdd: LDO_REG6 { 772 regulator-min-microvolt = <1200000>; 773 regulator-max-microvolt = <1200000>; 774 regulator-name = "vcc_dvdd"; 775 regulator-state-mem { 776 regulator-off-in-suspend; 777 }; 778 }; 779 780 vcc_avdd: LDO_REG7 { 781 regulator-min-microvolt = <2800000>; 782 regulator-max-microvolt = <2800000>; 783 regulator-name = "vcc_avdd"; 784 regulator-state-mem { 785 regulator-off-in-suspend; 786 }; 787 }; 788 789 vccio_sd: LDO_REG8 { 790 regulator-always-on; 791 regulator-boot-on; 792 regulator-min-microvolt = <1800000>; 793 regulator-max-microvolt = <3300000>; 794 regulator-name = "vccio_sd"; 795 regulator-state-mem { 796 regulator-off-in-suspend; 797 }; 798 }; 799 800 vcc3v3_sd: LDO_REG9 { 801 regulator-always-on; 802 regulator-boot-on; 803 regulator-min-microvolt = <3300000>; 804 regulator-max-microvolt = <3300000>; 805 regulator-name = "vcc3v3_sd"; 806 regulator-state-mem { 807 regulator-off-in-suspend; 808 }; 809 }; 810 811 vcc5v0_host: SWITCH_REG1 { 812 regulator-name = "vcc5v0_host"; 813 }; 814 815 vcc_3v3: SWITCH_REG2 { 816 regulator-always-on; 817 regulator-boot-on; 818 regulator-name = "vcc_3v3"; 819 }; 820 }; 821 822 rk809_codec: codec { 823 #sound-dai-cells = <0>; 824 compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; 825 clocks = <&cru MCLK_I2S0_TX_OUT2IO>; 826 clock-names = "mclk"; 827 pinctrl-names = "default"; 828 assigned-clocks = <&cru MCLK_I2S0_TX_OUT2IO>; 829 assigned-clock-parents = <&cru MCLK_I2S0_TX>; 830 pinctrl-0 = <&i2s0m0_mclk>; 831 hp-volume = <20>; 832 spk-volume = <3>; 833 }; 834 }; 835}; 836 837&i2c1 { 838 status = "okay"; 839 clock-frequency = <400000>; 840 841 ar0230: ar0230@10 { 842 compatible = "aptina,ar0230"; 843 reg = <0x10>; 844 clocks = <&cru CLK_CIF_OUT>; 845 clock-names = "xvclk"; 846 avdd-supply = <&vcc_avdd>; 847 dovdd-supply = <&vcc_dovdd>; 848 dvdd-supply = <&vcc_dvdd>; 849 power-domains = <&power RV1126_PD_VI>; 850 pwdn-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; 851 /*reset-gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;*/ 852 rockchip,grf = <&grf>; 853 pinctrl-names = "default"; 854 pinctrl-0 = <&cifm0_dvp_ctl>; 855 rockchip,camera-module-index = <0>; 856 rockchip,camera-module-facing = "back"; 857 rockchip,camera-module-name = "CMK-OT0836-PT2"; 858 rockchip,camera-module-lens-name = "YT-2929"; 859 port { 860 cam_para_out1: endpoint { 861 /* remote-endpoint = <&cif_para_in>; */ 862 }; 863 }; 864 }; 865 866 ov4689: ov4689@36 { 867 compatible = "ovti,ov4689"; 868 reg = <0x36>; 869 clocks = <&cru CLK_MIPICSI_OUT>; 870 clock-names = "xvclk"; 871 power-domains = <&power RV1126_PD_VI>; 872 pinctrl-names = "rockchip,camera_default"; 873 pinctrl-0 = <&mipicsi_clk1>; 874 /*pinctrl-0 = <&mipicsi_clk0>;*/ 875 avdd-supply = <&vcc_avdd>; 876 dovdd-supply = <&vcc_dovdd>; 877 dvdd-supply = <&vcc_dvdd>; 878 pwdn-gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_HIGH>; 879 /*pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;*/ 880 rockchip,camera-module-index = <1>; 881 rockchip,camera-module-facing = "front"; 882 rockchip,camera-module-name = "JSD3425-C1"; 883 rockchip,camera-module-lens-name = "JSD3425-C1"; 884 /* NO_HDR:0 HDR_X2:5 HDR_X3:6 */ 885 rockchip,camera-hdr-mode = <0>; 886 port { 887 ucam_out1: endpoint { 888 remote-endpoint = <&csi_dphy1_input>; 889 data-lanes = <1 2 3 4>; 890 }; 891 }; 892 893 }; 894 895 os04a10: os04a10@36 { 896 compatible = "ovti,os04a10"; 897 reg = <0x36>; 898 clocks = <&cru CLK_MIPICSI_OUT>; 899 clock-names = "xvclk"; 900 power-domains = <&power RV1126_PD_VI>; 901 pinctrl-names = "rockchip,camera_default"; 902 pinctrl-0 = <&mipicsi_clk0>; 903 avdd-supply = <&vcc_avdd>; 904 dovdd-supply = <&vcc_dovdd>; 905 dvdd-supply = <&vcc_dvdd>; 906 pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; 907 rockchip,camera-module-index = <1>; 908 rockchip,camera-module-facing = "front"; 909 rockchip,camera-module-name = "CMK-OT1607-FV1"; 910 rockchip,camera-module-lens-name = "M12-40IRC-4MP-F16"; 911 ir-cut = <&cam_ircut0>; 912 port { 913 ucam_out0: endpoint { 914 remote-endpoint = <&mipi_in_ucam0>; 915 data-lanes = <1 2 3 4>; 916 }; 917 }; 918 }; 919}; 920 921&i2c5 { 922 status = "okay"; 923 clock-frequency = <400000>; 924 925 gt1x: gt1x@14 { 926 compatible = "goodix,gt1x"; 927 reg = <0x14>; 928 gtp_ics_slot_report; 929 power-supply = <&vcc18_lcd_n>; 930 goodix,rst-gpio = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>; 931 goodix,irq-gpio = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>; 932 }; 933}; 934 935&i2s0_8ch { 936 status = "okay"; 937 #sound-dai-cells = <0>; 938 rockchip,clk-trcm = <1>; 939 rockchip,i2s-rx-route = <3 1 2 0>; 940 pinctrl-names = "default"; 941 pinctrl-0 = <&i2s0m0_sclk_tx 942 &i2s0m0_lrck_tx 943 &i2s0m0_sdo0 944 &i2s0m0_sdo1_sdi3>; 945}; 946 947&iep { 948 status = "okay"; 949}; 950 951&iep_mmu { 952 status = "okay"; 953}; 954 955&mdio { 956 phy: phy@0 { 957 compatible = "ethernet-phy-ieee802.3-c22"; 958 reg = <0x0>; 959 clocks = <&cru CLK_GMAC_ETHERNET_OUT>; 960 }; 961}; 962 963&mipi_csi2 { 964 status = "okay"; 965 966 ports { 967 #address-cells = <1>; 968 #size-cells = <0>; 969 970 port@0 { 971 reg = <0>; 972 #address-cells = <1>; 973 #size-cells = <0>; 974 975 mipi_csi2_input: endpoint@1 { 976 reg = <1>; 977 remote-endpoint = <&csidphy0_out>; 978 data-lanes = <1 2 3 4>; 979 }; 980 }; 981 982 port@1 { 983 reg = <1>; 984 #address-cells = <1>; 985 #size-cells = <0>; 986 987 mipi_csi2_output: endpoint@0 { 988 reg = <0>; 989 remote-endpoint = <&cif_mipi_in>; 990 data-lanes = <1 2 3 4>; 991 }; 992 }; 993 }; 994}; 995 996&mipi_dphy { 997 status = "okay"; 998}; 999 1000&mpp_srv { 1001 status = "okay"; 1002}; 1003 1004&nandc { 1005 /delete-property/ pinctrl-names; 1006 /delete-property/ pinctrl-0; 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 1010 nand@0 { 1011 reg = <0>; 1012 nand-bus-width = <8>; 1013 nand-ecc-mode = "hw"; 1014 nand-ecc-strength = <16>; 1015 nand-ecc-step-size = <1024>; 1016 }; 1017}; 1018 1019&npu { 1020 npu-supply = <&vdd_npu>; 1021 status = "okay"; 1022}; 1023 1024&npu_tsadc { 1025 status = "okay"; 1026}; 1027 1028&optee { 1029 status = "disabled"; 1030}; 1031 1032&otp { 1033 status = "okay"; 1034}; 1035 1036&pdm { 1037 status = "disabled"; 1038 #sound-dai-cells = <0>; 1039 pinctrl-names = "default"; 1040 pinctrl-0 = <&pdmm0_clk 1041 &pdmm0_clk1 1042 &pdmm0_sdi0 1043 &pdmm0_sdi1 1044 &pdmm0_sdi2>; 1045}; 1046 1047&pinctrl { 1048 pmic { 1049 /omit-if-no-ref/ 1050 pmic_int: pmic_int { 1051 rockchip,pins = 1052 <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; 1053 }; 1054 1055 /omit-if-no-ref/ 1056 soc_slppin_gpio: soc_slppin_gpio { 1057 rockchip,pins = 1058 <0 RK_PB2 RK_FUNC_GPIO &pcfg_output_low>; 1059 }; 1060 1061 /omit-if-no-ref/ 1062 soc_slppin_slp: soc_slppin_slp { 1063 rockchip,pins = 1064 <0 RK_PB2 1 &pcfg_pull_none>; 1065 }; 1066 1067 /omit-if-no-ref/ 1068 soc_slppin_rst: soc_slppin_rst { 1069 rockchip,pins = 1070 <0 RK_PB2 2 &pcfg_pull_none>; 1071 }; 1072 }; 1073 1074 sdio-pwrseq { 1075 /omit-if-no-ref/ 1076 wifi_enable_h: wifi-enable-h { 1077 rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1078 }; 1079 }; 1080 1081 wireless-wlan { 1082 /omit-if-no-ref/ 1083 wifi_wake_host: wifi-wake-host { 1084 rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; 1085 }; 1086 }; 1087}; 1088 1089&pmu_io_domains { 1090 status = "okay"; 1091 1092 pmuio0-supply = <&vcc1v8_pmu>; 1093 pmuio1-supply = <&vcc3v3_sys>; 1094 vccio2-supply = <&vccio_sd>; 1095 vccio3-supply = <&vcc_1v8>; 1096 vccio4-supply = <&vcc_1v8>; 1097 vccio5-supply = <&vcc_3v3>; 1098 vccio6-supply = <&vcc_1v8>; 1099 vccio7-supply = <&vcc_1v8>; 1100}; 1101 1102&pwm0 { 1103 status = "okay"; 1104 pinctrl-names = "active"; 1105 pinctrl-0 = <&pwm0m0_pins_pull_down>; 1106}; 1107 1108&pwm1 { 1109 status = "okay"; 1110 pinctrl-names = "active"; 1111 pinctrl-0 = <&pwm1m0_pins_pull_down>; 1112}; 1113 1114&pwm3 { 1115 status = "okay"; 1116}; 1117 1118&ramoops { 1119 status = "okay"; 1120}; 1121 1122&rk_rga { 1123 status = "okay"; 1124}; 1125 1126&rkcif { 1127 status = "okay"; 1128}; 1129 1130&rkcif_mmu { 1131 status = "disabled"; 1132}; 1133 1134&rkcif_dvp { 1135 status = "okay"; 1136 1137 port { 1138 /* Parallel bus endpoint */ 1139 /* 1140 cif_para_in: endpoint { 1141 remote-endpoint = <&cam_para_out1>; 1142 bus-width = <12>; 1143 hsync-active = <1>; 1144 vsync-active = <0>; 1145 }; 1146 */ 1147 }; 1148}; 1149 1150&rkcif_mipi_lvds { 1151 status = "okay"; 1152 1153 port { 1154 /* MIPI CSI-2 endpoint */ 1155 cif_mipi_in: endpoint { 1156 remote-endpoint = <&mipi_csi2_output>; 1157 data-lanes = <1 2 3 4>; 1158 }; 1159 }; 1160}; 1161 1162&rkcif_mipi_lvds_sditf { 1163 status = "okay"; 1164 1165 port { 1166 /* MIPI CSI-2 endpoint */ 1167 mipi_lvds_sditf: endpoint { 1168 remote-endpoint = <&isp_in>; 1169 data-lanes = <1 2 3 4>; 1170 }; 1171 }; 1172}; 1173 1174&rkisp { 1175 status = "okay"; 1176}; 1177 1178&rkisp_vir0 { 1179 status = "okay"; 1180 1181 ports { 1182 port@0 { 1183 reg = <0>; 1184 #address-cells = <1>; 1185 #size-cells = <0>; 1186 1187 isp_in: endpoint@0 { 1188 reg = <0>; 1189 remote-endpoint = <&mipi_lvds_sditf>; 1190 }; 1191 }; 1192 }; 1193}; 1194 1195&rkisp_mmu { 1196 status = "disabled"; 1197}; 1198 1199&rkispp { 1200 status = "okay"; 1201 /* the max input w h and fps of mulit sensor */ 1202 //max-input = <2688 1520 30>; 1203}; 1204 1205&rkispp_vir0 { 1206 status = "okay"; 1207}; 1208 1209&rkispp_mmu { 1210 status = "okay"; 1211}; 1212 1213&rkvdec { 1214 status = "okay"; 1215}; 1216 1217&rkvdec_mmu { 1218 status = "okay"; 1219}; 1220 1221&rkvenc { 1222 venc-supply = <&vdd_vepu>; 1223 status = "okay"; 1224}; 1225 1226&rkvenc_mmu { 1227 status = "okay"; 1228}; 1229 1230&rng { 1231 status = "okay"; 1232}; 1233 1234&rockchip_suspend { 1235 status = "okay"; 1236 rockchip,sleep-debug-en = <1>; 1237 rockchip,sleep-mode-config = < 1238 (0 1239 | RKPM_SLP_ARMOFF 1240 | RKPM_SLP_PMU_PMUALIVE_32K 1241 | RKPM_SLP_PMU_DIS_OSC 1242 | RKPM_SLP_PMIC_LP 1243 ) 1244 >; 1245 rockchip,wakeup-config = < 1246 (0 1247 | RKPM_GPIO_WKUP_EN 1248 ) 1249 >; 1250}; 1251 1252&route_dsi { 1253 status = "okay"; 1254}; 1255 1256&saradc { 1257 status = "okay"; 1258 vref-supply = <&vcc_1v8>; 1259}; 1260 1261&sdmmc { 1262 bus-width = <4>; 1263 cap-mmc-highspeed; 1264 cap-sd-highspeed; 1265 card-detect-delay = <200>; 1266 rockchip,default-sample-phase = <90>; 1267 no-sdio; 1268 no-mmc; 1269 sd-uhs-sdr12; 1270 sd-uhs-sdr25; 1271 sd-uhs-sdr104; 1272 vqmmc-supply = <&vccio_sd>; 1273 vmmc-supply = <&vcc3v3_sd>; 1274 status = "okay"; 1275}; 1276 1277&sdio { 1278 max-frequency = <200000000>; 1279 bus-width = <4>; 1280 cap-sd-highspeed; 1281 cap-sdio-irq; 1282 keep-power-in-suspend; 1283 non-removable; 1284 rockchip,default-sample-phase = <90>; 1285 sd-uhs-sdr104; 1286 no-sd; 1287 no-mmc; 1288 mmc-pwrseq = <&sdio_pwrseq>; 1289 status = "okay"; 1290}; 1291 1292&sfc { 1293 /delete-property/ pinctrl-names; 1294 /delete-property/ pinctrl-0; 1295 status = "okay"; 1296 1297 flash@0 { 1298 compatible = "spi-nand"; 1299 reg = <0>; 1300 spi-max-frequency = <80000000>; 1301 spi-rx-bus-width = <4>; 1302 spi-tx-bus-width = <1>; 1303 }; 1304}; 1305 1306&u2phy0 { 1307 status = "okay"; 1308 vup-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_LOW>; 1309 u2phy_otg: otg-port { 1310 status = "okay"; 1311 }; 1312}; 1313 1314&u2phy1 { 1315 status = "okay"; 1316 u2phy_host: host-port { 1317 status = "okay"; 1318 phy-supply = <&vcc5v0_host>; 1319 }; 1320}; 1321 1322&uart0 { 1323 pinctrl-names = "default"; 1324 pinctrl-0 = <&uart0_xfer &uart0_ctsn>; 1325 status = "okay"; 1326}; 1327 1328&usb_host0_ehci { 1329 status = "okay"; 1330}; 1331 1332&usb_host0_ohci { 1333 status = "okay"; 1334}; 1335 1336&usbdrd { 1337 status = "okay"; 1338}; 1339 1340&usbdrd_dwc3 { 1341 status = "okay"; 1342 extcon = <&u2phy0>; 1343}; 1344 1345&vdpu { 1346 status = "okay"; 1347}; 1348 1349&vepu { 1350 status = "okay"; 1351}; 1352 1353&vpu_mmu { 1354 status = "okay"; 1355}; 1356 1357&vop { 1358 status = "okay"; 1359}; 1360 1361&vop_mmu { 1362 status = "okay"; 1363}; 1364