1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4 */ 5 6/dts-v1/; 7#include "rv1126.dtsi" 8#include "rv1126-ipc.dtsi" 9#include <dt-bindings/input/input.h> 10 11/ { 12 model = "Rockchip RV1126 38x38 V10 EMMC DDR3 Board"; 13 compatible = "rockchip,rv1126-38x38-v10-emmc", "rockchip,rv1126"; 14 15 chosen { 16 bootargs = "earlycon=uart8250,mmio32,0xff570000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootfstype=squashfs rootwait snd_aloop.index=7"; 17 }; 18 19 /delete-node/ vdd-npu; 20 /delete-node/ vdd-vepu; 21 22 vcc_1v8: vcc-1v8 { 23 compatible = "regulator-fixed"; 24 regulator-name = "vcc_1v8"; 25 regulator-always-on; 26 regulator-boot-on; 27 regulator-min-microvolt = <1800000>; 28 regulator-max-microvolt = <1800000>; 29 }; 30 31 vcc_dvdd: vcc-dvdd { 32 compatible = "regulator-fixed"; 33 regulator-name = "vcc_dvdd"; 34 regulator-always-on; 35 regulator-boot-on; 36 regulator-min-microvolt = <1200000>; 37 regulator-max-microvolt = <1200000>; 38 }; 39 40 vcc3v3_sys: vcc33sys { 41 compatible = "regulator-fixed"; 42 regulator-name = "vcc3v3_sys"; 43 regulator-always-on; 44 regulator-boot-on; 45 regulator-min-microvolt = <3300000>; 46 regulator-max-microvolt = <3300000>; 47 }; 48 49 vcc_sd: vcc-sd { 50 compatible = "regulator-fixed"; 51 gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; 52 pinctrl-0 = <&sdmmc_pwr>; 53 pinctrl-names = "default"; 54 regulator-name = "vcc_sd"; 55 regulator-min-microvolt = <3300000>; 56 regulator-max-microvolt = <3300000>; 57 startup-delay-us = <100000>; 58 vin-supply = <&vcc3v3_sys>; 59 enable-active-high; 60 }; 61 62 vdd_arm: vdd-arm { 63 compatible = "pwm-regulator"; 64 pwms = <&pwm0 0 5000 1>; 65 regulator-name = "vdd_arm"; 66 regulator-min-microvolt = <720000>; 67 regulator-max-microvolt = <1000000>; 68 regulator-init-microvolt = <825000>; 69 regulator-always-on; 70 regulator-boot-on; 71 regulator-settling-time-up-us = <250>; 72 pwm-supply = <&vcc3v3_sys>; 73 status = "okay"; 74 }; 75 76 /* 77 * pwm1 is reserved as voltage adjustment in hardware 78 * use fixed regulator to avoid voltage adjustment by software 79 */ 80 vdd_logic_npu_vepu: vdd-logic-npu-vepu { 81 compatible = "pwm-regulator"; 82 pwms = <&pwm1 0 5000 1>; 83 regulator-name = "vdd_logic_npu_vepu"; 84 regulator-min-microvolt = <720000>; 85 regulator-max-microvolt = <880000>; 86 regulator-init-microvolt = <825000>; 87 regulator-always-on; 88 regulator-boot-on; 89 regulator-settling-time-up-us = <250>; 90 pwm-supply = <&vcc3v3_sys>; 91 status = "okay"; 92 }; 93 94 vdd_logic_npu_vepu_fixed: vdd-logic-npu-vepu-fixed { 95 compatible = "regulator-fixed"; 96 regulator-name = "vdd_logic_npu_vepu-fixed"; 97 regulator-always-on; 98 regulator-boot-on; 99 regulator-min-microvolt = <825000>; 100 regulator-max-microvolt = <825000>; 101 }; 102 103 adc-keys { 104 compatible = "adc-keys"; 105 io-channels = <&saradc 0>; 106 io-channel-names = "buttons"; 107 poll-interval = <100>; 108 keyup-threshold-microvolt = <1800000>; 109 110 esc-key { 111 label = "esc"; 112 linux,code = <KEY_ESC>; 113 press-threshold-microvolt = <0>; 114 }; 115 }; 116 117 cam_ircut0: cam_ircut { 118 status = "okay"; 119 compatible = "rockchip,ircut"; 120 ircut-open-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; 121 ircut-close-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; 122 rockchip,camera-module-index = <1>; 123 rockchip,camera-module-facing = "front"; 124 }; 125 126 flash_ir: flash-ir { 127 status = "okay"; 128 compatible = "led,rgb13h"; 129 label = "pwm-flash-ir"; 130 led-max-microamp = <20000>; 131 flash-max-microamp = <20000>; 132 flash-max-timeout-us = <1000000>; 133 pwms=<&pwm3 0 25000 0>; 134 rockchip,camera-module-index = <1>; 135 rockchip,camera-module-facing = "front"; 136 }; 137 138 i2s0_sound: i2s0-sound { 139 status = "okay"; 140 compatible = "simple-audio-card"; 141 simple-audio-card,format = "i2s"; 142 simple-audio-card,mclk-fs = <256>; 143 simple-audio-card,name = "rockchip,i2s0-sound"; 144 simple-audio-card,cpu { 145 sound-dai = <&i2s0_8ch>; 146 }; 147 simple-audio-card,codec { 148 sound-dai = <&es8311>; 149 }; 150 }; 151 152 wireless_wlan: wireless-wlan { 153 compatible = "wlan-platdata"; 154 rockchip,grf = <&grf>; 155 wifi_chip_type = "USB-WiFi"; 156 WIFI,poweren_gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; 157 status = "okay"; 158 }; 159}; 160 161&csi_dphy0 { 162 status = "okay"; 163 164 ports { 165 #address-cells = <1>; 166 #size-cells = <0>; 167 port@0 { 168 reg = <0>; 169 #address-cells = <1>; 170 #size-cells = <0>; 171 172 mipi_in_ucam0: endpoint@1 { 173 reg = <1>; 174 remote-endpoint = <&ucam_out0>; 175 data-lanes = <1 2 3 4>; 176 }; 177 }; 178 port@1 { 179 reg = <1>; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 183 csidphy0_out: endpoint@0 { 184 reg = <0>; 185 remote-endpoint = <&mipi_csi2_input>; 186 }; 187 }; 188 }; 189}; 190 191&emmc { 192 bus-width = <8>; 193 cap-mmc-highspeed; 194 non-removable; 195 mmc-hs200-1_8v; 196 rockchip,default-sample-phase = <90>; 197 no-sdio; 198 no-sd; 199 /delete-property/ pinctrl-names; 200 /delete-property/ pinctrl-0; 201 status = "okay"; 202}; 203 204&gmac { 205 phy-mode = "rmii"; 206 clock_in_out = "output"; 207 208 snps,reset-gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>; 209 snps,reset-active-low; 210 snps,reset-delays-us = <0 50000 10000>; 211 212 assigned-clocks = <&cru CLK_GMAC_SRC_M0>, <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>; 213 assigned-clock-rates = <0>, <50000000>; 214 assigned-clock-parents = <&cru CLK_GMAC_RGMII_M0>, <&cru CLK_GMAC_SRC_M0>, <&cru RMII_MODE_CLK>; 215 216 pinctrl-names = "default"; 217 pinctrl-0 = <&rmiim0_miim &rgmiim0_rxer &rmiim0_bus2 &rgmiim0_mclkinout>; 218 219 phy-handle = <&phy>; 220 status = "okay"; 221}; 222 223&i2c0 { 224 status = "okay"; 225 226 pcf8563: pcf8563@51 { 227 compatible = "pcf8563"; 228 reg = <0x51>; 229 #clock-cells = <0>; 230 clock-frequency = <32768>; 231 clock-output-names = "xin32k"; 232 }; 233}; 234 235&i2c1 { 236 status = "okay"; 237 clock-frequency = <400000>; 238 239 imx415: imx415@1a { 240 compatible = "sony,imx415"; 241 reg = <0x1a>; 242 clocks = <&cru CLK_MIPICSI_OUT>; 243 clock-names = "xvclk"; 244 power-domains = <&power RV1126_PD_VI>; 245 pinctrl-names = "rockchip,camera_default"; 246 pinctrl-0 = <&mipicsi_clk0>; 247 avdd-supply = <&vcc3v3_sys>; 248 dovdd-supply = <&vcc_1v8>; 249 dvdd-supply = <&vcc_dvdd>; 250 /* reset is always pulled high in v10 */ 251 reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; 252 rockchip,camera-module-index = <1>; 253 rockchip,camera-module-facing = "front"; 254 rockchip,camera-module-name = "YT10092"; 255 rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; 256 ir-cut = <&cam_ircut0>; 257 flash-leds = <&flash_ir>; 258 port { 259 ucam_out0: endpoint { 260 remote-endpoint = <&mipi_in_ucam0>; 261 data-lanes = <1 2 3 4>; 262 }; 263 }; 264 }; 265 266}; 267 268&i2c4 { 269 status = "okay"; 270 clock-frequency = <400000>; 271 pinctrl-0 = <&i2c4m1_xfer>; 272 273 es8311: es8311@18 { 274 compatible = "everest,es8311"; 275 reg = <0x18>; 276 clocks = <&cru MCLK_I2S0_TX_OUT2IO>; 277 clock-names = "mclk"; 278 adc-volume = <0xbf>; /* 0dB */ 279 dac-volume = <0xbf>; /* 0dB */ 280 aec-mode = "dac left, adc right"; 281 pinctrl-names = "default"; 282 pinctrl-0 = <&i2s0m0_mclk &spk_ctl>; 283 assigned-clocks = <&cru MCLK_I2S0_TX_OUT2IO>; 284 assigned-clock-parents = <&cru MCLK_I2S0_TX>; 285 spk-ctl-gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>; 286 #sound-dai-cells = <0>; 287 }; 288}; 289 290&i2s0_8ch { 291 status = "okay"; 292 rockchip,clk-trcm = <1>; 293 #sound-dai-cells = <0>; 294 pinctrl-0 = <&i2s0m0_sclk_tx 295 &i2s0m0_lrck_tx 296 &i2s0m0_sdi0 297 &i2s0m0_sdo0>; 298}; 299 300&isp_reserved { 301 size = <0x20000000>; 302}; 303 304&mdio { 305 phy: phy@1 { 306 compatible = "ethernet-phy-ieee802.3-c22"; 307 reg = <0x1>; 308 }; 309}; 310 311&mipi_csi2 { 312 status = "okay"; 313 314 ports { 315 #address-cells = <1>; 316 #size-cells = <0>; 317 318 port@0 { 319 reg = <0>; 320 #address-cells = <1>; 321 #size-cells = <0>; 322 323 mipi_csi2_input: endpoint@1 { 324 reg = <1>; 325 remote-endpoint = <&csidphy0_out>; 326 data-lanes = <1 2 3 4>; 327 }; 328 }; 329 330 port@1 { 331 reg = <1>; 332 #address-cells = <1>; 333 #size-cells = <0>; 334 335 mipi_csi2_output: endpoint@0 { 336 reg = <0>; 337 remote-endpoint = <&cif_mipi_in>; 338 data-lanes = <1 2 3 4>; 339 }; 340 }; 341 }; 342}; 343 344&npu { 345 npu-supply = <&vdd_logic_npu_vepu_fixed>; 346}; 347 348&npu_opp_table { 349 /delete-node/ opp-800000000; 350 /delete-node/ opp-934000000; 351}; 352 353&pinctrl { 354 es8311 { 355 spk_ctl: spk-ctl { 356 rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 357 }; 358 }; 359 360 sdmmc-pwr { 361 /omit-if-no-ref/ 362 sdmmc_pwr: sdmmc-pwr { 363 rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 364 }; 365 }; 366}; 367 368&pmu_io_domains { 369 status = "okay"; 370 371 pmuio0-supply = <&vcc3v3_sys>; 372 pmuio1-supply = <&vcc3v3_sys>; 373 vccio2-supply = <&vcc3v3_sys>; 374 vccio3-supply = <&vcc3v3_sys>; 375 vccio4-supply = <&vcc_1v8>; 376 vccio5-supply = <&vcc3v3_sys>; 377 vccio6-supply = <&vcc3v3_sys>; 378 vccio7-supply = <&vcc3v3_sys>; 379}; 380 381&pwm3 { 382 status = "okay"; 383 pinctrl-names = "active"; 384 pinctrl-0 = <&pwm3m0_pins_pull_down>; 385}; 386 387&rkcif { 388 status = "okay"; 389}; 390 391&rkcif_mmu { 392 status = "disabled"; 393}; 394 395&rkcif_mipi_lvds { 396 status = "okay"; 397 398 port { 399 /* MIPI CSI-2 endpoint */ 400 cif_mipi_in: endpoint { 401 remote-endpoint = <&mipi_csi2_output>; 402 data-lanes = <1 2 3 4>; 403 }; 404 }; 405}; 406 407&rkcif_mipi_lvds_sditf { 408 status = "okay"; 409 410 port { 411 /* MIPI CSI-2 endpoint */ 412 mipi_lvds_sditf: endpoint { 413 remote-endpoint = <&isp_in>; 414 data-lanes = <1 2 3 4>; 415 }; 416 }; 417}; 418 419&rkisp_vir0 { 420 status = "okay"; 421 422 ports { 423 port@0 { 424 reg = <0>; 425 #address-cells = <1>; 426 #size-cells = <0>; 427 428 isp_in: endpoint@0 { 429 reg = <0>; 430 remote-endpoint = <&mipi_lvds_sditf>; 431 }; 432 }; 433 }; 434}; 435 436&rkvenc { 437 venc-supply = <&vdd_logic_npu_vepu_fixed>; 438}; 439 440&rockchip_suspend { 441 status = "okay"; 442 rockchip,sleep-debug-en = <1>; 443 rockchip,sleep-mode-config = < 444 (0 445 | RKPM_SLP_ARMOFF 446 | RKPM_SLP_PMU_PMUALIVE_32K 447 | RKPM_SLP_PMU_DIS_OSC 448 ) 449 >; 450}; 451 452&saradc { 453 status = "okay"; 454 vref-supply = <&vcc_1v8>; 455}; 456 457&sdmmc0_bus4 { 458 rockchip,pins = 459 /* sdmmc0_d0 */ 460 <1 RK_PA4 1 &pcfg_pull_up_drv_level_0>, 461 /* sdmmc0_d1 */ 462 <1 RK_PA5 1 &pcfg_pull_up_drv_level_0>, 463 /* sdmmc0_d2 */ 464 <1 RK_PA6 1 &pcfg_pull_up_drv_level_0>, 465 /* sdmmc0_d3 */ 466 <1 RK_PA7 1 &pcfg_pull_up_drv_level_0>; 467}; 468 469&sdmmc0_clk { 470 rockchip,pins = 471 /* sdmmc0_clk */ 472 <1 RK_PB0 1 &pcfg_pull_up_drv_level_3>; 473}; 474 475&sdmmc0_cmd { 476 rockchip,pins = 477 /* sdmmc0_cmd */ 478 <1 RK_PB1 1 &pcfg_pull_up_drv_level_0>; 479}; 480 481&sdmmc { 482 bus-width = <4>; 483 cap-mmc-highspeed; 484 cap-sd-highspeed; 485 card-detect-delay = <200>; 486 rockchip,default-sample-phase = <90>; 487 no-sdio; 488 no-mmc; 489 status = "okay"; 490 vmmc-supply = <&vcc_sd>; 491}; 492 493&soc_crit { 494 /* millicelsius */ 495 temperature = <125000>; 496}; 497 498&u2phy1 { 499 status = "okay"; 500 u2phy_host: host-port { 501 status = "okay"; 502 }; 503}; 504 505&uart3 { 506 wakeup-source; 507 pinctrl-names = "default"; 508 pinctrl-0 = <&uart3m2_xfer &uart3m2_ctsn &uart3m2_rtsn>; 509 status = "okay"; 510}; 511 512&usb_host0_ehci { 513 status = "okay"; 514}; 515 516&usb_host0_ohci { 517 status = "okay"; 518}; 519 520&wdt { 521 status = "okay"; 522}; 523