1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 */ 5 6/dts-v1/; 7 8#include "rv1106.dtsi" 9#include "rv1106-evb-v10.dtsi" 10#include "rv1106-thunder-boot-spi-nor.dtsi" 11 12/ { 13 model = "Rockchip RV1106G EVB2 V10 Board"; 14 compatible = "rockchip,rv1106g-evb2-v10", "rockchip,rv1106"; 15 16 chosen { 17 bootargs = "loglevel=0 rootfstype=erofs rootflags=dax console=ttyFIQ0 root=/dev/rd0 snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0 driver_async_probe=dwmmc_rockchip"; 18 }; 19 20 vcc_1v8: vcc-1v8 { 21 compatible = "regulator-fixed"; 22 regulator-name = "vcc_1v8"; 23 regulator-always-on; 24 regulator-boot-on; 25 regulator-min-microvolt = <1800000>; 26 regulator-max-microvolt = <1800000>; 27 }; 28 29 vcc_3v3: vcc-3v3 { 30 compatible = "regulator-fixed"; 31 regulator-name = "vcc_3v3"; 32 regulator-always-on; 33 regulator-boot-on; 34 regulator-min-microvolt = <3300000>; 35 regulator-max-microvolt = <3300000>; 36 }; 37 38 vcc3v3_sd: vcc3v3-sd { 39 compatible = "regulator-fixed"; 40 gpio = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>; 41 regulator-name = "vcc3v3_sd"; 42 regulator-min-microvolt = <3300000>; 43 regulator-max-microvolt = <3300000>; 44 pinctrl-names = "default"; 45 pinctrl-0 = <&sdmmc_pwren>; 46 }; 47 48 wireless_wlan: wireless-wlan { 49 compatible = "wlan-platdata"; 50 WIFI,host_wake_irq = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; 51 status = "okay"; 52 }; 53}; 54 55&csi2_dphy_hw { 56 status = "okay"; 57}; 58 59&csi2_dphy0 { 60 status = "okay"; 61 62 ports { 63 #address-cells = <1>; 64 #size-cells = <0>; 65 66 port@0 { 67 reg = <0>; 68 #address-cells = <1>; 69 #size-cells = <0>; 70 71 csi_dphy_input0: endpoint@0 { 72 reg = <0>; 73 remote-endpoint = <&sc3338_out>; 74 data-lanes = <1 2>; 75 }; 76 }; 77 78 port@1 { 79 reg = <1>; 80 #address-cells = <1>; 81 #size-cells = <0>; 82 83 csi_dphy_output: endpoint@0 { 84 reg = <0>; 85 remote-endpoint = <&mipi_csi2_input>; 86 }; 87 }; 88 }; 89}; 90 91&emmc { 92 status = "disabled"; 93}; 94 95&fiq_debugger { 96 rockchip,baudrate = <1500000>; 97 pinctrl-names = "default"; 98 pinctrl-0 = <&uart2m1_xfer>; 99}; 100 101&i2c4 { 102 rockchip,amp-shared; 103 104 sc3338: sc3338@30 { 105 compatible = "smartsens,sc3338"; 106 status = "okay"; 107 reg = <0x30>; 108 clocks = <&cru MCLK_REF_MIPI0>; 109 clock-names = "xvclk"; 110 pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; 111 pinctrl-names = "default"; 112 pinctrl-0 = <&mipi_refclk_out0>; 113 rockchip,camera-module-index = <0>; 114 rockchip,camera-module-facing = "back"; 115 rockchip,camera-module-name = "FKO1"; 116 rockchip,camera-module-lens-name = "30IRC-F16"; 117 port { 118 sc3338_out: endpoint { 119 remote-endpoint = <&csi_dphy_input0>; 120 data-lanes = <1 2>; 121 }; 122 }; 123 }; 124}; 125 126&mipi0_csi2 { 127 status = "okay"; 128 129 ports { 130 #address-cells = <1>; 131 #size-cells = <0>; 132 133 port@0 { 134 reg = <0>; 135 #address-cells = <1>; 136 #size-cells = <0>; 137 138 mipi_csi2_input: endpoint@1 { 139 reg = <1>; 140 remote-endpoint = <&csi_dphy_output>; 141 }; 142 }; 143 144 port@1 { 145 reg = <1>; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 149 mipi_csi2_output: endpoint@0 { 150 reg = <0>; 151 remote-endpoint = <&cif_mipi_in>; 152 }; 153 }; 154 }; 155}; 156 157&mailbox { 158 status = "okay"; 159}; 160 161&rkcif { 162 status = "okay"; 163}; 164 165&rkcif_mipi_lvds { 166 status = "okay"; 167 memory-region-thunderboot = <&rkisp_thunderboot>; 168 169 pinctrl-names = "default"; 170 pinctrl-0 = <&mipi_pins>; 171 port { 172 /* MIPI CSI-2 endpoint */ 173 cif_mipi_in: endpoint { 174 remote-endpoint = <&mipi_csi2_output>; 175 }; 176 }; 177}; 178 179&rkcif_mipi_lvds_sditf { 180 status = "okay"; 181 182 port { 183 /* MIPI CSI-2 endpoint */ 184 mipi_lvds_sditf: endpoint { 185 remote-endpoint = <&isp_in>; 186 }; 187 }; 188}; 189 190&rkisp { 191 status = "okay"; 192}; 193 194&rkisp_vir0 { 195 status = "okay"; 196 197 port@0 { 198 isp_in: endpoint { 199 remote-endpoint = <&mipi_lvds_sditf>; 200 }; 201 }; 202}; 203 204&thunder_boot_service { 205 status = "okay"; 206}; 207 208&rkisp_thunderboot { 209 /* reg's offset MUST match with RTOS */ 210 /* 211 * vicap, capture raw10, ceil(w*10/8/256)*256*h *4(buf num) 212 * e.g. 2304x1296: 0xf30000 213 */ 214 reg = <0x00860000 0xf30000>; 215}; 216 217&ramdisk_r { 218 reg = <0x1790000 (20 * 0x00100000)>; 219}; 220 221&ramdisk_c { 222 reg = <0x2b90000 (10 * 0x00100000)>; 223}; 224 225&pinctrl { 226 sdmmc { 227 /omit-if-no-ref/ 228 sdmmc_pwren: sdmmc-pwren { 229 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; 230 }; 231 }; 232}; 233 234&pwm10 { 235 status = "okay"; 236}; 237 238&pwm11 { 239 status = "okay"; 240}; 241 242&sdio { 243 max-frequency = <50000000>; 244 bus-width = <1>; 245 cap-sd-highspeed; 246 cap-sdio-irq; 247 keep-power-in-suspend; 248 non-removable; 249 rockchip,default-sample-phase = <90>; 250 no-sd; 251 no-mmc; 252 supports-sdio; 253 pinctrl-names = "default"; 254 pinctrl-0 = <&sdmmc1m0_cmd &sdmmc1m0_clk &sdmmc1m0_bus4>; 255 status = "okay"; 256}; 257 258&sdmmc { 259 max-frequency = <200000000>; 260 no-sdio; 261 no-mmc; 262 bus-width = <4>; 263 cap-mmc-highspeed; 264 cap-sd-highspeed; 265 disable-wp; 266 pinctrl-names = "normal", "idle"; 267 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>; 268 pinctrl-1 = <&sdmmc0_idle_pins &sdmmc0_det>; 269 vmmc-supply = <&vcc3v3_sd>; 270 status = "okay"; 271}; 272 273&sfc { 274 assigned-clocks = <&cru SCLK_SFC>; 275 assigned-clock-rates = <125000000>; 276 status = "okay"; 277 278 flash@0 { 279 compatible = "jedec,spi-nor"; 280 reg = <0>; 281 spi-max-frequency = <125000000>; 282 spi-rx-bus-width = <4>; 283 spi-tx-bus-width = <1>; 284 }; 285}; 286 287&usbdrd_dwc3 { 288 dr_mode = "peripheral"; 289}; 290