1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/pinctrl/rockchip.h> 7#include "rockchip-pinconf.dtsi" 8 9/* 10 * This file is auto generated by pin2dts tool, please keep these code 11 * by adding changes at end of this file. 12 */ 13&pinctrl { 14 adc { 15 /omit-if-no-ref/ 16 adc_pins: adc-pins { 17 rockchip,pins = 18 /* adc_in0 */ 19 <4 RK_PC0 1 &pcfg_pull_none>, 20 /* adc_in1 */ 21 <4 RK_PC1 1 &pcfg_pull_none>; 22 }; 23 }; 24 25 avs { 26 /omit-if-no-ref/ 27 avs_pins: avs-pins { 28 rockchip,pins = 29 /* avs_arm */ 30 <1 RK_PA2 2 &pcfg_pull_none>; 31 }; 32 }; 33 34 clk { 35 /omit-if-no-ref/ 36 clk_32k: clk-32k { 37 rockchip,pins = 38 /* clk_32k */ 39 <0 RK_PA0 2 &pcfg_pull_none>; 40 }; 41 /omit-if-no-ref/ 42 clk_refout: clk-refout { 43 rockchip,pins = 44 /* clk_refout */ 45 <0 RK_PA0 3 &pcfg_pull_none>; 46 }; 47 }; 48 49 dsmaudio { 50 /omit-if-no-ref/ 51 dsmaudio_pins: dsmaudio-pins { 52 rockchip,pins = 53 /* dsmaudio_n */ 54 <1 RK_PD3 7 &pcfg_pull_none>, 55 /* dsmaudio_p */ 56 <1 RK_PD2 7 &pcfg_pull_none>; 57 }; 58 }; 59 60 emmc { 61 /omit-if-no-ref/ 62 emmc_bus8: emmc-bus8 { 63 rockchip,pins = 64 /* emmc_d0 */ 65 <4 RK_PA4 1 &pcfg_pull_up_drv_level_2>, 66 /* emmc_d1 */ 67 <4 RK_PA3 1 &pcfg_pull_up_drv_level_2>, 68 /* emmc_d2 */ 69 <4 RK_PA2 1 &pcfg_pull_up_drv_level_2>, 70 /* emmc_d3 */ 71 <4 RK_PA6 1 &pcfg_pull_up_drv_level_2>, 72 /* emmc_d4 */ 73 <4 RK_PA5 1 &pcfg_pull_up_drv_level_2>, 74 /* emmc_d5 */ 75 <4 RK_PA7 1 &pcfg_pull_up_drv_level_2>, 76 /* emmc_d6 */ 77 <4 RK_PA1 1 &pcfg_pull_up_drv_level_2>, 78 /* emmc_d7 */ 79 <4 RK_PA0 1 &pcfg_pull_up_drv_level_2>; 80 }; 81 82 /omit-if-no-ref/ 83 emmc_clk: emmc-clk { 84 rockchip,pins = 85 /* emmc_clk */ 86 <4 RK_PB1 1 &pcfg_pull_up_drv_level_2>; 87 }; 88 89 /omit-if-no-ref/ 90 emmc_cmd: emmc-cmd { 91 rockchip,pins = 92 /* emmc_cmd */ 93 <4 RK_PB0 1 &pcfg_pull_up_drv_level_2>; 94 }; 95 }; 96 97 flash { 98 /omit-if-no-ref/ 99 flash_pins: flash-pins { 100 rockchip,pins = 101 /* flash_trig_out */ 102 <2 RK_PA6 6 &pcfg_pull_none>; 103 }; 104 }; 105 106 fspi { 107 /omit-if-no-ref/ 108 fspi_pins: fspi-pins { 109 rockchip,pins = 110 /* fspi_clk */ 111 <4 RK_PB1 2 &pcfg_pull_up_drv_level_2>, 112 /* fspi_d0 */ 113 <4 RK_PA4 2 &pcfg_pull_none>, 114 /* fspi_d1 */ 115 <4 RK_PA3 2 &pcfg_pull_none>, 116 /* fspi_d2 */ 117 <4 RK_PA2 2 &pcfg_pull_none>, 118 /* fspi_d3 */ 119 <4 RK_PA6 2 &pcfg_pull_none>; 120 }; 121 122 /omit-if-no-ref/ 123 fspi_cs0: fspi-cs0 { 124 rockchip,pins = 125 /* fspi_cs0n */ 126 <4 RK_PB0 2 &pcfg_pull_up>; 127 }; 128 }; 129 130 hpmcu { 131 /omit-if-no-ref/ 132 hpmcum0_pins: hpmcum0-pins { 133 rockchip,pins = 134 /* hpmcu_jtag_tck_m0 */ 135 <1 RK_PB2 3 &pcfg_pull_none>, 136 /* hpmcu_jtag_tms_m0 */ 137 <1 RK_PB3 3 &pcfg_pull_none>; 138 }; 139 140 /omit-if-no-ref/ 141 hpmcum1_pins: hpmcum1-pins { 142 rockchip,pins = 143 /* hpmcu_jtag_tck_m1 */ 144 <3 RK_PA7 4 &pcfg_pull_none>, 145 /* hpmcu_jtag_tms_m1 */ 146 <3 RK_PA6 4 &pcfg_pull_none>; 147 }; 148 }; 149 150 i2c0 { 151 /omit-if-no-ref/ 152 i2c0m0_xfer: i2c0m0-xfer { 153 rockchip,pins = 154 /* i2c0_scl_m0 */ 155 <1 RK_PA3 2 &pcfg_pull_none_smt>, 156 /* i2c0_sda_m0 */ 157 <1 RK_PA4 2 &pcfg_pull_none_smt>; 158 }; 159 160 /omit-if-no-ref/ 161 i2c0m1_xfer: i2c0m1-xfer { 162 rockchip,pins = 163 /* i2c0_scl_m1 */ 164 <4 RK_PA1 4 &pcfg_pull_none_smt>, 165 /* i2c0_sda_m1 */ 166 <4 RK_PA0 4 &pcfg_pull_none_smt>; 167 }; 168 169 /omit-if-no-ref/ 170 i2c0m2_xfer: i2c0m2-xfer { 171 rockchip,pins = 172 /* i2c0_scl_m2 */ 173 <3 RK_PA4 3 &pcfg_pull_none_smt>, 174 /* i2c0_sda_m2 */ 175 <3 RK_PA5 3 &pcfg_pull_none_smt>; 176 }; 177 }; 178 179 i2c1 { 180 /omit-if-no-ref/ 181 i2c1m0_xfer: i2c1m0-xfer { 182 rockchip,pins = 183 /* i2c1_scl_m0 */ 184 <0 RK_PA5 1 &pcfg_pull_none_smt>, 185 /* i2c1_sda_m0 */ 186 <0 RK_PA6 1 &pcfg_pull_none_smt>; 187 }; 188 189 /omit-if-no-ref/ 190 i2c1m1_xfer: i2c1m1-xfer { 191 rockchip,pins = 192 /* i2c1_scl_m1 */ 193 <2 RK_PB0 2 &pcfg_pull_none_smt>, 194 /* i2c1_sda_m1 */ 195 <2 RK_PB1 2 &pcfg_pull_none_smt>; 196 }; 197 }; 198 199 i2c2 { 200 /omit-if-no-ref/ 201 i2c2m0_xfer: i2c2m0-xfer { 202 rockchip,pins = 203 /* i2c2_scl_m0 */ 204 <1 RK_PA0 2 &pcfg_pull_none_smt>, 205 /* i2c2_sda_m0 */ 206 <1 RK_PA1 2 &pcfg_pull_none_smt>; 207 }; 208 209 /omit-if-no-ref/ 210 i2c2m1_xfer: i2c2m1-xfer { 211 rockchip,pins = 212 /* i2c2_scl_m1 */ 213 <4 RK_PA7 4 &pcfg_pull_none_smt>, 214 /* i2c2_sda_m1 */ 215 <4 RK_PA5 4 &pcfg_pull_none_smt>; 216 }; 217 }; 218 219 i2c3 { 220 /omit-if-no-ref/ 221 i2c3m0_xfer: i2c3m0-xfer { 222 rockchip,pins = 223 /* i2c3_scl_m0 */ 224 <2 RK_PA6 5 &pcfg_pull_none_smt>, 225 /* i2c3_sda_m0 */ 226 <2 RK_PA7 5 &pcfg_pull_none_smt>; 227 }; 228 229 /omit-if-no-ref/ 230 i2c3m1_xfer: i2c3m1-xfer { 231 rockchip,pins = 232 /* i2c3_scl_m1 */ 233 <1 RK_PD3 3 &pcfg_pull_none_smt>, 234 /* i2c3_sda_m1 */ 235 <1 RK_PD2 3 &pcfg_pull_none_smt>; 236 }; 237 238 /omit-if-no-ref/ 239 i2c3m2_xfer: i2c3m2-xfer { 240 rockchip,pins = 241 /* i2c3_scl_m2 */ 242 <3 RK_PD1 3 &pcfg_pull_none_smt>, 243 /* i2c3_sda_m2 */ 244 <3 RK_PD2 3 &pcfg_pull_none_smt>; 245 }; 246 }; 247 248 i2c4 { 249 /omit-if-no-ref/ 250 i2c4m0_xfer: i2c4m0-xfer { 251 rockchip,pins = 252 /* i2c4_scl_m0 */ 253 <2 RK_PA1 5 &pcfg_pull_none_smt>, 254 /* i2c4_sda_m0 */ 255 <2 RK_PA0 5 &pcfg_pull_none_smt>; 256 }; 257 258 /omit-if-no-ref/ 259 i2c4m1_xfer: i2c4m1-xfer { 260 rockchip,pins = 261 /* i2c4_scl_m1 */ 262 <1 RK_PC2 4 &pcfg_pull_none_smt>, 263 /* i2c4_sda_m1 */ 264 <1 RK_PC3 4 &pcfg_pull_none_smt>; 265 }; 266 267 /omit-if-no-ref/ 268 i2c4m2_xfer: i2c4m2-xfer { 269 rockchip,pins = 270 /* i2c4_scl_m2 */ 271 <3 RK_PC7 3 &pcfg_pull_none_smt>, 272 /* i2c4_sda_m2 */ 273 <3 RK_PD0 3 &pcfg_pull_none_smt>; 274 }; 275 }; 276 277 i2s0 { 278 /omit-if-no-ref/ 279 i2s0_pins: i2s0-pins { 280 rockchip,pins = 281 /* i2s0_lrck */ 282 <2 RK_PA1 2 &pcfg_pull_none>, 283 /* i2s0_mclk */ 284 <2 RK_PA2 2 &pcfg_pull_none>, 285 /* i2s0_sclk */ 286 <2 RK_PA0 2 &pcfg_pull_none>, 287 /* i2s0_sdi0 */ 288 <2 RK_PA5 2 &pcfg_pull_none>, 289 /* i2s0_sdo0 */ 290 <2 RK_PA4 2 &pcfg_pull_none>, 291 /* i2s0_sdo1_sdi3 */ 292 <2 RK_PA7 2 &pcfg_pull_none>, 293 /* i2s0_sdo2_sdi2 */ 294 <2 RK_PA6 2 &pcfg_pull_none>, 295 /* i2s0_sdo3_sdi1 */ 296 <2 RK_PA3 2 &pcfg_pull_none>; 297 }; 298 }; 299 300 lcd { 301 /omit-if-no-ref/ 302 lcd_pins: lcd-pins { 303 rockchip,pins = 304 /* lcd_clk */ 305 <1 RK_PD3 1 &pcfg_pull_none_drv_level_4>, 306 /* lcd_d0 */ 307 <1 RK_PC7 1 &pcfg_pull_none_drv_level_3>, 308 /* lcd_d1 */ 309 <1 RK_PC6 1 &pcfg_pull_none_drv_level_3>, 310 /* lcd_d2 */ 311 <1 RK_PC5 1 &pcfg_pull_none_drv_level_3>, 312 /* lcd_d3 */ 313 <1 RK_PC4 1 &pcfg_pull_none_drv_level_3>, 314 /* lcd_d4 */ 315 <1 RK_PC3 1 &pcfg_pull_none_drv_level_3>, 316 /* lcd_d5 */ 317 <1 RK_PC2 1 &pcfg_pull_none_drv_level_3>, 318 /* lcd_d6 */ 319 <1 RK_PC1 1 &pcfg_pull_none_drv_level_3>, 320 /* lcd_d7 */ 321 <1 RK_PC0 1 &pcfg_pull_none_drv_level_3>, 322 /* lcd_d8 */ 323 <2 RK_PA0 3 &pcfg_pull_none_drv_level_3>, 324 /* lcd_d9 */ 325 <2 RK_PA1 3 &pcfg_pull_none_drv_level_3>, 326 /* lcd_d10 */ 327 <2 RK_PA2 3 &pcfg_pull_none_drv_level_3>, 328 /* lcd_d11 */ 329 <2 RK_PA3 3 &pcfg_pull_none_drv_level_3>, 330 /* lcd_d12 */ 331 <2 RK_PA4 3 &pcfg_pull_none_drv_level_3>, 332 /* lcd_d13 */ 333 <2 RK_PA5 3 &pcfg_pull_none_drv_level_3>, 334 /* lcd_d14 */ 335 <2 RK_PA6 3 &pcfg_pull_none_drv_level_3>, 336 /* lcd_d15 */ 337 <2 RK_PA7 3 &pcfg_pull_none_drv_level_3>, 338 /* lcd_d16 */ 339 <2 RK_PB0 3 &pcfg_pull_none_drv_level_3>, 340 /* lcd_d17 */ 341 <2 RK_PB1 3 &pcfg_pull_none_drv_level_3>, 342 /* lcd_den */ 343 <1 RK_PD0 1 &pcfg_pull_none_drv_level_3>, 344 /* lcd_hsync */ 345 <1 RK_PD1 1 &pcfg_pull_none_drv_level_3>, 346 /* lcd_vsync */ 347 <1 RK_PD2 1 &pcfg_pull_none_drv_level_3>; 348 }; 349 }; 350 351 lpmcu { 352 /omit-if-no-ref/ 353 lpmcum0_pins: lpmcum0-pins { 354 rockchip,pins = 355 /* lpmcu_jtag_tck_m0 */ 356 <1 RK_PB2 4 &pcfg_pull_none>, 357 /* lpmcu_jtag_tms_m0 */ 358 <1 RK_PB3 4 &pcfg_pull_none>; 359 }; 360 361 /omit-if-no-ref/ 362 lpmcum1_pins: lpmcum1-pins { 363 rockchip,pins = 364 /* lpmcu_jtag_tck_m1 */ 365 <3 RK_PA4 4 &pcfg_pull_none>, 366 /* lpmcu_jtag_tms_m1 */ 367 <3 RK_PA5 4 &pcfg_pull_none>; 368 }; 369 }; 370 371 mipi { 372 /omit-if-no-ref/ 373 mipi_pins: mipi-pins { 374 rockchip,pins = 375 /* mipi_lvds_ck0n */ 376 <3 RK_PC0 2 &pcfg_pull_none>, 377 /* mipi_lvds_ck0p */ 378 <3 RK_PC1 2 &pcfg_pull_none>, 379 /* mipi_lvds_ck1n */ 380 <3 RK_PB2 2 &pcfg_pull_none>, 381 /* mipi_lvds_ck1p */ 382 <3 RK_PB3 2 &pcfg_pull_none>, 383 /* mipi_lvds_d0n */ 384 <3 RK_PC2 2 &pcfg_pull_none>, 385 /* mipi_lvds_d0p */ 386 <3 RK_PC3 2 &pcfg_pull_none>, 387 /* mipi_lvds_d1n */ 388 <3 RK_PB6 2 &pcfg_pull_none>, 389 /* mipi_lvds_d1p */ 390 <3 RK_PB7 2 &pcfg_pull_none>, 391 /* mipi_lvds_d2n */ 392 <3 RK_PB4 2 &pcfg_pull_none>, 393 /* mipi_lvds_d2p */ 394 <3 RK_PB5 2 &pcfg_pull_none>, 395 /* mipi_lvds_d3n */ 396 <3 RK_PB0 2 &pcfg_pull_none>, 397 /* mipi_lvds_d3p */ 398 <3 RK_PB1 2 &pcfg_pull_none>; 399 }; 400 }; 401 402 pmic { 403 /omit-if-no-ref/ 404 pmicm0_pins: pmicm0-pins { 405 rockchip,pins = 406 /* pmic_sleep_m0 */ 407 <0 RK_PA4 1 &pcfg_pull_none>; 408 }; 409 410 /omit-if-no-ref/ 411 pmicm1_pins: pmicm1-pins { 412 rockchip,pins = 413 /* pmic_sleep_m1 */ 414 <0 RK_PA3 1 &pcfg_pull_none>; 415 }; 416 }; 417 418 pmu { 419 /omit-if-no-ref/ 420 pmu_pins: pmu-pins { 421 rockchip,pins = 422 /* pmu_debug */ 423 <1 RK_PA1 3 &pcfg_pull_none>; 424 }; 425 }; 426 427 prelight { 428 /omit-if-no-ref/ 429 prelight_pins: prelight-pins { 430 rockchip,pins = 431 /* prelight_trig_out */ 432 <2 RK_PA7 6 &pcfg_pull_none>; 433 }; 434 }; 435 436 pwm0 { 437 /omit-if-no-ref/ 438 pwm0m0_pins: pwm0m0-pins { 439 rockchip,pins = 440 /* pwm0_m0 */ 441 <1 RK_PA2 1 &pcfg_pull_none>; 442 }; 443 444 /omit-if-no-ref/ 445 pwm0m1_pins: pwm0m1-pins { 446 rockchip,pins = 447 /* pwm0_m1 */ 448 <1 RK_PD2 6 &pcfg_pull_none>; 449 }; 450 }; 451 452 pwm1 { 453 /omit-if-no-ref/ 454 pwm1m0_pins: pwm1m0-pins { 455 rockchip,pins = 456 /* pwm1_m0 */ 457 <0 RK_PA4 2 &pcfg_pull_none>; 458 }; 459 460 /omit-if-no-ref/ 461 pwm1m1_pins: pwm1m1-pins { 462 rockchip,pins = 463 /* pwm1_m1 */ 464 <4 RK_PC1 2 &pcfg_pull_none>; 465 }; 466 467 /omit-if-no-ref/ 468 pwm1m2_pins: pwm1m2-pins { 469 rockchip,pins = 470 /* pwm1_m2 */ 471 <3 RK_PD3 2 &pcfg_pull_none>; 472 }; 473 }; 474 475 pwm2 { 476 /omit-if-no-ref/ 477 pwm2m0_pins: pwm2m0-pins { 478 rockchip,pins = 479 /* pwm2_m0 */ 480 <0 RK_PA1 2 &pcfg_pull_none>; 481 }; 482 483 /omit-if-no-ref/ 484 pwm2m1_pins: pwm2m1-pins { 485 rockchip,pins = 486 /* pwm2_m1 */ 487 <2 RK_PA6 4 &pcfg_pull_none>; 488 }; 489 490 /omit-if-no-ref/ 491 pwm2m2_pins: pwm2m2-pins { 492 rockchip,pins = 493 /* pwm2_m2 */ 494 <1 RK_PC0 3 &pcfg_pull_none>; 495 }; 496 }; 497 498 pwm3 { 499 /omit-if-no-ref/ 500 pwm3m0_pins: pwm3m0-pins { 501 rockchip,pins = 502 /* pwm3_ir_m0 */ 503 <0 RK_PA2 1 &pcfg_pull_none>; 504 }; 505 506 /omit-if-no-ref/ 507 pwm3m1_pins: pwm3m1-pins { 508 rockchip,pins = 509 /* pwm3_ir_m1 */ 510 <1 RK_PB0 2 &pcfg_pull_none>; 511 }; 512 513 /omit-if-no-ref/ 514 pwm3m2_pins: pwm3m2-pins { 515 rockchip,pins = 516 /* pwm3_ir_m2 */ 517 <1 RK_PD0 3 &pcfg_pull_none>; 518 }; 519 }; 520 521 pwm4 { 522 /omit-if-no-ref/ 523 pwm4m0_pins: pwm4m0-pins { 524 rockchip,pins = 525 /* pwm4_m0 */ 526 <1 RK_PA1 4 &pcfg_pull_none>; 527 }; 528 529 /omit-if-no-ref/ 530 pwm4m1_pins: pwm4m1-pins { 531 rockchip,pins = 532 /* pwm4_m1 */ 533 <2 RK_PA7 4 &pcfg_pull_none>; 534 }; 535 536 /omit-if-no-ref/ 537 pwm4m2_pins: pwm4m2-pins { 538 rockchip,pins = 539 /* pwm4_m2 */ 540 <1 RK_PC1 3 &pcfg_pull_none>; 541 }; 542 }; 543 544 pwm5 { 545 /omit-if-no-ref/ 546 pwm5m0_pins: pwm5m0-pins { 547 rockchip,pins = 548 /* pwm5_m0 */ 549 <0 RK_PA5 3 &pcfg_pull_none>; 550 }; 551 552 /omit-if-no-ref/ 553 pwm5m1_pins: pwm5m1-pins { 554 rockchip,pins = 555 /* pwm5_m1 */ 556 <2 RK_PB0 4 &pcfg_pull_none>; 557 }; 558 559 /omit-if-no-ref/ 560 pwm5m2_pins: pwm5m2-pins { 561 rockchip,pins = 562 /* pwm5_m2 */ 563 <1 RK_PC2 3 &pcfg_pull_none>; 564 }; 565 }; 566 567 pwm6 { 568 /omit-if-no-ref/ 569 pwm6m0_pins: pwm6m0-pins { 570 rockchip,pins = 571 /* pwm6_m0 */ 572 <0 RK_PA6 3 &pcfg_pull_none>; 573 }; 574 575 /omit-if-no-ref/ 576 pwm6m1_pins: pwm6m1-pins { 577 rockchip,pins = 578 /* pwm6_m1 */ 579 <2 RK_PB1 4 &pcfg_pull_none>; 580 }; 581 582 /omit-if-no-ref/ 583 pwm6m2_pins: pwm6m2-pins { 584 rockchip,pins = 585 /* pwm6_m2 */ 586 <1 RK_PC3 3 &pcfg_pull_none>; 587 }; 588 }; 589 590 pwm7 { 591 /omit-if-no-ref/ 592 pwm7m0_pins: pwm7m0-pins { 593 rockchip,pins = 594 /* pwm7_ir_m0 */ 595 <1 RK_PA0 3 &pcfg_pull_none>; 596 }; 597 598 /omit-if-no-ref/ 599 pwm7m1_pins: pwm7m1-pins { 600 rockchip,pins = 601 /* pwm7_ir_m1 */ 602 <1 RK_PB1 2 &pcfg_pull_none>; 603 }; 604 605 /omit-if-no-ref/ 606 pwm7m2_pins: pwm7m2-pins { 607 rockchip,pins = 608 /* pwm7_ir_m2 */ 609 <3 RK_PC6 2 &pcfg_pull_none>; 610 }; 611 }; 612 613 pwm8 { 614 /omit-if-no-ref/ 615 pwm8m0_pins: pwm8m0-pins { 616 rockchip,pins = 617 /* pwm8_m0 */ 618 <3 RK_PA3 4 &pcfg_pull_none>; 619 }; 620 621 /omit-if-no-ref/ 622 pwm8m1_pins: pwm8m1-pins { 623 rockchip,pins = 624 /* pwm8_m1 */ 625 <1 RK_PC4 3 &pcfg_pull_none>; 626 }; 627 }; 628 629 pwm9 { 630 /omit-if-no-ref/ 631 pwm9m0_pins: pwm9m0-pins { 632 rockchip,pins = 633 /* pwm9_m0 */ 634 <3 RK_PA2 4 &pcfg_pull_none>; 635 }; 636 637 /omit-if-no-ref/ 638 pwm9m1_pins: pwm9m1-pins { 639 rockchip,pins = 640 /* pwm9_m1 */ 641 <1 RK_PC5 3 &pcfg_pull_none>; 642 }; 643 }; 644 645 pwm10 { 646 /omit-if-no-ref/ 647 pwm10m0_pins: pwm10m0-pins { 648 rockchip,pins = 649 /* pwm10_m0 */ 650 <3 RK_PA4 5 &pcfg_pull_none>; 651 }; 652 653 /omit-if-no-ref/ 654 pwm10m1_pins: pwm10m1-pins { 655 rockchip,pins = 656 /* pwm10_m1 */ 657 <1 RK_PC6 3 &pcfg_pull_none>; 658 }; 659 660 /omit-if-no-ref/ 661 pwm10m2_pins: pwm10m2-pins { 662 rockchip,pins = 663 /* pwm10_m2 */ 664 <1 RK_PD1 3 &pcfg_pull_none>; 665 }; 666 }; 667 668 pwm11 { 669 /omit-if-no-ref/ 670 pwm11m0_pins: pwm11m0-pins { 671 rockchip,pins = 672 /* pwm11_ir_m0 */ 673 <3 RK_PA5 5 &pcfg_pull_none>; 674 }; 675 676 /omit-if-no-ref/ 677 pwm11m1_pins: pwm11m1-pins { 678 rockchip,pins = 679 /* pwm11_ir_m1 */ 680 <1 RK_PC7 3 &pcfg_pull_none>; 681 }; 682 683 /omit-if-no-ref/ 684 pwm11m2_pins: pwm11m2-pins { 685 rockchip,pins = 686 /* pwm11_ir_m2 */ 687 <1 RK_PD3 5 &pcfg_pull_none>; 688 }; 689 }; 690 691 rtc { 692 /omit-if-no-ref/ 693 rtc_pins: rtc-pins { 694 rockchip,pins = 695 /* rtc_clko */ 696 <0 RK_PA0 4 &pcfg_pull_none>; 697 }; 698 }; 699 700 sdmmc0 { 701 /omit-if-no-ref/ 702 sdmmc0_bus4: sdmmc0-bus4 { 703 rockchip,pins = 704 /* sdmmc0_d0 */ 705 <3 RK_PA3 1 &pcfg_pull_up_drv_level_2>, 706 /* sdmmc0_d1 */ 707 <3 RK_PA2 1 &pcfg_pull_up_drv_level_2>, 708 /* sdmmc0_d2 */ 709 <3 RK_PA7 1 &pcfg_pull_up_drv_level_2>, 710 /* sdmmc0_d3 */ 711 <3 RK_PA6 1 &pcfg_pull_up_drv_level_2>; 712 }; 713 714 /omit-if-no-ref/ 715 sdmmc0_clk: sdmmc0-clk { 716 rockchip,pins = 717 /* sdmmc0_clk */ 718 <3 RK_PA4 1 &pcfg_pull_up_drv_level_2>; 719 }; 720 721 /omit-if-no-ref/ 722 sdmmc0_cmd: sdmmc0-cmd { 723 rockchip,pins = 724 /* sdmmc0_cmd */ 725 <3 RK_PA5 1 &pcfg_pull_up_drv_level_2>; 726 }; 727 728 /omit-if-no-ref/ 729 sdmmc0_det: sdmmc0-det { 730 rockchip,pins = 731 /* sdmmc0_det */ 732 <3 RK_PA1 1 &pcfg_pull_up>; 733 }; 734 735 /omit-if-no-ref/ 736 sdmmc0_idle_pins: sdmmc0-idle-pins { 737 rockchip,pins = 738 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>, 739 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_down>, 740 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>, 741 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>, 742 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>, 743 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; 744 }; 745 }; 746 747 sdmmc1 { 748 /omit-if-no-ref/ 749 sdmmc1m0_bus1: sdmmc1m0-bus1 { 750 rockchip,pins = 751 /* sdmmc1_d0_m0 */ 752 <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>; 753 }; 754 755 /omit-if-no-ref/ 756 sdmmc1m0_bus4: sdmmc1m0-bus4 { 757 rockchip,pins = 758 /* sdmmc1_d0_m0 */ 759 <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>, 760 /* sdmmc1_d1_m0 */ 761 <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>, 762 /* sdmmc1_d2_m0 */ 763 <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>, 764 /* sdmmc1_d3_m0 */ 765 <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>; 766 }; 767 768 /omit-if-no-ref/ 769 sdmmc1m0_clk: sdmmc1m0-clk { 770 rockchip,pins = 771 /* sdmmc1_clk_m0 */ 772 <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>; 773 }; 774 775 /omit-if-no-ref/ 776 sdmmc1m0_cmd: sdmmc1m0-cmd { 777 rockchip,pins = 778 /* sdmmc1_cmd_m0 */ 779 <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>; 780 }; 781 782 /omit-if-no-ref/ 783 sdmmc1m0_idle_pins: sdmmc1m0-idle-pins { 784 rockchip,pins = 785 <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>, 786 <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>, 787 <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>, 788 <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_down>, 789 <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>, 790 <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>; 791 }; 792 793 /omit-if-no-ref/ 794 sdmmc1m1_bus4: sdmmc1m1-bus4 { 795 rockchip,pins = 796 /* sdmmc1_d0_m1 */ 797 <1 RK_PC1 5 &pcfg_pull_up_drv_level_2>, 798 /* sdmmc1_d1_m1 */ 799 <1 RK_PC0 5 &pcfg_pull_up_drv_level_2>, 800 /* sdmmc1_d2_m1 */ 801 <1 RK_PC5 5 &pcfg_pull_up_drv_level_2>, 802 /* sdmmc1_d3_m1 */ 803 <1 RK_PC4 5 &pcfg_pull_up_drv_level_2>; 804 }; 805 806 /omit-if-no-ref/ 807 sdmmc1m1_clk: sdmmc1m1-clk { 808 rockchip,pins = 809 /* sdmmc1_clk_m1 */ 810 <1 RK_PC2 5 &pcfg_pull_up_drv_level_2>; 811 }; 812 813 /omit-if-no-ref/ 814 sdmmc1m1_cmd: sdmmc1m1-cmd { 815 rockchip,pins = 816 /* sdmmc1_cmd_m1 */ 817 <1 RK_PC3 5 &pcfg_pull_up_drv_level_2>; 818 }; 819 820 /omit-if-no-ref/ 821 sdmmc1m1_idle_pins: sdmmc1m1-idle-pins { 822 rockchip,pins = 823 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>, 824 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>, 825 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>, 826 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>, 827 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>, 828 <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; 829 }; 830 }; 831 832 spi0 { 833 /omit-if-no-ref/ 834 spi0m0_pins: spi0m0-pins { 835 rockchip,pins = 836 /* spi0_clk_m0 */ 837 <1 RK_PC1 4 &pcfg_pull_none>, 838 /* spi0_miso_m0 */ 839 <1 RK_PC3 6 &pcfg_pull_none>, 840 /* spi0_mosi_m0 */ 841 <1 RK_PC2 6 &pcfg_pull_none>; 842 }; 843 844 /omit-if-no-ref/ 845 spi0m0_cs0: spi0m0-cs0 { 846 rockchip,pins = 847 /* spi0_cs0n_m0 */ 848 <1 RK_PC0 4 &pcfg_pull_none>; 849 }; 850 851 /omit-if-no-ref/ 852 spi0m0_cs1: spi0m0-cs1 { 853 rockchip,pins = 854 /* spi0_cs1n_m0 */ 855 <1 RK_PD2 5 &pcfg_pull_none>; 856 }; 857 }; 858 859 spi1 { 860 /omit-if-no-ref/ 861 spi1m0_pins: spi1m0-pins { 862 rockchip,pins = 863 /* spi1_clk_m0 */ 864 <4 RK_PA7 2 &pcfg_pull_none>, 865 /* spi1_miso_m0 */ 866 <4 RK_PA0 2 &pcfg_pull_none>, 867 /* spi1_mosi_m0 */ 868 <4 RK_PA1 2 &pcfg_pull_none>; 869 }; 870 871 /omit-if-no-ref/ 872 spi1m0_cs0: spi1m0-cs0 { 873 rockchip,pins = 874 /* spi1_cs0n_m0 */ 875 <4 RK_PA5 2 &pcfg_pull_none>; 876 }; 877 878 /omit-if-no-ref/ 879 spi1m0_cs1: spi1m0-cs1 { 880 rockchip,pins = 881 /* spi1_cs1n_m0 */ 882 <1 RK_PB1 3 &pcfg_pull_none>; 883 }; 884 }; 885 886 uart0 { 887 /omit-if-no-ref/ 888 uart0m0_xfer: uart0m0-xfer { 889 rockchip,pins = 890 /* uart0_rx_m0 */ 891 <0 RK_PA0 1 &pcfg_pull_up>, 892 /* uart0_tx_m0 */ 893 <0 RK_PA1 1 &pcfg_pull_up>; 894 }; 895 896 /omit-if-no-ref/ 897 uart0m1_xfer: uart0m1-xfer { 898 rockchip,pins = 899 /* uart0_rx_m1 */ 900 <2 RK_PB0 1 &pcfg_pull_up>, 901 /* uart0_tx_m1 */ 902 <2 RK_PB1 1 &pcfg_pull_up>; 903 }; 904 905 /omit-if-no-ref/ 906 uart0m1_ctsn: uart0m1-ctsn { 907 rockchip,pins = 908 /* uart0m1_ctsn */ 909 <2 RK_PA7 1 &pcfg_pull_none>; 910 }; 911 /omit-if-no-ref/ 912 uart0m1_rtsn: uart0m1-rtsn { 913 rockchip,pins = 914 /* uart0m1_rtsn */ 915 <2 RK_PA6 1 &pcfg_pull_none>; 916 }; 917 918 /omit-if-no-ref/ 919 uart0m2_xfer: uart0m2-xfer { 920 rockchip,pins = 921 /* uart0_rx_m2 */ 922 <4 RK_PA0 3 &pcfg_pull_up>, 923 /* uart0_tx_m2 */ 924 <4 RK_PA1 3 &pcfg_pull_up>; 925 }; 926 }; 927 928 uart1 { 929 /omit-if-no-ref/ 930 uart1m0_xfer: uart1m0-xfer { 931 rockchip,pins = 932 /* uart1_rx_m0 */ 933 <1 RK_PA4 1 &pcfg_pull_up>, 934 /* uart1_tx_m0 */ 935 <1 RK_PA3 1 &pcfg_pull_up>; 936 }; 937 938 /omit-if-no-ref/ 939 uart1m0_ctsn: uart1m0-ctsn { 940 rockchip,pins = 941 /* uart1m0_ctsn */ 942 <0 RK_PA6 2 &pcfg_pull_none>; 943 }; 944 /omit-if-no-ref/ 945 uart1m0_rtsn: uart1m0-rtsn { 946 rockchip,pins = 947 /* uart1m0_rtsn */ 948 <0 RK_PA5 2 &pcfg_pull_none>; 949 }; 950 951 /omit-if-no-ref/ 952 uart1m1_xfer: uart1m1-xfer { 953 rockchip,pins = 954 /* uart1_rx_m1 */ 955 <2 RK_PA5 4 &pcfg_pull_up>, 956 /* uart1_tx_m1 */ 957 <2 RK_PA4 4 &pcfg_pull_up>; 958 }; 959 960 /omit-if-no-ref/ 961 uart1m1_ctsn: uart1m1-ctsn { 962 rockchip,pins = 963 /* uart1m1_ctsn */ 964 <2 RK_PA0 4 &pcfg_pull_none>; 965 }; 966 /omit-if-no-ref/ 967 uart1m1_rtsn: uart1m1-rtsn { 968 rockchip,pins = 969 /* uart1m1_rtsn */ 970 <2 RK_PA1 4 &pcfg_pull_none>; 971 }; 972 973 /omit-if-no-ref/ 974 uart1m2_xfer: uart1m2-xfer { 975 rockchip,pins = 976 /* uart1_rx_m2 */ 977 <4 RK_PA7 3 &pcfg_pull_up>, 978 /* uart1_tx_m2 */ 979 <4 RK_PA5 3 &pcfg_pull_up>; 980 }; 981 }; 982 983 uart2 { 984 /omit-if-no-ref/ 985 uart2m0_xfer: uart2m0-xfer { 986 rockchip,pins = 987 /* uart2_rx_m0 */ 988 <3 RK_PA3 2 &pcfg_pull_up>, 989 /* uart2_tx_m0 */ 990 <3 RK_PA2 2 &pcfg_pull_up>; 991 }; 992 993 /omit-if-no-ref/ 994 uart2m1_xfer: uart2m1-xfer { 995 rockchip,pins = 996 /* uart2_rx_m1 */ 997 <1 RK_PB3 2 &pcfg_pull_up>, 998 /* uart2_tx_m1 */ 999 <1 RK_PB2 2 &pcfg_pull_up>; 1000 }; 1001 }; 1002 1003 uart3 { 1004 /omit-if-no-ref/ 1005 uart3m0_xfer: uart3m0-xfer { 1006 rockchip,pins = 1007 /* uart3_rx_m0 */ 1008 <1 RK_PA1 1 &pcfg_pull_up>, 1009 /* uart3_tx_m0 */ 1010 <1 RK_PA0 1 &pcfg_pull_up>; 1011 }; 1012 1013 /omit-if-no-ref/ 1014 uart3m1_xfer: uart3m1-xfer { 1015 rockchip,pins = 1016 /* uart3_rx_m1 */ 1017 <1 RK_PD1 5 &pcfg_pull_up>, 1018 /* uart3_tx_m1 */ 1019 <1 RK_PD0 5 &pcfg_pull_up>; 1020 }; 1021 }; 1022 1023 uart4 { 1024 /omit-if-no-ref/ 1025 uart4m0_xfer: uart4m0-xfer { 1026 rockchip,pins = 1027 /* uart4_rx_m0 */ 1028 <1 RK_PB0 1 &pcfg_pull_up>, 1029 /* uart4_tx_m0 */ 1030 <1 RK_PB1 1 &pcfg_pull_up>; 1031 }; 1032 1033 /omit-if-no-ref/ 1034 uart4m1_xfer: uart4m1-xfer { 1035 rockchip,pins = 1036 /* uart4_rx_m1 */ 1037 <1 RK_PC4 4 &pcfg_pull_up>, 1038 /* uart4_tx_m1 */ 1039 <1 RK_PC5 4 &pcfg_pull_up>; 1040 }; 1041 1042 /omit-if-no-ref/ 1043 uart4m1_ctsn: uart4m1-ctsn { 1044 rockchip,pins = 1045 /* uart4m1_ctsn */ 1046 <1 RK_PC7 4 &pcfg_pull_none>; 1047 }; 1048 /omit-if-no-ref/ 1049 uart4m1_rtsn: uart4m1-rtsn { 1050 rockchip,pins = 1051 /* uart4m1_rtsn */ 1052 <1 RK_PC6 4 &pcfg_pull_none>; 1053 }; 1054 }; 1055 1056 uart5 { 1057 /omit-if-no-ref/ 1058 uart5m0_xfer: uart5m0-xfer { 1059 rockchip,pins = 1060 /* uart5_rx_m0 */ 1061 <3 RK_PA7 2 &pcfg_pull_up>, 1062 /* uart5_tx_m0 */ 1063 <3 RK_PA6 2 &pcfg_pull_up>; 1064 }; 1065 1066 /omit-if-no-ref/ 1067 uart5m0_ctsn: uart5m0-ctsn { 1068 rockchip,pins = 1069 /* uart5m0_ctsn */ 1070 <3 RK_PA5 2 &pcfg_pull_none>; 1071 }; 1072 /omit-if-no-ref/ 1073 uart5m0_rtsn: uart5m0-rtsn { 1074 rockchip,pins = 1075 /* uart5m0_rtsn */ 1076 <3 RK_PA4 2 &pcfg_pull_none>; 1077 }; 1078 1079 /omit-if-no-ref/ 1080 uart5m1_xfer: uart5m1-xfer { 1081 rockchip,pins = 1082 /* uart5_rx_m1 */ 1083 <1 RK_PD2 4 &pcfg_pull_up>, 1084 /* uart5_tx_m1 */ 1085 <1 RK_PD3 4 &pcfg_pull_up>; 1086 }; 1087 1088 /omit-if-no-ref/ 1089 uart5m1_ctsn: uart5m1-ctsn { 1090 rockchip,pins = 1091 /* uart5m1_ctsn */ 1092 <1 RK_PD1 4 &pcfg_pull_none>; 1093 }; 1094 /omit-if-no-ref/ 1095 uart5m1_rtsn: uart5m1-rtsn { 1096 rockchip,pins = 1097 /* uart5m1_rtsn */ 1098 <1 RK_PD0 4 &pcfg_pull_none>; 1099 }; 1100 1101 /omit-if-no-ref/ 1102 uart5m2_xfer: uart5m2-xfer { 1103 rockchip,pins = 1104 /* uart5_rx_m2 */ 1105 <3 RK_PD0 2 &pcfg_pull_up>, 1106 /* uart5_tx_m2 */ 1107 <3 RK_PC7 2 &pcfg_pull_up>; 1108 }; 1109 1110 /omit-if-no-ref/ 1111 uart5m2_ctsn: uart5m2-ctsn { 1112 rockchip,pins = 1113 /* uart5m2_ctsn */ 1114 <3 RK_PD2 2 &pcfg_pull_none>; 1115 }; 1116 /omit-if-no-ref/ 1117 uart5m2_rtsn: uart5m2-rtsn { 1118 rockchip,pins = 1119 /* uart5m2_rtsn */ 1120 <3 RK_PD1 2 &pcfg_pull_none>; 1121 }; 1122 }; 1123 1124 vicap { 1125 /omit-if-no-ref/ 1126 vicapm0_pins: vicapm0-pins { 1127 rockchip,pins = 1128 /* vicap_clkin_m0 */ 1129 <3 RK_PC2 1 &pcfg_pull_none>, 1130 /* vicap_d0_m0 */ 1131 <3 RK_PB0 1 &pcfg_pull_none>, 1132 /* vicap_d1_m0 */ 1133 <3 RK_PB1 1 &pcfg_pull_none>, 1134 /* vicap_d2_m0 */ 1135 <3 RK_PB2 1 &pcfg_pull_none>, 1136 /* vicap_d3_m0 */ 1137 <3 RK_PB3 1 &pcfg_pull_none>, 1138 /* vicap_d4_m0 */ 1139 <3 RK_PB4 1 &pcfg_pull_none>, 1140 /* vicap_d5_m0 */ 1141 <3 RK_PB5 1 &pcfg_pull_none>, 1142 /* vicap_d6_m0 */ 1143 <3 RK_PB6 1 &pcfg_pull_none>, 1144 /* vicap_d7_m0 */ 1145 <3 RK_PB7 1 &pcfg_pull_none>, 1146 /* vicap_d8_m0 */ 1147 <3 RK_PC0 1 &pcfg_pull_none>, 1148 /* vicap_d9_m0 */ 1149 <3 RK_PC1 1 &pcfg_pull_none>, 1150 /* vicap_hsync_m0 */ 1151 <3 RK_PC3 1 &pcfg_pull_none>, 1152 /* vicap_vsync_m0 */ 1153 <3 RK_PC5 1 &pcfg_pull_none>; 1154 }; 1155 1156 /omit-if-no-ref/ 1157 vicapm1_pins: vicapm1-pins { 1158 rockchip,pins = 1159 /* vicap_clkin_m1 */ 1160 <1 RK_PD0 2 &pcfg_pull_none>, 1161 /* vicap_d0_m1 */ 1162 <1 RK_PA2 3 &pcfg_pull_none>, 1163 /* vicap_d1_m1 */ 1164 <1 RK_PB1 4 &pcfg_pull_none>, 1165 /* vicap_d2_m1 */ 1166 <1 RK_PC0 2 &pcfg_pull_none>, 1167 /* vicap_d3_m1 */ 1168 <1 RK_PC1 2 &pcfg_pull_none>, 1169 /* vicap_d4_m1 */ 1170 <1 RK_PC2 2 &pcfg_pull_none>, 1171 /* vicap_d5_m1 */ 1172 <1 RK_PC3 2 &pcfg_pull_none>, 1173 /* vicap_d6_m1 */ 1174 <1 RK_PC4 2 &pcfg_pull_none>, 1175 /* vicap_d7_m1 */ 1176 <1 RK_PC5 2 &pcfg_pull_none>, 1177 /* vicap_d8_m1 */ 1178 <1 RK_PC6 2 &pcfg_pull_none>, 1179 /* vicap_d9_m1 */ 1180 <1 RK_PC7 2 &pcfg_pull_none>, 1181 /* vicap_hsync_m1 */ 1182 <1 RK_PD1 2 &pcfg_pull_none>, 1183 /* vicap_vsync_m1 */ 1184 <1 RK_PD2 2 &pcfg_pull_none>; 1185 }; 1186 1187 /omit-if-no-ref/ 1188 vicap_d10: vicap-d10 { 1189 rockchip,pins = 1190 /* vicap_d10 */ 1191 <3 RK_PC6 1 &pcfg_pull_none>; 1192 }; 1193 /omit-if-no-ref/ 1194 vicap_d11: vicap-d11 { 1195 rockchip,pins = 1196 /* vicap_d11 */ 1197 <3 RK_PC7 1 &pcfg_pull_none>; 1198 }; 1199 /omit-if-no-ref/ 1200 vicap_d12: vicap-d12 { 1201 rockchip,pins = 1202 /* vicap_d12 */ 1203 <3 RK_PD0 1 &pcfg_pull_none>; 1204 }; 1205 /omit-if-no-ref/ 1206 vicap_d13: vicap-d13 { 1207 rockchip,pins = 1208 /* vicap_d13 */ 1209 <3 RK_PD1 1 &pcfg_pull_none>; 1210 }; 1211 /omit-if-no-ref/ 1212 vicap_d14: vicap-d14 { 1213 rockchip,pins = 1214 /* vicap_d14 */ 1215 <3 RK_PD2 1 &pcfg_pull_none>; 1216 }; 1217 /omit-if-no-ref/ 1218 vicap_d15: vicap-d15 { 1219 rockchip,pins = 1220 /* vicap_d15 */ 1221 <3 RK_PD3 1 &pcfg_pull_none>; 1222 }; 1223 }; 1224}; 1225 1226/* 1227 * This part is edited handly. 1228 */ 1229&pinctrl { 1230 vicap { 1231 /omit-if-no-ref/ 1232 vicap_clkout_m0: vicap-clkout-m0 { 1233 rockchip,pins = 1234 /* vicap_clkout_m0 */ 1235 <3 RK_PC4 1 &pcfg_pull_none>; 1236 }; 1237 1238 /omit-if-no-ref/ 1239 vicap_clkout_m1: vicap-clkout-m1 { 1240 rockchip,pins = 1241 /* vicap_clkout_m1 */ 1242 <1 RK_PD3 2 &pcfg_pull_none>; 1243 }; 1244 }; 1245 1246 mipi { 1247 /omit-if-no-ref/ 1248 mipi_refclk_out0: mipi-refclk-out0 { 1249 rockchip,pins = 1250 /* mipi_refclk_out0 */ 1251 <3 RK_PC4 2 &pcfg_pull_none>; 1252 }; 1253 /omit-if-no-ref/ 1254 mipi_refclk_out1: mipi-refclk-out1 { 1255 rockchip,pins = 1256 /* mipi_refclk_out1 */ 1257 <3 RK_PC6 3 &pcfg_pull_none>; 1258 }; 1259 }; 1260 1261 lcd { 1262 /omit-if-no-ref/ 1263 bt1120_pins: bt1120-pins { 1264 rockchip,pins = 1265 /* lcd_clk */ 1266 <1 RK_PD3 1 &pcfg_pull_none_drv_level_3>, 1267 /* lcd_d0 */ 1268 <1 RK_PC7 1 &pcfg_pull_none_drv_level_2>, 1269 /* lcd_d1 */ 1270 <1 RK_PC6 1 &pcfg_pull_none_drv_level_2>, 1271 /* lcd_d2 */ 1272 <1 RK_PC5 1 &pcfg_pull_none_drv_level_2>, 1273 /* lcd_d3 */ 1274 <1 RK_PC4 1 &pcfg_pull_none_drv_level_2>, 1275 /* lcd_d4 */ 1276 <1 RK_PC3 1 &pcfg_pull_none_drv_level_2>, 1277 /* lcd_d5 */ 1278 <1 RK_PC2 1 &pcfg_pull_none_drv_level_2>, 1279 /* lcd_d6 */ 1280 <1 RK_PC1 1 &pcfg_pull_none_drv_level_2>, 1281 /* lcd_d7 */ 1282 <1 RK_PC0 1 &pcfg_pull_none_drv_level_2>, 1283 /* lcd_d8 */ 1284 <2 RK_PA0 3 &pcfg_pull_none_drv_level_2>, 1285 /* lcd_d9 */ 1286 <2 RK_PA1 3 &pcfg_pull_none_drv_level_2>, 1287 /* lcd_d10 */ 1288 <2 RK_PA2 3 &pcfg_pull_none_drv_level_2>, 1289 /* lcd_d11 */ 1290 <2 RK_PA3 3 &pcfg_pull_none_drv_level_2>, 1291 /* lcd_d12 */ 1292 <2 RK_PA4 3 &pcfg_pull_none_drv_level_2>, 1293 /* lcd_d13 */ 1294 <2 RK_PA5 3 &pcfg_pull_none_drv_level_2>, 1295 /* lcd_d14 */ 1296 <2 RK_PA6 3 &pcfg_pull_none_drv_level_2>, 1297 /* lcd_d15 */ 1298 <2 RK_PA7 3 &pcfg_pull_none_drv_level_2>; 1299 }; 1300 1301 /omit-if-no-ref/ 1302 bt656_pins: bt656-pins { 1303 rockchip,pins = 1304 /* lcd_clk */ 1305 <1 RK_PD3 1 &pcfg_pull_none_drv_level_2>, 1306 /* lcd_d0 */ 1307 <1 RK_PC7 1 &pcfg_pull_none_drv_level_1>, 1308 /* lcd_d1 */ 1309 <1 RK_PC6 1 &pcfg_pull_none_drv_level_1>, 1310 /* lcd_d2 */ 1311 <1 RK_PC5 1 &pcfg_pull_none_drv_level_1>, 1312 /* lcd_d3 */ 1313 <1 RK_PC4 1 &pcfg_pull_none_drv_level_1>, 1314 /* lcd_d4 */ 1315 <1 RK_PC3 1 &pcfg_pull_none_drv_level_1>, 1316 /* lcd_d5 */ 1317 <1 RK_PC2 1 &pcfg_pull_none_drv_level_1>, 1318 /* lcd_d6 */ 1319 <1 RK_PC1 1 &pcfg_pull_none_drv_level_1>, 1320 /* lcd_d7 */ 1321 <1 RK_PC0 1 &pcfg_pull_none_drv_level_1>; 1322 }; 1323 1324 /omit-if-no-ref/ 1325 rgb3x8_pins: rgb3x8-pins { 1326 rockchip,pins = 1327 /* lcd_clk */ 1328 <1 RK_PD3 1 &pcfg_pull_none_drv_level_4>, 1329 /* lcd_d0 */ 1330 <1 RK_PC7 1 &pcfg_pull_none_drv_level_3>, 1331 /* lcd_d1 */ 1332 <1 RK_PC6 1 &pcfg_pull_none_drv_level_3>, 1333 /* lcd_d2 */ 1334 <1 RK_PC5 1 &pcfg_pull_none_drv_level_3>, 1335 /* lcd_d3 */ 1336 <1 RK_PC4 1 &pcfg_pull_none_drv_level_3>, 1337 /* lcd_d4 */ 1338 <1 RK_PC3 1 &pcfg_pull_none_drv_level_3>, 1339 /* lcd_d5 */ 1340 <1 RK_PC2 1 &pcfg_pull_none_drv_level_3>, 1341 /* lcd_d6 */ 1342 <1 RK_PC1 1 &pcfg_pull_none_drv_level_3>, 1343 /* lcd_d7 */ 1344 <1 RK_PC0 1 &pcfg_pull_none_drv_level_3>, 1345 /* lcd_den */ 1346 <1 RK_PD0 1 &pcfg_pull_none_drv_level_3>, 1347 /* lcd_hsync */ 1348 <1 RK_PD1 1 &pcfg_pull_none_drv_level_3>, 1349 /* lcd_vsync */ 1350 <1 RK_PD2 1 &pcfg_pull_none_drv_level_3>; 1351 }; 1352 1353 /omit-if-no-ref/ 1354 rgb565_pins: rgb565-pins { 1355 rockchip,pins = 1356 /* lcd_clk */ 1357 <1 RK_PD3 1 &pcfg_pull_none_drv_level_4>, 1358 /* lcd_d0 */ 1359 <1 RK_PC7 1 &pcfg_pull_none_drv_level_3>, 1360 /* lcd_d1 */ 1361 <1 RK_PC6 1 &pcfg_pull_none_drv_level_3>, 1362 /* lcd_d2 */ 1363 <1 RK_PC5 1 &pcfg_pull_none_drv_level_3>, 1364 /* lcd_d3 */ 1365 <1 RK_PC4 1 &pcfg_pull_none_drv_level_3>, 1366 /* lcd_d4 */ 1367 <1 RK_PC3 1 &pcfg_pull_none_drv_level_3>, 1368 /* lcd_d5 */ 1369 <1 RK_PC2 1 &pcfg_pull_none_drv_level_3>, 1370 /* lcd_d6 */ 1371 <1 RK_PC1 1 &pcfg_pull_none_drv_level_3>, 1372 /* lcd_d7 */ 1373 <1 RK_PC0 1 &pcfg_pull_none_drv_level_3>, 1374 /* lcd_d8 */ 1375 <2 RK_PA0 3 &pcfg_pull_none_drv_level_3>, 1376 /* lcd_d9 */ 1377 <2 RK_PA1 3 &pcfg_pull_none_drv_level_3>, 1378 /* lcd_d10 */ 1379 <2 RK_PA2 3 &pcfg_pull_none_drv_level_3>, 1380 /* lcd_d11 */ 1381 <2 RK_PA3 3 &pcfg_pull_none_drv_level_3>, 1382 /* lcd_d12 */ 1383 <2 RK_PA4 3 &pcfg_pull_none_drv_level_3>, 1384 /* lcd_d13 */ 1385 <2 RK_PA5 3 &pcfg_pull_none_drv_level_3>, 1386 /* lcd_d14 */ 1387 <2 RK_PA6 3 &pcfg_pull_none_drv_level_3>, 1388 /* lcd_d15 */ 1389 <2 RK_PA7 3 &pcfg_pull_none_drv_level_3>, 1390 /* lcd_den */ 1391 <1 RK_PD0 1 &pcfg_pull_none_drv_level_3>, 1392 /* lcd_hsync */ 1393 <1 RK_PD1 1 &pcfg_pull_none_drv_level_3>, 1394 /* lcd_vsync */ 1395 <1 RK_PD2 1 &pcfg_pull_none_drv_level_3>; 1396 }; 1397 }; 1398}; 1399