1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/display/media-bus-format.h> 7 8/ { 9 backlight: backlight { 10 status = "okay"; 11 compatible = "pwm-backlight"; 12 pwms = <&pwm3 0 25000 0>; 13 brightness-levels = < 14 0 1 2 3 4 5 6 7 15 8 9 10 11 12 13 14 15 16 16 17 18 19 20 21 22 23 17 24 25 26 27 28 29 30 31 18 32 33 34 35 36 37 38 39 19 40 41 42 43 44 45 46 47 20 48 49 50 51 52 53 54 55 21 56 57 58 59 60 61 62 63 22 64 65 66 67 68 69 70 71 23 72 73 74 75 76 77 78 79 24 80 81 82 83 84 85 86 87 25 88 89 90 91 92 93 94 95 26 96 97 98 99 100 101 102 103 27 104 105 106 107 108 109 110 111 28 112 113 114 115 116 117 118 119 29 120 121 122 123 124 125 126 127 30 128 129 130 131 132 133 134 135 31 136 137 138 139 140 141 142 143 32 144 145 146 147 148 149 150 151 33 152 153 154 155 156 157 158 159 34 160 161 162 163 164 165 166 167 35 168 169 170 171 172 173 174 175 36 176 177 178 179 180 181 182 183 37 184 185 186 187 188 189 190 191 38 192 193 194 195 196 197 198 199 39 200 201 202 203 204 205 206 207 40 208 209 210 211 212 213 214 215 41 216 217 218 219 220 221 222 223 42 224 225 226 227 228 229 230 231 43 232 233 234 235 236 237 238 239 44 240 241 242 243 244 245 246 247 45 248 249 250 251 252 253 254 255>; 46 default-brightness-level = <200>; 47 }; 48 49 reserved-memory { 50 #address-cells = <1>; 51 #size-cells = <1>; 52 ranges; 53 54 linux,cma { 55 compatible = "shared-dma-pool"; 56 inactive; 57 reusable; 58 size = <0x1000000>; 59 linux,cma-default; 60 }; 61 62 drm_logo: drm-logo@00000000 { 63 compatible = "rockchip,drm-logo"; 64 reg = <0x0 0x0>; 65 }; 66 }; 67}; 68 69&display_subsystem { 70 status = "okay"; 71 logo-memory-region = <&drm_logo>; 72}; 73 74&pwm3 { 75 status = "okay"; 76 pinctrl-names = "active"; 77 pinctrl-0 = <&pwm3m1_pins>; 78}; 79 80&rgb { 81 status = "okay"; 82 rockchip,data-sync-bypass; 83 pinctrl-names = "default"; 84 pinctrl-0 = <&rgb565_pins>; 85 86 /* 87 * 320x480 RGB/MCU screen K350C4516T 88 */ 89 mcu_panel: mcu-panel { 90 /* 91 * MEDIA_BUS_FMT_RGB888_3X8 for serial mcu 92 * MEDIA_BUS_FMT_RGB565_1X16 for parallel mcu 93 */ 94 bus-format = <MEDIA_BUS_FMT_RGB565_1X16>; 95 backlight = <&backlight>; 96 enable-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_LOW>; 97 enable-delay-ms = <20>; 98 reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; 99 reset-value = <0>; 100 reset-delay-ms = <10>; 101 prepare-delay-ms = <20>; 102 unprepare-delay-ms = <20>; 103 disable-delay-ms = <20>; 104 width-mm = <217>; 105 height-mm = <136>; 106 107 // type:0 is cmd, 1 is data 108 panel-init-sequence = [ 109 //type delay num val1 val2 val3 110 00 00 01 e0 111 01 00 01 00 112 01 00 01 07 113 01 00 01 0f 114 01 00 01 0d 115 01 00 01 1b 116 01 00 01 0a 117 01 00 01 3c 118 01 00 01 78 119 01 00 01 4a 120 01 00 01 07 121 01 00 01 0e 122 01 00 01 09 123 01 00 01 1b 124 01 00 01 1e 125 01 00 01 0f 126 00 00 01 e1 127 01 00 01 00 128 01 00 01 22 129 01 00 01 24 130 01 00 01 06 131 01 00 01 12 132 01 00 01 07 133 01 00 01 36 134 01 00 01 47 135 01 00 01 47 136 01 00 01 06 137 01 00 01 0a 138 01 00 01 07 139 01 00 01 30 140 01 00 01 37 141 01 00 01 0f 142 143 00 00 01 c0 144 01 00 01 10 145 01 00 01 10 146 147 00 00 01 c1 148 01 00 01 41 149 150 00 00 01 c5 151 01 00 01 00 152 01 00 01 22 153 01 00 01 80 154 155 00 00 01 36 156 01 00 01 48 157 158 00 00 01 3a //interface pixel format 159 01 00 01 55 // bpp cfg 160 // 3 11 161 // 16 55 162 // 18 66 163 // 24 77 164 165 00 00 01 b0 //interface mode control 166 01 00 01 00 167 168 00 00 01 b1 //frame rate 60hz 169 01 00 01 a0 170 01 00 01 11 171 00 00 01 b4 172 01 00 01 02 173 00 00 01 B6 174 01 00 01 02 175 01 00 01 02 176 177 00 00 01 b7 178 01 00 01 c6 179 180 00 00 01 be 181 01 00 01 00 182 01 00 01 04 183 184 00 00 01 e9 185 01 00 01 00 186 187 00 00 01 f7 188 01 00 01 a9 189 01 00 01 51 190 01 00 01 2c 191 01 00 01 82 192 193 00 78 01 11 194 00 32 01 29 195 00 00 01 2c 196 ]; 197 198 panel-exit-sequence = [ 199 //type delay num val1 val2 val3 200 00 0a 01 28 201 00 78 01 10 202 ]; 203 204 display-timings { 205 native-mode = <&kd050fwfba002_timing>; 206 207 kd050fwfba002_timing: timing0 { 208 clock-frequency = <73174500>; 209 hactive = <320>; 210 vactive = <480>; 211 hback-porch = <10>; 212 hfront-porch = <5>; 213 vback-porch = <10>; 214 vfront-porch = <5>; 215 hsync-len = <10>; 216 vsync-len = <10>; 217 hsync-active = <0>; 218 vsync-active = <0>; 219 de-active = <0>; 220 pixelclk-active = <1>; 221 }; 222 }; 223 224 port { 225 panel_in_rgb: endpoint { 226 remote-endpoint = <&rgb_out_panel>; 227 }; 228 }; 229 }; 230 231 ports { 232 rgb_out: port@1 { 233 reg = <1>; 234 #address-cells = <1>; 235 #size-cells = <0>; 236 237 rgb_out_panel: endpoint@0 { 238 reg = <0>; 239 remote-endpoint = <&panel_in_rgb>; 240 }; 241 }; 242 }; 243}; 244 245&rgb_in_vop { 246 status = "okay"; 247}; 248 249&route_rgb { 250 status = "disabled"; 251}; 252 253/* 254 * The pins of sdmmc1 and lcd are multiplexed 255 */ 256&sdio { 257 status = "disabled"; 258}; 259 260&sdio_pwrseq { 261 status = "disabled"; 262}; 263 264&vop { 265 status = "okay"; 266 267 /* 268 * Default config is as follows: 269 * 270 * mcu-pix-total = <9>; 271 * mcu-cs-pst = <1>; 272 * mcu-cs-pend = <8>; 273 * mcu-rw-pst = <2>; 274 * mcu-rw-pend = <5>; 275 * mcu-hold-mode = <0>; // default set to 0 276 * 277 * Ruduce all parameters because the max vop dclk 278 * is 74.25M in rv1106. 279 */ 280 mcu-timing { 281 mcu-pix-total = <7>; 282 mcu-cs-pst = <1>; 283 mcu-cs-pend = <6>; 284 mcu-rw-pst = <2>; 285 mcu-rw-pend = <5>; 286 287 mcu-hold-mode = <0>; // default set to 0 288 }; 289}; 290