1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include "rv1103g-evb-v11.dts" 9*4882a593Smuzhiyun#include <dt-bindings/display/media-bus-format.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun backlight: backlight { 13*4882a593Smuzhiyun status = "okay"; 14*4882a593Smuzhiyun compatible = "pwm-backlight"; 15*4882a593Smuzhiyun pwms = <&pwm7 0 25000 0>; 16*4882a593Smuzhiyun brightness-levels = < 17*4882a593Smuzhiyun 0 1 2 3 4 5 6 7 18*4882a593Smuzhiyun 8 9 10 11 12 13 14 15 19*4882a593Smuzhiyun 16 17 18 19 20 21 22 23 20*4882a593Smuzhiyun 24 25 26 27 28 29 30 31 21*4882a593Smuzhiyun 32 33 34 35 36 37 38 39 22*4882a593Smuzhiyun 40 41 42 43 44 45 46 47 23*4882a593Smuzhiyun 48 49 50 51 52 53 54 55 24*4882a593Smuzhiyun 56 57 58 59 60 61 62 63 25*4882a593Smuzhiyun 64 65 66 67 68 69 70 71 26*4882a593Smuzhiyun 72 73 74 75 76 77 78 79 27*4882a593Smuzhiyun 80 81 82 83 84 85 86 87 28*4882a593Smuzhiyun 88 89 90 91 92 93 94 95 29*4882a593Smuzhiyun 96 97 98 99 100 101 102 103 30*4882a593Smuzhiyun 104 105 106 107 108 109 110 111 31*4882a593Smuzhiyun 112 113 114 115 116 117 118 119 32*4882a593Smuzhiyun 120 121 122 123 124 125 126 127 33*4882a593Smuzhiyun 128 129 130 131 132 133 134 135 34*4882a593Smuzhiyun 136 137 138 139 140 141 142 143 35*4882a593Smuzhiyun 144 145 146 147 148 149 150 151 36*4882a593Smuzhiyun 152 153 154 155 156 157 158 159 37*4882a593Smuzhiyun 160 161 162 163 164 165 166 167 38*4882a593Smuzhiyun 168 169 170 171 172 173 174 175 39*4882a593Smuzhiyun 176 177 178 179 180 181 182 183 40*4882a593Smuzhiyun 184 185 186 187 188 189 190 191 41*4882a593Smuzhiyun 192 193 194 195 196 197 198 199 42*4882a593Smuzhiyun 200 201 202 203 204 205 206 207 43*4882a593Smuzhiyun 208 209 210 211 212 213 214 215 44*4882a593Smuzhiyun 216 217 218 219 220 221 222 223 45*4882a593Smuzhiyun 224 225 226 227 228 229 230 231 46*4882a593Smuzhiyun 232 233 234 235 236 237 238 239 47*4882a593Smuzhiyun 240 241 242 243 244 245 246 247 48*4882a593Smuzhiyun 248 249 250 251 252 253 254 255>; 49*4882a593Smuzhiyun default-brightness-level = <50>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun reserved-memory { 53*4882a593Smuzhiyun #address-cells = <1>; 54*4882a593Smuzhiyun #size-cells = <1>; 55*4882a593Smuzhiyun ranges; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun linux,cma { 58*4882a593Smuzhiyun compatible = "shared-dma-pool"; 59*4882a593Smuzhiyun inactive; 60*4882a593Smuzhiyun reusable; 61*4882a593Smuzhiyun size = <0x1000000>; 62*4882a593Smuzhiyun linux,cma-default; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun drm_logo: drm-logo@00000000 { 66*4882a593Smuzhiyun compatible = "rockchip,drm-logo"; 67*4882a593Smuzhiyun reg = <0x0 0x0>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun}; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun&display_subsystem { 73*4882a593Smuzhiyun status = "okay"; 74*4882a593Smuzhiyun logo-memory-region = <&drm_logo>; 75*4882a593Smuzhiyun}; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun/* 78*4882a593Smuzhiyun * The pins of i2c4m2 and lcd are multiplexed 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun&i2c4 { 81*4882a593Smuzhiyun status = "disabled"; 82*4882a593Smuzhiyun}; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun&pwm7 { 85*4882a593Smuzhiyun status = "okay"; 86*4882a593Smuzhiyun pinctrl-names = "active"; 87*4882a593Smuzhiyun pinctrl-0 = <&pwm7m2_pins>; 88*4882a593Smuzhiyun}; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun&rgb { 91*4882a593Smuzhiyun status = "okay"; 92*4882a593Smuzhiyun rockchip,data-sync-bypass; 93*4882a593Smuzhiyun pinctrl-names = "default"; 94*4882a593Smuzhiyun pinctrl-0 = <&rgb3x8_pins>; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* 97*4882a593Smuzhiyun * 320x480 RGB/MCU screen K350C4516T 98*4882a593Smuzhiyun */ 99*4882a593Smuzhiyun mcu_panel: mcu-panel { 100*4882a593Smuzhiyun bus-format = <MEDIA_BUS_FMT_RGB888_3X8>; 101*4882a593Smuzhiyun backlight = <&backlight>; 102*4882a593Smuzhiyun enable-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_LOW>; 103*4882a593Smuzhiyun enable-delay-ms = <20>; 104*4882a593Smuzhiyun reset-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_LOW>; 105*4882a593Smuzhiyun reset-value = <0>; 106*4882a593Smuzhiyun reset-delay-ms = <10>; 107*4882a593Smuzhiyun prepare-delay-ms = <20>; 108*4882a593Smuzhiyun unprepare-delay-ms = <20>; 109*4882a593Smuzhiyun disable-delay-ms = <20>; 110*4882a593Smuzhiyun width-mm = <217>; 111*4882a593Smuzhiyun height-mm = <136>; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun // type:0 is cmd, 1 is data 114*4882a593Smuzhiyun panel-init-sequence = [ 115*4882a593Smuzhiyun //type delay num val1 val2 val3 116*4882a593Smuzhiyun 00 00 01 e0 117*4882a593Smuzhiyun 01 00 01 00 118*4882a593Smuzhiyun 01 00 01 07 119*4882a593Smuzhiyun 01 00 01 0f 120*4882a593Smuzhiyun 01 00 01 0d 121*4882a593Smuzhiyun 01 00 01 1b 122*4882a593Smuzhiyun 01 00 01 0a 123*4882a593Smuzhiyun 01 00 01 3c 124*4882a593Smuzhiyun 01 00 01 78 125*4882a593Smuzhiyun 01 00 01 4a 126*4882a593Smuzhiyun 01 00 01 07 127*4882a593Smuzhiyun 01 00 01 0e 128*4882a593Smuzhiyun 01 00 01 09 129*4882a593Smuzhiyun 01 00 01 1b 130*4882a593Smuzhiyun 01 00 01 1e 131*4882a593Smuzhiyun 01 00 01 0f 132*4882a593Smuzhiyun 00 00 01 e1 133*4882a593Smuzhiyun 01 00 01 00 134*4882a593Smuzhiyun 01 00 01 22 135*4882a593Smuzhiyun 01 00 01 24 136*4882a593Smuzhiyun 01 00 01 06 137*4882a593Smuzhiyun 01 00 01 12 138*4882a593Smuzhiyun 01 00 01 07 139*4882a593Smuzhiyun 01 00 01 36 140*4882a593Smuzhiyun 01 00 01 47 141*4882a593Smuzhiyun 01 00 01 47 142*4882a593Smuzhiyun 01 00 01 06 143*4882a593Smuzhiyun 01 00 01 0a 144*4882a593Smuzhiyun 01 00 01 07 145*4882a593Smuzhiyun 01 00 01 30 146*4882a593Smuzhiyun 01 00 01 37 147*4882a593Smuzhiyun 01 00 01 0f 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun 00 00 01 c0 150*4882a593Smuzhiyun 01 00 01 10 151*4882a593Smuzhiyun 01 00 01 10 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun 00 00 01 c1 154*4882a593Smuzhiyun 01 00 01 41 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun 00 00 01 c5 157*4882a593Smuzhiyun 01 00 01 00 158*4882a593Smuzhiyun 01 00 01 22 159*4882a593Smuzhiyun 01 00 01 80 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun 00 00 01 36 162*4882a593Smuzhiyun 01 00 01 48 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun 00 00 01 3a //interface pixel format 165*4882a593Smuzhiyun 01 00 01 77 // bpp cfg 166*4882a593Smuzhiyun // 3 11 167*4882a593Smuzhiyun // 16 55 168*4882a593Smuzhiyun // 18 66 169*4882a593Smuzhiyun // 24 77 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun 00 00 01 b0 //interface mode control 172*4882a593Smuzhiyun 01 00 01 00 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun 00 00 01 b1 //frame rate 60hz 175*4882a593Smuzhiyun 01 00 01 a0 176*4882a593Smuzhiyun 01 00 01 11 177*4882a593Smuzhiyun 00 00 01 b4 178*4882a593Smuzhiyun 01 00 01 02 179*4882a593Smuzhiyun 00 00 01 B6 180*4882a593Smuzhiyun 01 00 01 02 181*4882a593Smuzhiyun 01 00 01 02 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun 00 00 01 b7 184*4882a593Smuzhiyun 01 00 01 c6 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun 00 00 01 be 187*4882a593Smuzhiyun 01 00 01 00 188*4882a593Smuzhiyun 01 00 01 04 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun 00 00 01 e9 191*4882a593Smuzhiyun 01 00 01 00 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun 00 00 01 f7 194*4882a593Smuzhiyun 01 00 01 a9 195*4882a593Smuzhiyun 01 00 01 51 196*4882a593Smuzhiyun 01 00 01 2c 197*4882a593Smuzhiyun 01 00 01 82 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun 00 78 01 11 200*4882a593Smuzhiyun 00 32 01 29 201*4882a593Smuzhiyun 00 00 01 2c 202*4882a593Smuzhiyun ]; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun panel-exit-sequence = [ 205*4882a593Smuzhiyun //type delay num val1 val2 val3 206*4882a593Smuzhiyun 00 0a 01 28 207*4882a593Smuzhiyun 00 78 01 10 208*4882a593Smuzhiyun ]; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun display-timings { 211*4882a593Smuzhiyun native-mode = <&kd050fwfba002_timing>; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun kd050fwfba002_timing: timing0 { 214*4882a593Smuzhiyun clock-frequency = <73174500>; 215*4882a593Smuzhiyun hactive = <320>; 216*4882a593Smuzhiyun vactive = <480>; 217*4882a593Smuzhiyun hback-porch = <10>; 218*4882a593Smuzhiyun hfront-porch = <5>; 219*4882a593Smuzhiyun vback-porch = <10>; 220*4882a593Smuzhiyun vfront-porch = <5>; 221*4882a593Smuzhiyun hsync-len = <10>; 222*4882a593Smuzhiyun vsync-len = <10>; 223*4882a593Smuzhiyun hsync-active = <0>; 224*4882a593Smuzhiyun vsync-active = <0>; 225*4882a593Smuzhiyun de-active = <0>; 226*4882a593Smuzhiyun pixelclk-active = <1>; 227*4882a593Smuzhiyun }; 228*4882a593Smuzhiyun }; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun port { 231*4882a593Smuzhiyun panel_in_rgb: endpoint { 232*4882a593Smuzhiyun remote-endpoint = <&rgb_out_panel>; 233*4882a593Smuzhiyun }; 234*4882a593Smuzhiyun }; 235*4882a593Smuzhiyun }; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun ports { 238*4882a593Smuzhiyun rgb_out: port@1 { 239*4882a593Smuzhiyun reg = <1>; 240*4882a593Smuzhiyun #address-cells = <1>; 241*4882a593Smuzhiyun #size-cells = <0>; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun rgb_out_panel: endpoint@0 { 244*4882a593Smuzhiyun reg = <0>; 245*4882a593Smuzhiyun remote-endpoint = <&panel_in_rgb>; 246*4882a593Smuzhiyun }; 247*4882a593Smuzhiyun }; 248*4882a593Smuzhiyun }; 249*4882a593Smuzhiyun}; 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun&rgb_in_vop { 252*4882a593Smuzhiyun status = "okay"; 253*4882a593Smuzhiyun}; 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun&route_rgb { 256*4882a593Smuzhiyun status = "disabled"; 257*4882a593Smuzhiyun}; 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun/* 260*4882a593Smuzhiyun * The pins of vcc3v3_sd/vcc3v3_wifi and lcd are multiplexed 261*4882a593Smuzhiyun */ 262*4882a593Smuzhiyun&vcc3v3_sd { 263*4882a593Smuzhiyun status = "disabled"; 264*4882a593Smuzhiyun}; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun&vcc3v3_wifi { 267*4882a593Smuzhiyun status = "disabled"; 268*4882a593Smuzhiyun}; 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun&vop { 271*4882a593Smuzhiyun status = "okay"; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun /* 274*4882a593Smuzhiyun * Default config is as follows: 275*4882a593Smuzhiyun * 276*4882a593Smuzhiyun * mcu-pix-total = <9>; 277*4882a593Smuzhiyun * mcu-cs-pst = <1>; 278*4882a593Smuzhiyun * mcu-cs-pend = <8>; 279*4882a593Smuzhiyun * mcu-rw-pst = <2>; 280*4882a593Smuzhiyun * mcu-rw-pend = <5>; 281*4882a593Smuzhiyun * mcu-hold-mode = <0>; // default set to 0 282*4882a593Smuzhiyun * 283*4882a593Smuzhiyun * Ruduce all parameters because the max vop dclk 284*4882a593Smuzhiyun * is 74.25M in rv1106. 285*4882a593Smuzhiyun */ 286*4882a593Smuzhiyun mcu-timing { 287*4882a593Smuzhiyun mcu-pix-total = <7>; 288*4882a593Smuzhiyun mcu-cs-pst = <1>; 289*4882a593Smuzhiyun mcu-cs-pend = <6>; 290*4882a593Smuzhiyun mcu-rw-pst = <2>; 291*4882a593Smuzhiyun mcu-rw-pend = <5>; 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun mcu-hold-mode = <0>; // default set to 0 294*4882a593Smuzhiyun }; 295*4882a593Smuzhiyun}; 296