1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 */ 5 6/dts-v1/; 7 8#include "rv1103g-evb-v11.dts" 9#include <dt-bindings/display/media-bus-format.h> 10 11/ { 12 backlight: backlight { 13 status = "okay"; 14 compatible = "pwm-backlight"; 15 pwms = <&pwm7 0 25000 0>; 16 brightness-levels = < 17 0 1 2 3 4 5 6 7 18 8 9 10 11 12 13 14 15 19 16 17 18 19 20 21 22 23 20 24 25 26 27 28 29 30 31 21 32 33 34 35 36 37 38 39 22 40 41 42 43 44 45 46 47 23 48 49 50 51 52 53 54 55 24 56 57 58 59 60 61 62 63 25 64 65 66 67 68 69 70 71 26 72 73 74 75 76 77 78 79 27 80 81 82 83 84 85 86 87 28 88 89 90 91 92 93 94 95 29 96 97 98 99 100 101 102 103 30 104 105 106 107 108 109 110 111 31 112 113 114 115 116 117 118 119 32 120 121 122 123 124 125 126 127 33 128 129 130 131 132 133 134 135 34 136 137 138 139 140 141 142 143 35 144 145 146 147 148 149 150 151 36 152 153 154 155 156 157 158 159 37 160 161 162 163 164 165 166 167 38 168 169 170 171 172 173 174 175 39 176 177 178 179 180 181 182 183 40 184 185 186 187 188 189 190 191 41 192 193 194 195 196 197 198 199 42 200 201 202 203 204 205 206 207 43 208 209 210 211 212 213 214 215 44 216 217 218 219 220 221 222 223 45 224 225 226 227 228 229 230 231 46 232 233 234 235 236 237 238 239 47 240 241 242 243 244 245 246 247 48 248 249 250 251 252 253 254 255>; 49 default-brightness-level = <50>; 50 }; 51 52 reserved-memory { 53 #address-cells = <1>; 54 #size-cells = <1>; 55 ranges; 56 57 linux,cma { 58 compatible = "shared-dma-pool"; 59 inactive; 60 reusable; 61 size = <0x1000000>; 62 linux,cma-default; 63 }; 64 65 drm_logo: drm-logo@00000000 { 66 compatible = "rockchip,drm-logo"; 67 reg = <0x0 0x0>; 68 }; 69 }; 70}; 71 72&display_subsystem { 73 status = "okay"; 74 logo-memory-region = <&drm_logo>; 75}; 76 77/* 78 * The pins of i2c4m2 and lcd are multiplexed 79 */ 80&i2c4 { 81 status = "disabled"; 82}; 83 84&pwm7 { 85 status = "okay"; 86 pinctrl-names = "active"; 87 pinctrl-0 = <&pwm7m2_pins>; 88}; 89 90&rgb { 91 status = "okay"; 92 rockchip,data-sync-bypass; 93 pinctrl-names = "default"; 94 pinctrl-0 = <&rgb3x8_pins>; 95 96 /* 97 * 320x480 RGB/MCU screen K350C4516T 98 */ 99 mcu_panel: mcu-panel { 100 bus-format = <MEDIA_BUS_FMT_RGB888_3X8>; 101 backlight = <&backlight>; 102 enable-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_LOW>; 103 enable-delay-ms = <20>; 104 reset-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_LOW>; 105 reset-value = <0>; 106 reset-delay-ms = <10>; 107 prepare-delay-ms = <20>; 108 unprepare-delay-ms = <20>; 109 disable-delay-ms = <20>; 110 width-mm = <217>; 111 height-mm = <136>; 112 113 // type:0 is cmd, 1 is data 114 panel-init-sequence = [ 115 //type delay num val1 val2 val3 116 00 00 01 e0 117 01 00 01 00 118 01 00 01 07 119 01 00 01 0f 120 01 00 01 0d 121 01 00 01 1b 122 01 00 01 0a 123 01 00 01 3c 124 01 00 01 78 125 01 00 01 4a 126 01 00 01 07 127 01 00 01 0e 128 01 00 01 09 129 01 00 01 1b 130 01 00 01 1e 131 01 00 01 0f 132 00 00 01 e1 133 01 00 01 00 134 01 00 01 22 135 01 00 01 24 136 01 00 01 06 137 01 00 01 12 138 01 00 01 07 139 01 00 01 36 140 01 00 01 47 141 01 00 01 47 142 01 00 01 06 143 01 00 01 0a 144 01 00 01 07 145 01 00 01 30 146 01 00 01 37 147 01 00 01 0f 148 149 00 00 01 c0 150 01 00 01 10 151 01 00 01 10 152 153 00 00 01 c1 154 01 00 01 41 155 156 00 00 01 c5 157 01 00 01 00 158 01 00 01 22 159 01 00 01 80 160 161 00 00 01 36 162 01 00 01 48 163 164 00 00 01 3a //interface pixel format 165 01 00 01 77 // bpp cfg 166 // 3 11 167 // 16 55 168 // 18 66 169 // 24 77 170 171 00 00 01 b0 //interface mode control 172 01 00 01 00 173 174 00 00 01 b1 //frame rate 60hz 175 01 00 01 a0 176 01 00 01 11 177 00 00 01 b4 178 01 00 01 02 179 00 00 01 B6 180 01 00 01 02 181 01 00 01 02 182 183 00 00 01 b7 184 01 00 01 c6 185 186 00 00 01 be 187 01 00 01 00 188 01 00 01 04 189 190 00 00 01 e9 191 01 00 01 00 192 193 00 00 01 f7 194 01 00 01 a9 195 01 00 01 51 196 01 00 01 2c 197 01 00 01 82 198 199 00 78 01 11 200 00 32 01 29 201 00 00 01 2c 202 ]; 203 204 panel-exit-sequence = [ 205 //type delay num val1 val2 val3 206 00 0a 01 28 207 00 78 01 10 208 ]; 209 210 display-timings { 211 native-mode = <&kd050fwfba002_timing>; 212 213 kd050fwfba002_timing: timing0 { 214 clock-frequency = <73174500>; 215 hactive = <320>; 216 vactive = <480>; 217 hback-porch = <10>; 218 hfront-porch = <5>; 219 vback-porch = <10>; 220 vfront-porch = <5>; 221 hsync-len = <10>; 222 vsync-len = <10>; 223 hsync-active = <0>; 224 vsync-active = <0>; 225 de-active = <0>; 226 pixelclk-active = <1>; 227 }; 228 }; 229 230 port { 231 panel_in_rgb: endpoint { 232 remote-endpoint = <&rgb_out_panel>; 233 }; 234 }; 235 }; 236 237 ports { 238 rgb_out: port@1 { 239 reg = <1>; 240 #address-cells = <1>; 241 #size-cells = <0>; 242 243 rgb_out_panel: endpoint@0 { 244 reg = <0>; 245 remote-endpoint = <&panel_in_rgb>; 246 }; 247 }; 248 }; 249}; 250 251&rgb_in_vop { 252 status = "okay"; 253}; 254 255&route_rgb { 256 status = "disabled"; 257}; 258 259/* 260 * The pins of vcc3v3_sd/vcc3v3_wifi and lcd are multiplexed 261 */ 262&vcc3v3_sd { 263 status = "disabled"; 264}; 265 266&vcc3v3_wifi { 267 status = "disabled"; 268}; 269 270&vop { 271 status = "okay"; 272 273 /* 274 * Default config is as follows: 275 * 276 * mcu-pix-total = <9>; 277 * mcu-cs-pst = <1>; 278 * mcu-cs-pend = <8>; 279 * mcu-rw-pst = <2>; 280 * mcu-rw-pend = <5>; 281 * mcu-hold-mode = <0>; // default set to 0 282 * 283 * Ruduce all parameters because the max vop dclk 284 * is 74.25M in rv1106. 285 */ 286 mcu-timing { 287 mcu-pix-total = <7>; 288 mcu-cs-pst = <1>; 289 mcu-cs-pend = <6>; 290 mcu-rw-pst = <2>; 291 mcu-rw-pend = <5>; 292 293 mcu-hold-mode = <0>; // default set to 0 294 }; 295}; 296