xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/rk3288-android.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This file is dual-licensed: you can use it either under the terms
5*4882a593Smuzhiyun * of the GPL or the X11 license, at your option. Note that this dual
6*4882a593Smuzhiyun * licensing only applies to this file, and not this project as a
7*4882a593Smuzhiyun * whole.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun *  a) This file is free software; you can redistribute it and/or
10*4882a593Smuzhiyun *     modify it under the terms of the GNU General Public License as
11*4882a593Smuzhiyun *     published by the Free Software Foundation; either version 2 of the
12*4882a593Smuzhiyun *     License, or (at your option) any later version.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun *     This file is distributed in the hope that it will be useful,
15*4882a593Smuzhiyun *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16*4882a593Smuzhiyun *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17*4882a593Smuzhiyun *     GNU General Public License for more details.
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * Or, alternatively,
20*4882a593Smuzhiyun *
21*4882a593Smuzhiyun *  b) Permission is hereby granted, free of charge, to any person
22*4882a593Smuzhiyun *     obtaining a copy of this software and associated documentation
23*4882a593Smuzhiyun *     files (the "Software"), to deal in the Software without
24*4882a593Smuzhiyun *     restriction, including without limitation the rights to use,
25*4882a593Smuzhiyun *     copy, modify, merge, publish, distribute, sublicense, and/or
26*4882a593Smuzhiyun *     sell copies of the Software, and to permit persons to whom the
27*4882a593Smuzhiyun *     Software is furnished to do so, subject to the following
28*4882a593Smuzhiyun *     conditions:
29*4882a593Smuzhiyun *
30*4882a593Smuzhiyun *     The above copyright notice and this permission notice shall be
31*4882a593Smuzhiyun *     included in all copies or substantial portions of the Software.
32*4882a593Smuzhiyun *
33*4882a593Smuzhiyun *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34*4882a593Smuzhiyun *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35*4882a593Smuzhiyun *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36*4882a593Smuzhiyun *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37*4882a593Smuzhiyun *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38*4882a593Smuzhiyun *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39*4882a593Smuzhiyun *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40*4882a593Smuzhiyun *     OTHER DEALINGS IN THE SOFTWARE.
41*4882a593Smuzhiyun */
42*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h>
43*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
44*4882a593Smuzhiyun#include <dt-bindings/soc/rockchip-system-status.h>
45*4882a593Smuzhiyun#include "rk3288-dram-default-timing.dtsi"
46*4882a593Smuzhiyun#include <dt-bindings/display/media-bus-format.h>
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun/ {
49*4882a593Smuzhiyun	chosen: chosen {
50*4882a593Smuzhiyun		bootargs = "earlycon=uart8250,mmio32,0xff690000 vmalloc=496M";
51*4882a593Smuzhiyun	};
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun	cpuinfo {
54*4882a593Smuzhiyun		compatible = "rockchip,cpuinfo";
55*4882a593Smuzhiyun		nvmem-cells = <&efuse_id>;
56*4882a593Smuzhiyun		nvmem-cell-names = "id";
57*4882a593Smuzhiyun	};
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun	/delete-node/ dmc@ff610000;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun	dfi: dfi {
62*4882a593Smuzhiyun		compatible = "rockchip,rk3288-dfi";
63*4882a593Smuzhiyun		rockchip,pmu = <&pmu>;
64*4882a593Smuzhiyun		rockchip,grf = <&grf>;
65*4882a593Smuzhiyun		status = "disabled";
66*4882a593Smuzhiyun	};
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun	dmc: dmc {
69*4882a593Smuzhiyun		compatible = "rockchip,rk3288-dmc";
70*4882a593Smuzhiyun		devfreq-events = <&dfi>;
71*4882a593Smuzhiyun		clocks = <&cru SCLK_DDRCLK>, <&cru PCLK_PUBL0>,
72*4882a593Smuzhiyun			 <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL1>,
73*4882a593Smuzhiyun			 <&cru PCLK_DDRUPCTL1>;
74*4882a593Smuzhiyun		clock-names = "dmc_clk", "pclk_phy0", "pclk_upctl0",
75*4882a593Smuzhiyun			      "pclk_phy1", "pclk_upctl1";
76*4882a593Smuzhiyun		upthreshold = <55>;
77*4882a593Smuzhiyun		downdifferential = <10>;
78*4882a593Smuzhiyun		operating-points-v2 = <&dmc_opp_table>;
79*4882a593Smuzhiyun		vop-dclk-mode = <0>;
80*4882a593Smuzhiyun		min-cpu-freq = <600000>;
81*4882a593Smuzhiyun		rockchip,ddr_timing = <&ddr_timing>;
82*4882a593Smuzhiyun		system-status-freq = <
83*4882a593Smuzhiyun			/*system status		freq(KHz)*/
84*4882a593Smuzhiyun			SYS_STATUS_NORMAL	396000
85*4882a593Smuzhiyun			SYS_STATUS_REBOOT	396000
86*4882a593Smuzhiyun			SYS_STATUS_SUSPEND	192000
87*4882a593Smuzhiyun			SYS_STATUS_VIDEO_1080P	300000
88*4882a593Smuzhiyun			SYS_STATUS_VIDEO_4K	528000
89*4882a593Smuzhiyun			SYS_STATUS_VIDEO_4K_10B	528000
90*4882a593Smuzhiyun			SYS_STATUS_PERFORMANCE	528000
91*4882a593Smuzhiyun			SYS_STATUS_BOOST	396000
92*4882a593Smuzhiyun			SYS_STATUS_DUALVIEW	528000
93*4882a593Smuzhiyun			SYS_STATUS_ISP		528000
94*4882a593Smuzhiyun		>;
95*4882a593Smuzhiyun		auto-min-freq = <396000>;
96*4882a593Smuzhiyun		auto-freq-en = <0>;
97*4882a593Smuzhiyun		status = "diasbled";
98*4882a593Smuzhiyun	};
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun	dmc_opp_table: opp_table2 {
101*4882a593Smuzhiyun		compatible = "operating-points-v2";
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun		opp-192000000 {
104*4882a593Smuzhiyun			opp-hz = /bits/ 64 <192000000>;
105*4882a593Smuzhiyun			opp-microvolt = <1100000>;
106*4882a593Smuzhiyun		};
107*4882a593Smuzhiyun		opp-300000000 {
108*4882a593Smuzhiyun			opp-hz = /bits/ 64 <300000000>;
109*4882a593Smuzhiyun			opp-microvolt = <1100000>;
110*4882a593Smuzhiyun		};
111*4882a593Smuzhiyun		opp-396000000 {
112*4882a593Smuzhiyun			opp-hz = /bits/ 64 <396000000>;
113*4882a593Smuzhiyun			opp-microvolt = <1100000>;
114*4882a593Smuzhiyun		};
115*4882a593Smuzhiyun		opp-528000000 {
116*4882a593Smuzhiyun			opp-hz = /bits/ 64 <528000000>;
117*4882a593Smuzhiyun			opp-microvolt = <1150000>;
118*4882a593Smuzhiyun		};
119*4882a593Smuzhiyun	};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun	reserved-memory {
122*4882a593Smuzhiyun		ramoops: ramoops@8000000 {
123*4882a593Smuzhiyun			compatible = "ramoops";
124*4882a593Smuzhiyun			reg = <0x0 0x8000000 0x0 0xF0000>;
125*4882a593Smuzhiyun			record-size = <0x20000>;
126*4882a593Smuzhiyun			console-size = <0x80000>;
127*4882a593Smuzhiyun			ftrace-size = <0x00000>;
128*4882a593Smuzhiyun			pmsg-size = <0x50000>;
129*4882a593Smuzhiyun		};
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun		drm_logo: drm-logo@00000000 {
132*4882a593Smuzhiyun			compatible = "rockchip,drm-logo";
133*4882a593Smuzhiyun			reg = <0x0 0x0 0x0 0x0>;
134*4882a593Smuzhiyun		};
135*4882a593Smuzhiyun	};
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun	fiq-debugger {
138*4882a593Smuzhiyun		compatible = "rockchip,fiq-debugger";
139*4882a593Smuzhiyun		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
140*4882a593Smuzhiyun		rockchip,serial-id = <2>;
141*4882a593Smuzhiyun		rockchip,wake-irq = <0>;
142*4882a593Smuzhiyun		rockchip,irq-mode-enable = <0>;  /* If enable uart uses irq instead of fiq */
143*4882a593Smuzhiyun		rockchip,baudrate = <115200>;  /* Only 115200 and 1500000 */
144*4882a593Smuzhiyun		pinctrl-names = "default";
145*4882a593Smuzhiyun		pinctrl-0 = <&uart2_xfer>;
146*4882a593Smuzhiyun	};
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun	firmware {
149*4882a593Smuzhiyun		optee: optee {
150*4882a593Smuzhiyun			compatible = "linaro,optee-tz";
151*4882a593Smuzhiyun			method = "smc";
152*4882a593Smuzhiyun		};
153*4882a593Smuzhiyun	};
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun	/delete-node/ timer@ff810000;
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun	display-subsystem {
158*4882a593Smuzhiyun		status = "okay";
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun		ports = <&vopb_out>, <&vopl_out>;
161*4882a593Smuzhiyun		logo-memory-region = <&drm_logo>;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun		route {
164*4882a593Smuzhiyun			route_edp: route-edp {
165*4882a593Smuzhiyun				status = "disabled";
166*4882a593Smuzhiyun				logo,uboot = "logo.bmp";
167*4882a593Smuzhiyun				logo,kernel = "logo_kernel.bmp";
168*4882a593Smuzhiyun				logo,mode = "center";
169*4882a593Smuzhiyun				charge_logo,mode = "center";
170*4882a593Smuzhiyun				connect = <&vopl_out_edp>;
171*4882a593Smuzhiyun			};
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun			route_dsi0: route-dsi0 {
174*4882a593Smuzhiyun				status = "disabled";
175*4882a593Smuzhiyun				logo,uboot = "logo.bmp";
176*4882a593Smuzhiyun				logo,kernel = "logo_kernel.bmp";
177*4882a593Smuzhiyun				logo,mode = "center";
178*4882a593Smuzhiyun				charge_logo,mode = "center";
179*4882a593Smuzhiyun				connect = <&vopl_out_dsi0>;
180*4882a593Smuzhiyun			};
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun			route_lvds: route-lvds {
183*4882a593Smuzhiyun				status = "disabled";
184*4882a593Smuzhiyun				logo,uboot = "logo.bmp";
185*4882a593Smuzhiyun				logo,kernel = "logo_kernel.bmp";
186*4882a593Smuzhiyun				logo,mode = "center";
187*4882a593Smuzhiyun				charge_logo,mode = "center";
188*4882a593Smuzhiyun				connect = <&vopl_out_lvds>;
189*4882a593Smuzhiyun			};
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun			route_hdmi: route-hdmi {
192*4882a593Smuzhiyun				status = "disabled";
193*4882a593Smuzhiyun				logo,uboot = "logo.bmp";
194*4882a593Smuzhiyun				logo,kernel = "logo_kernel.bmp";
195*4882a593Smuzhiyun				logo,mode = "center";
196*4882a593Smuzhiyun				charge_logo,mode = "center";
197*4882a593Smuzhiyun				connect = <&vopb_out_hdmi>;
198*4882a593Smuzhiyun			};
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun			route_rgb: route-rgb {
201*4882a593Smuzhiyun				status = "disabled";
202*4882a593Smuzhiyun				logo,uboot = "logo.bmp";
203*4882a593Smuzhiyun				logo,kernel = "logo_kernel.bmp";
204*4882a593Smuzhiyun				logo,mode = "center";
205*4882a593Smuzhiyun				charge_logo,mode = "center";
206*4882a593Smuzhiyun				connect = <&vopl_out_rgb>;
207*4882a593Smuzhiyun			};
208*4882a593Smuzhiyun		};
209*4882a593Smuzhiyun	};
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun	nandc0: nandc@ff400000 {
212*4882a593Smuzhiyun		compatible = "rockchip,rk-nandc";
213*4882a593Smuzhiyun		reg = <0x0 0xff400000 0x0 0x4000>;
214*4882a593Smuzhiyun		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
215*4882a593Smuzhiyun		nandc_id = <0>;
216*4882a593Smuzhiyun		clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
217*4882a593Smuzhiyun		clock-names = "clk_nandc", "hclk_nandc";
218*4882a593Smuzhiyun		status = "okay";
219*4882a593Smuzhiyun	};
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun	hdmi_analog_sound: hdmi-analog-sound {
222*4882a593Smuzhiyun		status = "disabled";
223*4882a593Smuzhiyun		compatible = "rockchip,rk3288-hdmi-analog",
224*4882a593Smuzhiyun				"rockchip,rk3368-hdmi-analog";
225*4882a593Smuzhiyun		rockchip,model = "rockchip,rt5640-codec";
226*4882a593Smuzhiyun		rockchip,cpu = <&i2s>;
227*4882a593Smuzhiyun		//rockchip,codec = <&rt5640>, <&hdmi>;
228*4882a593Smuzhiyun		rockchip,codec = <&hdmi>;
229*4882a593Smuzhiyun		rockchip,widgets =
230*4882a593Smuzhiyun			"Microphone", "Microphone Jack",
231*4882a593Smuzhiyun			"Headphone", "Headphone Jack";
232*4882a593Smuzhiyun		rockchip,routing =
233*4882a593Smuzhiyun			"MIC1", "Microphone Jack",
234*4882a593Smuzhiyun			"MIC2", "Microphone Jack",
235*4882a593Smuzhiyun			"Microphone Jack", "micbias1",
236*4882a593Smuzhiyun			"Headphone Jack", "HPOL",
237*4882a593Smuzhiyun			"Headphone Jack", "HPOR";
238*4882a593Smuzhiyun	};
239*4882a593Smuzhiyun};
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun&dmac_bus_s {
242*4882a593Smuzhiyun	/* change to non-secure dmac */
243*4882a593Smuzhiyun	reg = <0x0 0xff600000 0x0 0x4000>;
244*4882a593Smuzhiyun};
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun&dsi0 {
247*4882a593Smuzhiyun	panel@0 {
248*4882a593Smuzhiyun		reg = <0>;
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun		ports {
251*4882a593Smuzhiyun			#address-cells = <1>;
252*4882a593Smuzhiyun			#size-cells = <0>;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun			port@0 {
255*4882a593Smuzhiyun				reg = <0>;
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun				panel_in_dsi: endpoint {
258*4882a593Smuzhiyun					remote-endpoint = <&dsi_out_panel>;
259*4882a593Smuzhiyun				};
260*4882a593Smuzhiyun			};
261*4882a593Smuzhiyun		};
262*4882a593Smuzhiyun	};
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun	ports {
265*4882a593Smuzhiyun		#address-cells = <1>;
266*4882a593Smuzhiyun		#size-cells = <0>;
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun		port@1 {
269*4882a593Smuzhiyun			reg = <1>;
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun			dsi_out_panel: endpoint {
272*4882a593Smuzhiyun				remote-endpoint = <&panel_in_dsi>;
273*4882a593Smuzhiyun			};
274*4882a593Smuzhiyun		};
275*4882a593Smuzhiyun	};
276*4882a593Smuzhiyun};
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun&efuse {
279*4882a593Smuzhiyun	compatible = "rockchip,rk3288-secure-efuse";
280*4882a593Smuzhiyun};
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun&iep {
283*4882a593Smuzhiyun	status = "okay";
284*4882a593Smuzhiyun};
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun&iep_mmu {
287*4882a593Smuzhiyun	status = "okay";
288*4882a593Smuzhiyun};
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun&dsi0_in_vopb {
291*4882a593Smuzhiyun	status = "disabled";
292*4882a593Smuzhiyun};
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun&edp_in_vopb {
295*4882a593Smuzhiyun	status = "disabled";
296*4882a593Smuzhiyun};
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun&hdmi_in_vopl {
299*4882a593Smuzhiyun	status = "disabled";
300*4882a593Smuzhiyun};
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun&mpp_srv {
303*4882a593Smuzhiyun	status = "okay";
304*4882a593Smuzhiyun};
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun&hevc {
307*4882a593Smuzhiyun	status = "okay";
308*4882a593Smuzhiyun};
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun&hevc_mmu {
311*4882a593Smuzhiyun	status = "okay";
312*4882a593Smuzhiyun};
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun&rga {
315*4882a593Smuzhiyun	compatible = "rockchip,rga2";
316*4882a593Smuzhiyun	clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
317*4882a593Smuzhiyun	clock-names = "aclk_rga", "hclk_rga", "clk_rga";
318*4882a593Smuzhiyun	assigned-clocks = <&cru ACLK_RGA>, <&cru SCLK_RGA>;
319*4882a593Smuzhiyun	assigned-clock-rates = <300000000>, <300000000>;
320*4882a593Smuzhiyun	status = "okay";
321*4882a593Smuzhiyun};
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun&rng {
324*4882a593Smuzhiyun	status = "okay";
325*4882a593Smuzhiyun};
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun&uart2 {
328*4882a593Smuzhiyun	status = "disabled";
329*4882a593Smuzhiyun};
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun&pinctrl {
332*4882a593Smuzhiyun	buttons {
333*4882a593Smuzhiyun		pwrbtn: pwrbtn {
334*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
335*4882a593Smuzhiyun		};
336*4882a593Smuzhiyun	};
337*4882a593Smuzhiyun};
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun&vdpu {
340*4882a593Smuzhiyun	status = "okay";
341*4882a593Smuzhiyun};
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun&vepu {
344*4882a593Smuzhiyun	status = "okay";
345*4882a593Smuzhiyun};
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun&vopb {
348*4882a593Smuzhiyun	support-multi-area;
349*4882a593Smuzhiyun};
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun&vopl {
352*4882a593Smuzhiyun	support-multi-area;
353*4882a593Smuzhiyun};
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun&video_phy {
356*4882a593Smuzhiyun	status = "okay";
357*4882a593Smuzhiyun};
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun&vpu_mmu {
360*4882a593Smuzhiyun	status = "okay";
361*4882a593Smuzhiyun};
362