1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42#include <dt-bindings/pwm/pwm.h> 43#include <dt-bindings/input/input.h> 44#include <dt-bindings/soc/rockchip-system-status.h> 45#include "rk3288-dram-default-timing.dtsi" 46#include <dt-bindings/display/media-bus-format.h> 47 48/ { 49 chosen: chosen { 50 bootargs = "earlycon=uart8250,mmio32,0xff690000 vmalloc=496M"; 51 }; 52 53 cpuinfo { 54 compatible = "rockchip,cpuinfo"; 55 nvmem-cells = <&efuse_id>; 56 nvmem-cell-names = "id"; 57 }; 58 59 /delete-node/ dmc@ff610000; 60 61 dfi: dfi { 62 compatible = "rockchip,rk3288-dfi"; 63 rockchip,pmu = <&pmu>; 64 rockchip,grf = <&grf>; 65 status = "disabled"; 66 }; 67 68 dmc: dmc { 69 compatible = "rockchip,rk3288-dmc"; 70 devfreq-events = <&dfi>; 71 clocks = <&cru SCLK_DDRCLK>, <&cru PCLK_PUBL0>, 72 <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL1>, 73 <&cru PCLK_DDRUPCTL1>; 74 clock-names = "dmc_clk", "pclk_phy0", "pclk_upctl0", 75 "pclk_phy1", "pclk_upctl1"; 76 upthreshold = <55>; 77 downdifferential = <10>; 78 operating-points-v2 = <&dmc_opp_table>; 79 vop-dclk-mode = <0>; 80 min-cpu-freq = <600000>; 81 rockchip,ddr_timing = <&ddr_timing>; 82 system-status-freq = < 83 /*system status freq(KHz)*/ 84 SYS_STATUS_NORMAL 396000 85 SYS_STATUS_REBOOT 396000 86 SYS_STATUS_SUSPEND 192000 87 SYS_STATUS_VIDEO_1080P 300000 88 SYS_STATUS_VIDEO_4K 528000 89 SYS_STATUS_VIDEO_4K_10B 528000 90 SYS_STATUS_PERFORMANCE 528000 91 SYS_STATUS_BOOST 396000 92 SYS_STATUS_DUALVIEW 528000 93 SYS_STATUS_ISP 528000 94 >; 95 auto-min-freq = <396000>; 96 auto-freq-en = <0>; 97 status = "diasbled"; 98 }; 99 100 dmc_opp_table: opp_table2 { 101 compatible = "operating-points-v2"; 102 103 opp-192000000 { 104 opp-hz = /bits/ 64 <192000000>; 105 opp-microvolt = <1100000>; 106 }; 107 opp-300000000 { 108 opp-hz = /bits/ 64 <300000000>; 109 opp-microvolt = <1100000>; 110 }; 111 opp-396000000 { 112 opp-hz = /bits/ 64 <396000000>; 113 opp-microvolt = <1100000>; 114 }; 115 opp-528000000 { 116 opp-hz = /bits/ 64 <528000000>; 117 opp-microvolt = <1150000>; 118 }; 119 }; 120 121 reserved-memory { 122 ramoops: ramoops@8000000 { 123 compatible = "ramoops"; 124 reg = <0x0 0x8000000 0x0 0xF0000>; 125 record-size = <0x20000>; 126 console-size = <0x80000>; 127 ftrace-size = <0x00000>; 128 pmsg-size = <0x50000>; 129 }; 130 131 drm_logo: drm-logo@00000000 { 132 compatible = "rockchip,drm-logo"; 133 reg = <0x0 0x0 0x0 0x0>; 134 }; 135 }; 136 137 fiq-debugger { 138 compatible = "rockchip,fiq-debugger"; 139 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 140 rockchip,serial-id = <2>; 141 rockchip,wake-irq = <0>; 142 rockchip,irq-mode-enable = <0>; /* If enable uart uses irq instead of fiq */ 143 rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ 144 pinctrl-names = "default"; 145 pinctrl-0 = <&uart2_xfer>; 146 }; 147 148 firmware { 149 optee: optee { 150 compatible = "linaro,optee-tz"; 151 method = "smc"; 152 }; 153 }; 154 155 /delete-node/ timer@ff810000; 156 157 display-subsystem { 158 status = "okay"; 159 160 ports = <&vopb_out>, <&vopl_out>; 161 logo-memory-region = <&drm_logo>; 162 163 route { 164 route_edp: route-edp { 165 status = "disabled"; 166 logo,uboot = "logo.bmp"; 167 logo,kernel = "logo_kernel.bmp"; 168 logo,mode = "center"; 169 charge_logo,mode = "center"; 170 connect = <&vopl_out_edp>; 171 }; 172 173 route_dsi0: route-dsi0 { 174 status = "disabled"; 175 logo,uboot = "logo.bmp"; 176 logo,kernel = "logo_kernel.bmp"; 177 logo,mode = "center"; 178 charge_logo,mode = "center"; 179 connect = <&vopl_out_dsi0>; 180 }; 181 182 route_lvds: route-lvds { 183 status = "disabled"; 184 logo,uboot = "logo.bmp"; 185 logo,kernel = "logo_kernel.bmp"; 186 logo,mode = "center"; 187 charge_logo,mode = "center"; 188 connect = <&vopl_out_lvds>; 189 }; 190 191 route_hdmi: route-hdmi { 192 status = "disabled"; 193 logo,uboot = "logo.bmp"; 194 logo,kernel = "logo_kernel.bmp"; 195 logo,mode = "center"; 196 charge_logo,mode = "center"; 197 connect = <&vopb_out_hdmi>; 198 }; 199 200 route_rgb: route-rgb { 201 status = "disabled"; 202 logo,uboot = "logo.bmp"; 203 logo,kernel = "logo_kernel.bmp"; 204 logo,mode = "center"; 205 charge_logo,mode = "center"; 206 connect = <&vopl_out_rgb>; 207 }; 208 }; 209 }; 210 211 nandc0: nandc@ff400000 { 212 compatible = "rockchip,rk-nandc"; 213 reg = <0x0 0xff400000 0x0 0x4000>; 214 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 215 nandc_id = <0>; 216 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>; 217 clock-names = "clk_nandc", "hclk_nandc"; 218 status = "okay"; 219 }; 220 221 hdmi_analog_sound: hdmi-analog-sound { 222 status = "disabled"; 223 compatible = "rockchip,rk3288-hdmi-analog", 224 "rockchip,rk3368-hdmi-analog"; 225 rockchip,model = "rockchip,rt5640-codec"; 226 rockchip,cpu = <&i2s>; 227 //rockchip,codec = <&rt5640>, <&hdmi>; 228 rockchip,codec = <&hdmi>; 229 rockchip,widgets = 230 "Microphone", "Microphone Jack", 231 "Headphone", "Headphone Jack"; 232 rockchip,routing = 233 "MIC1", "Microphone Jack", 234 "MIC2", "Microphone Jack", 235 "Microphone Jack", "micbias1", 236 "Headphone Jack", "HPOL", 237 "Headphone Jack", "HPOR"; 238 }; 239}; 240 241&dmac_bus_s { 242 /* change to non-secure dmac */ 243 reg = <0x0 0xff600000 0x0 0x4000>; 244}; 245 246&dsi0 { 247 panel@0 { 248 reg = <0>; 249 250 ports { 251 #address-cells = <1>; 252 #size-cells = <0>; 253 254 port@0 { 255 reg = <0>; 256 257 panel_in_dsi: endpoint { 258 remote-endpoint = <&dsi_out_panel>; 259 }; 260 }; 261 }; 262 }; 263 264 ports { 265 #address-cells = <1>; 266 #size-cells = <0>; 267 268 port@1 { 269 reg = <1>; 270 271 dsi_out_panel: endpoint { 272 remote-endpoint = <&panel_in_dsi>; 273 }; 274 }; 275 }; 276}; 277 278&efuse { 279 compatible = "rockchip,rk3288-secure-efuse"; 280}; 281 282&iep { 283 status = "okay"; 284}; 285 286&iep_mmu { 287 status = "okay"; 288}; 289 290&dsi0_in_vopb { 291 status = "disabled"; 292}; 293 294&edp_in_vopb { 295 status = "disabled"; 296}; 297 298&hdmi_in_vopl { 299 status = "disabled"; 300}; 301 302&mpp_srv { 303 status = "okay"; 304}; 305 306&hevc { 307 status = "okay"; 308}; 309 310&hevc_mmu { 311 status = "okay"; 312}; 313 314&rga { 315 compatible = "rockchip,rga2"; 316 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; 317 clock-names = "aclk_rga", "hclk_rga", "clk_rga"; 318 assigned-clocks = <&cru ACLK_RGA>, <&cru SCLK_RGA>; 319 assigned-clock-rates = <300000000>, <300000000>; 320 status = "okay"; 321}; 322 323&rng { 324 status = "okay"; 325}; 326 327&uart2 { 328 status = "disabled"; 329}; 330 331&pinctrl { 332 buttons { 333 pwrbtn: pwrbtn { 334 rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; 335 }; 336 }; 337}; 338 339&vdpu { 340 status = "okay"; 341}; 342 343&vepu { 344 status = "okay"; 345}; 346 347&vopb { 348 support-multi-area; 349}; 350 351&vopl { 352 support-multi-area; 353}; 354 355&video_phy { 356 status = "okay"; 357}; 358 359&vpu_mmu { 360 status = "okay"; 361}; 362
