1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 3#include <dt-bindings/gpio/gpio.h> 4#include <dt-bindings/interrupt-controller/irq.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/pinctrl/rockchip.h> 7#include <dt-bindings/clock/rk3228-cru.h> 8#include <dt-bindings/thermal/thermal.h> 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 interrupt-parent = <&gic>; 15 16 aliases { 17 ethernet0 = &gmac; 18 gpio0 = &gpio0; 19 gpio1 = &gpio1; 20 gpio2 = &gpio2; 21 gpio3 = &gpio3; 22 serial0 = &uart0; 23 serial1 = &uart1; 24 serial2 = &uart2; 25 spi0 = &spi0; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 cpu0: cpu@f00 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a7"; 35 reg = <0xf00>; 36 resets = <&cru SRST_CORE0>; 37 operating-points-v2 = <&cpu0_opp_table>; 38 #cooling-cells = <2>; /* min followed by max */ 39 clock-latency = <40000>; 40 clocks = <&cru ARMCLK>; 41 enable-method = "psci"; 42 }; 43 44 cpu1: cpu@f01 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a7"; 47 reg = <0xf01>; 48 resets = <&cru SRST_CORE1>; 49 operating-points-v2 = <&cpu0_opp_table>; 50 #cooling-cells = <2>; /* min followed by max */ 51 enable-method = "psci"; 52 }; 53 54 cpu2: cpu@f02 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a7"; 57 reg = <0xf02>; 58 resets = <&cru SRST_CORE2>; 59 operating-points-v2 = <&cpu0_opp_table>; 60 #cooling-cells = <2>; /* min followed by max */ 61 enable-method = "psci"; 62 }; 63 64 cpu3: cpu@f03 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a7"; 67 reg = <0xf03>; 68 resets = <&cru SRST_CORE3>; 69 operating-points-v2 = <&cpu0_opp_table>; 70 #cooling-cells = <2>; /* min followed by max */ 71 enable-method = "psci"; 72 }; 73 }; 74 75 cpu0_opp_table: opp_table0 { 76 compatible = "operating-points-v2"; 77 opp-shared; 78 79 opp-408000000 { 80 opp-hz = /bits/ 64 <408000000>; 81 opp-microvolt = <950000>; 82 clock-latency-ns = <40000>; 83 opp-suspend; 84 }; 85 opp-600000000 { 86 opp-hz = /bits/ 64 <600000000>; 87 opp-microvolt = <975000>; 88 }; 89 opp-816000000 { 90 opp-hz = /bits/ 64 <816000000>; 91 opp-microvolt = <1000000>; 92 }; 93 opp-1008000000 { 94 opp-hz = /bits/ 64 <1008000000>; 95 opp-microvolt = <1175000>; 96 }; 97 opp-1200000000 { 98 opp-hz = /bits/ 64 <1200000000>; 99 opp-microvolt = <1275000>; 100 }; 101 }; 102 103 amba: bus { 104 compatible = "simple-bus"; 105 #address-cells = <1>; 106 #size-cells = <1>; 107 ranges; 108 109 pdma: pdma@110f0000 { 110 compatible = "arm,pl330", "arm,primecell"; 111 reg = <0x110f0000 0x4000>; 112 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 114 #dma-cells = <1>; 115 arm,pl330-periph-burst; 116 clocks = <&cru ACLK_DMAC>; 117 clock-names = "apb_pclk"; 118 }; 119 }; 120 121 arm-pmu { 122 compatible = "arm,cortex-a7-pmu"; 123 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 127 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 128 }; 129 130 psci { 131 compatible = "arm,psci-1.0", "arm,psci-0.2"; 132 method = "smc"; 133 }; 134 135 timer { 136 compatible = "arm,armv7-timer"; 137 arm,cpu-registers-not-fw-configured; 138 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 139 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 140 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 141 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 142 clock-frequency = <24000000>; 143 }; 144 145 xin24m: oscillator { 146 compatible = "fixed-clock"; 147 clock-frequency = <24000000>; 148 clock-output-names = "xin24m"; 149 #clock-cells = <0>; 150 }; 151 152 display_subsystem: display-subsystem { 153 compatible = "rockchip,display-subsystem"; 154 ports = <&vop_out>; 155 }; 156 157 i2s1: i2s1@100b0000 { 158 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 159 reg = <0x100b0000 0x4000>; 160 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 161 clock-names = "i2s_clk", "i2s_hclk"; 162 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 163 dmas = <&pdma 14>, <&pdma 15>; 164 dma-names = "tx", "rx"; 165 resets = <&cru SRST_I2S1>; 166 reset-names = "reset-m"; 167 pinctrl-names = "default"; 168 pinctrl-0 = <&i2s1_bus>; 169 status = "disabled"; 170 }; 171 172 i2s0: i2s0@100c0000 { 173 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 174 reg = <0x100c0000 0x4000>; 175 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 176 clock-names = "i2s_clk", "i2s_hclk"; 177 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 178 dmas = <&pdma 11>, <&pdma 12>; 179 dma-names = "tx", "rx"; 180 resets = <&cru SRST_I2S0>; 181 reset-names = "reset-m"; 182 status = "disabled"; 183 }; 184 185 spdif: spdif@100d0000 { 186 compatible = "rockchip,rk3228-spdif"; 187 reg = <0x100d0000 0x1000>; 188 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 189 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 190 clock-names = "mclk", "hclk"; 191 dmas = <&pdma 10>; 192 dma-names = "tx"; 193 pinctrl-names = "default"; 194 pinctrl-0 = <&spdif_tx>; 195 status = "disabled"; 196 }; 197 198 i2s2: i2s2@100e0000 { 199 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 200 reg = <0x100e0000 0x4000>; 201 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 202 clock-names = "i2s_clk", "i2s_hclk"; 203 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 204 dmas = <&pdma 0>, <&pdma 1>; 205 dma-names = "tx", "rx"; 206 resets = <&cru SRST_I2S2>; 207 reset-names = "reset-m"; 208 status = "disabled"; 209 }; 210 211 grf: syscon@11000000 { 212 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd"; 213 reg = <0x11000000 0x1000>; 214 #address-cells = <1>; 215 #size-cells = <1>; 216 217 io_domains: io-domains { 218 compatible = "rockchip,rk3228-io-voltage-domain"; 219 status = "disabled"; 220 }; 221 222 u2phy0: usb2-phy@760 { 223 compatible = "rockchip,rk3228-usb2phy"; 224 reg = <0x0760 0x0c>; 225 clocks = <&cru SCLK_OTGPHY0>; 226 clock-names = "phyclk"; 227 clock-output-names = "usb480m_phy0"; 228 #clock-cells = <0>; 229 status = "disabled"; 230 231 u2phy0_otg: otg-port { 232 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 235 interrupt-names = "otg-bvalid", "otg-id", 236 "linestate"; 237 #phy-cells = <0>; 238 status = "disabled"; 239 }; 240 241 u2phy0_host: host-port { 242 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 243 interrupt-names = "linestate"; 244 #phy-cells = <0>; 245 status = "disabled"; 246 }; 247 }; 248 249 u2phy1: usb2-phy@800 { 250 compatible = "rockchip,rk3228-usb2phy"; 251 reg = <0x0800 0x0c>; 252 clocks = <&cru SCLK_OTGPHY1>; 253 clock-names = "phyclk"; 254 clock-output-names = "usb480m_phy1"; 255 #clock-cells = <0>; 256 status = "disabled"; 257 258 u2phy1_otg: otg-port { 259 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 260 interrupt-names = "linestate"; 261 #phy-cells = <0>; 262 status = "disabled"; 263 }; 264 265 u2phy1_host: host-port { 266 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 267 interrupt-names = "linestate"; 268 #phy-cells = <0>; 269 status = "disabled"; 270 }; 271 }; 272 }; 273 274 uart0: serial@11010000 { 275 compatible = "snps,dw-apb-uart"; 276 reg = <0x11010000 0x100>; 277 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 278 clock-frequency = <24000000>; 279 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 280 clock-names = "baudclk", "apb_pclk"; 281 pinctrl-names = "default"; 282 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 283 reg-shift = <2>; 284 reg-io-width = <4>; 285 status = "disabled"; 286 }; 287 288 uart1: serial@11020000 { 289 compatible = "snps,dw-apb-uart"; 290 reg = <0x11020000 0x100>; 291 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 292 clock-frequency = <24000000>; 293 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 294 clock-names = "baudclk", "apb_pclk"; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&uart1_xfer>; 297 reg-shift = <2>; 298 reg-io-width = <4>; 299 status = "disabled"; 300 }; 301 302 uart2: serial@11030000 { 303 compatible = "snps,dw-apb-uart"; 304 reg = <0x11030000 0x100>; 305 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 306 clock-frequency = <24000000>; 307 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 308 clock-names = "baudclk", "apb_pclk"; 309 pinctrl-names = "default"; 310 pinctrl-0 = <&uart2_xfer>; 311 reg-shift = <2>; 312 reg-io-width = <4>; 313 status = "disabled"; 314 }; 315 316 efuse: efuse@11040000 { 317 compatible = "rockchip,rk3228-efuse"; 318 reg = <0x11040000 0x20>; 319 clocks = <&cru PCLK_EFUSE_256>; 320 clock-names = "pclk_efuse"; 321 #address-cells = <1>; 322 #size-cells = <1>; 323 324 /* Data cells */ 325 efuse_id: id@7 { 326 reg = <0x7 0x10>; 327 }; 328 cpu_leakage: cpu_leakage@17 { 329 reg = <0x17 0x1>; 330 }; 331 }; 332 333 i2c0: i2c@11050000 { 334 compatible = "rockchip,rk3228-i2c"; 335 reg = <0x11050000 0x1000>; 336 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 337 #address-cells = <1>; 338 #size-cells = <0>; 339 clock-names = "i2c"; 340 clocks = <&cru PCLK_I2C0>; 341 pinctrl-names = "default"; 342 pinctrl-0 = <&i2c0_xfer>; 343 status = "disabled"; 344 }; 345 346 i2c1: i2c@11060000 { 347 compatible = "rockchip,rk3228-i2c"; 348 reg = <0x11060000 0x1000>; 349 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 clock-names = "i2c"; 353 clocks = <&cru PCLK_I2C1>; 354 pinctrl-names = "default"; 355 pinctrl-0 = <&i2c1_xfer>; 356 status = "disabled"; 357 }; 358 359 i2c2: i2c@11070000 { 360 compatible = "rockchip,rk3228-i2c"; 361 reg = <0x11070000 0x1000>; 362 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 363 #address-cells = <1>; 364 #size-cells = <0>; 365 clock-names = "i2c"; 366 clocks = <&cru PCLK_I2C2>; 367 pinctrl-names = "default"; 368 pinctrl-0 = <&i2c2_xfer>; 369 status = "disabled"; 370 }; 371 372 i2c3: i2c@11080000 { 373 compatible = "rockchip,rk3228-i2c"; 374 reg = <0x11080000 0x1000>; 375 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 clock-names = "i2c"; 379 clocks = <&cru PCLK_I2C3>; 380 pinctrl-names = "default"; 381 pinctrl-0 = <&i2c3_xfer>; 382 status = "disabled"; 383 }; 384 385 spi0: spi@11090000 { 386 compatible = "rockchip,rk3228-spi"; 387 reg = <0x11090000 0x1000>; 388 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 392 clock-names = "spiclk", "apb_pclk"; 393 pinctrl-names = "default"; 394 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>; 395 status = "disabled"; 396 }; 397 398 wdt: watchdog@110a0000 { 399 compatible = "snps,dw-wdt"; 400 reg = <0x110a0000 0x100>; 401 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&cru PCLK_CPU>; 403 status = "disabled"; 404 }; 405 406 pwm0: pwm@110b0000 { 407 compatible = "rockchip,rk3288-pwm"; 408 reg = <0x110b0000 0x10>; 409 #pwm-cells = <3>; 410 clocks = <&cru PCLK_PWM>; 411 clock-names = "pwm"; 412 pinctrl-names = "active"; 413 pinctrl-0 = <&pwm0_pin>; 414 status = "disabled"; 415 }; 416 417 pwm1: pwm@110b0010 { 418 compatible = "rockchip,rk3288-pwm"; 419 reg = <0x110b0010 0x10>; 420 #pwm-cells = <3>; 421 clocks = <&cru PCLK_PWM>; 422 clock-names = "pwm"; 423 pinctrl-names = "active"; 424 pinctrl-0 = <&pwm1_pin>; 425 status = "disabled"; 426 }; 427 428 pwm2: pwm@110b0020 { 429 compatible = "rockchip,rk3288-pwm"; 430 reg = <0x110b0020 0x10>; 431 #pwm-cells = <3>; 432 clocks = <&cru PCLK_PWM>; 433 clock-names = "pwm"; 434 pinctrl-names = "active"; 435 pinctrl-0 = <&pwm2_pin>; 436 status = "disabled"; 437 }; 438 439 pwm3: pwm@110b0030 { 440 compatible = "rockchip,rk3288-pwm"; 441 reg = <0x110b0030 0x10>; 442 #pwm-cells = <2>; 443 clocks = <&cru PCLK_PWM>; 444 clock-names = "pwm"; 445 pinctrl-names = "active"; 446 pinctrl-0 = <&pwm3_pin>; 447 status = "disabled"; 448 }; 449 450 timer: timer@110c0000 { 451 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer"; 452 reg = <0x110c0000 0x20>; 453 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&xin24m>, <&cru PCLK_TIMER>; 455 clock-names = "timer", "pclk"; 456 }; 457 458 cru: clock-controller@110e0000 { 459 compatible = "rockchip,rk3228-cru"; 460 reg = <0x110e0000 0x1000>; 461 rockchip,grf = <&grf>; 462 #clock-cells = <1>; 463 #reset-cells = <1>; 464 assigned-clocks = 465 <&cru PLL_GPLL>, <&cru ARMCLK>, 466 <&cru PLL_CPLL>, <&cru ACLK_PERI>, 467 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 468 <&cru ACLK_CPU>, <&cru HCLK_CPU>, 469 <&cru PCLK_CPU>; 470 assigned-clock-rates = 471 <594000000>, <816000000>, 472 <500000000>, <150000000>, 473 <150000000>, <75000000>, 474 <150000000>, <150000000>, 475 <75000000>; 476 }; 477 478 thermal-zones { 479 cpu_thermal: cpu-thermal { 480 polling-delay-passive = <100>; /* milliseconds */ 481 polling-delay = <5000>; /* milliseconds */ 482 483 thermal-sensors = <&tsadc 0>; 484 485 trips { 486 cpu_alert0: cpu_alert0 { 487 temperature = <70000>; /* millicelsius */ 488 hysteresis = <2000>; /* millicelsius */ 489 type = "passive"; 490 }; 491 cpu_alert1: cpu_alert1 { 492 temperature = <75000>; /* millicelsius */ 493 hysteresis = <2000>; /* millicelsius */ 494 type = "passive"; 495 }; 496 cpu_crit: cpu_crit { 497 temperature = <90000>; /* millicelsius */ 498 hysteresis = <2000>; /* millicelsius */ 499 type = "critical"; 500 }; 501 }; 502 503 cooling-maps { 504 map0 { 505 trip = <&cpu_alert0>; 506 cooling-device = 507 <&cpu0 THERMAL_NO_LIMIT 6>, 508 <&cpu1 THERMAL_NO_LIMIT 6>, 509 <&cpu2 THERMAL_NO_LIMIT 6>, 510 <&cpu3 THERMAL_NO_LIMIT 6>; 511 }; 512 map1 { 513 trip = <&cpu_alert1>; 514 cooling-device = 515 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 516 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 517 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 518 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 519 }; 520 }; 521 }; 522 }; 523 524 tsadc: tsadc@11150000 { 525 compatible = "rockchip,rk3228-tsadc"; 526 reg = <0x11150000 0x100>; 527 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 529 clock-names = "tsadc", "apb_pclk"; 530 assigned-clocks = <&cru SCLK_TSADC>; 531 assigned-clock-rates = <32768>; 532 resets = <&cru SRST_TSADC>; 533 reset-names = "tsadc-apb"; 534 pinctrl-names = "gpio", "otpout"; 535 pinctrl-0 = <&otp_pin>; 536 pinctrl-1 = <&otp_out>; 537 #thermal-sensor-cells = <1>; 538 rockchip,hw-tshut-temp = <95000>; 539 status = "disabled"; 540 }; 541 542 hdmi_phy: hdmi-phy@12030000 { 543 compatible = "rockchip,rk3228-hdmi-phy"; 544 reg = <0x12030000 0x10000>; 545 clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>; 546 clock-names = "sysclk", "refoclk", "refpclk"; 547 #clock-cells = <0>; 548 clock-output-names = "hdmiphy_phy"; 549 #phy-cells = <0>; 550 status = "disabled"; 551 }; 552 553 gpu: gpu@20000000 { 554 compatible = "rockchip,rk3228-mali", "arm,mali-400"; 555 reg = <0x20000000 0x10000>; 556 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 562 interrupt-names = "gp", 563 "gpmmu", 564 "pp0", 565 "ppmmu0", 566 "pp1", 567 "ppmmu1"; 568 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 569 clock-names = "bus", "core"; 570 resets = <&cru SRST_GPU_A>; 571 status = "disabled"; 572 }; 573 574 vpu_mmu: iommu@20020800 { 575 compatible = "rockchip,iommu"; 576 reg = <0x20020800 0x100>; 577 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 579 clock-names = "aclk", "iface"; 580 #iommu-cells = <0>; 581 status = "disabled"; 582 }; 583 584 vdec_mmu: iommu@20030480 { 585 compatible = "rockchip,iommu"; 586 reg = <0x20030480 0x40>, <0x200304c0 0x40>; 587 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 589 clock-names = "aclk", "iface"; 590 #iommu-cells = <0>; 591 status = "disabled"; 592 }; 593 594 vop: vop@20050000 { 595 compatible = "rockchip,rk3228-vop"; 596 reg = <0x20050000 0x1ffc>; 597 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; 599 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 600 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 601 reset-names = "axi", "ahb", "dclk"; 602 iommus = <&vop_mmu>; 603 status = "disabled"; 604 605 vop_out: port { 606 #address-cells = <1>; 607 #size-cells = <0>; 608 609 vop_out_hdmi: endpoint@0 { 610 reg = <0>; 611 remote-endpoint = <&hdmi_in_vop>; 612 }; 613 }; 614 }; 615 616 vop_mmu: iommu@20053f00 { 617 compatible = "rockchip,iommu"; 618 reg = <0x20053f00 0x100>; 619 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 621 clock-names = "aclk", "iface"; 622 #iommu-cells = <0>; 623 status = "disabled"; 624 }; 625 626 rga: rga@20060000 { 627 compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga"; 628 reg = <0x20060000 0x1000>; 629 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; 631 clock-names = "aclk", "hclk", "sclk"; 632 resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>; 633 reset-names = "core", "axi", "ahb"; 634 }; 635 636 iep_mmu: iommu@20070800 { 637 compatible = "rockchip,iommu"; 638 reg = <0x20070800 0x100>; 639 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 641 clock-names = "aclk", "iface"; 642 #iommu-cells = <0>; 643 status = "disabled"; 644 }; 645 646 hdmi: hdmi@200a0000 { 647 compatible = "rockchip,rk3228-dw-hdmi"; 648 reg = <0x200a0000 0x20000>; 649 reg-io-width = <4>; 650 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 651 assigned-clocks = <&cru SCLK_HDMI_PHY>; 652 assigned-clock-parents = <&hdmi_phy>; 653 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; 654 clock-names = "iahb", "isfr", "cec"; 655 pinctrl-names = "default"; 656 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; 657 resets = <&cru SRST_HDMI_P>; 658 reset-names = "hdmi"; 659 phys = <&hdmi_phy>; 660 phy-names = "hdmi"; 661 rockchip,grf = <&grf>; 662 status = "disabled"; 663 664 ports { 665 hdmi_in: port { 666 #address-cells = <1>; 667 #size-cells = <0>; 668 hdmi_in_vop: endpoint@0 { 669 reg = <0>; 670 remote-endpoint = <&vop_out_hdmi>; 671 }; 672 }; 673 }; 674 }; 675 676 sdmmc: mmc@30000000 { 677 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 678 reg = <0x30000000 0x4000>; 679 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 680 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 681 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 682 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 683 fifo-depth = <0x100>; 684 pinctrl-names = "default"; 685 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 686 status = "disabled"; 687 }; 688 689 sdio: mmc@30010000 { 690 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 691 reg = <0x30010000 0x4000>; 692 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 693 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 694 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 695 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 696 fifo-depth = <0x100>; 697 pinctrl-names = "default"; 698 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; 699 status = "disabled"; 700 }; 701 702 emmc: mmc@30020000 { 703 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; 704 reg = <0x30020000 0x4000>; 705 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 706 clock-frequency = <37500000>; 707 max-frequency = <37500000>; 708 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 709 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 710 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 711 bus-width = <8>; 712 rockchip,default-sample-phase = <158>; 713 fifo-depth = <0x100>; 714 pinctrl-names = "default"; 715 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 716 resets = <&cru SRST_EMMC>; 717 reset-names = "reset"; 718 status = "disabled"; 719 }; 720 721 usb_otg: usb@30040000 { 722 compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb", 723 "snps,dwc2"; 724 reg = <0x30040000 0x40000>; 725 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 726 clocks = <&cru HCLK_OTG>; 727 clock-names = "otg"; 728 dr_mode = "otg"; 729 g-np-tx-fifo-size = <16>; 730 g-rx-fifo-size = <280>; 731 g-tx-fifo-size = <256 128 128 64 32 16>; 732 phys = <&u2phy0_otg>; 733 phy-names = "usb2-phy"; 734 status = "disabled"; 735 }; 736 737 usb_host0_ehci: usb@30080000 { 738 compatible = "generic-ehci"; 739 reg = <0x30080000 0x20000>; 740 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 741 clocks = <&cru HCLK_HOST0>, <&u2phy0>; 742 phys = <&u2phy0_host>; 743 phy-names = "usb"; 744 status = "disabled"; 745 }; 746 747 usb_host0_ohci: usb@300a0000 { 748 compatible = "generic-ohci"; 749 reg = <0x300a0000 0x20000>; 750 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&cru HCLK_HOST0>, <&u2phy0>; 752 phys = <&u2phy0_host>; 753 phy-names = "usb"; 754 status = "disabled"; 755 }; 756 757 usb_host1_ehci: usb@300c0000 { 758 compatible = "generic-ehci"; 759 reg = <0x300c0000 0x20000>; 760 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 761 clocks = <&cru HCLK_HOST1>, <&u2phy1>; 762 phys = <&u2phy1_otg>; 763 phy-names = "usb"; 764 status = "disabled"; 765 }; 766 767 usb_host1_ohci: usb@300e0000 { 768 compatible = "generic-ohci"; 769 reg = <0x300e0000 0x20000>; 770 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&cru HCLK_HOST1>, <&u2phy1>; 772 phys = <&u2phy1_otg>; 773 phy-names = "usb"; 774 status = "disabled"; 775 }; 776 777 usb_host2_ehci: usb@30100000 { 778 compatible = "generic-ehci"; 779 reg = <0x30100000 0x20000>; 780 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&cru HCLK_HOST2>, <&u2phy1>; 782 phys = <&u2phy1_host>; 783 phy-names = "usb"; 784 status = "disabled"; 785 }; 786 787 usb_host2_ohci: usb@30120000 { 788 compatible = "generic-ohci"; 789 reg = <0x30120000 0x20000>; 790 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 791 clocks = <&cru HCLK_HOST2>, <&u2phy1>; 792 phys = <&u2phy1_host>; 793 phy-names = "usb"; 794 status = "disabled"; 795 }; 796 797 gmac: ethernet@30200000 { 798 compatible = "rockchip,rk3228-gmac"; 799 reg = <0x30200000 0x10000>; 800 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 801 interrupt-names = "macirq"; 802 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 803 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, 804 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 805 <&cru PCLK_GMAC>; 806 clock-names = "stmmaceth", "mac_clk_rx", 807 "mac_clk_tx", "clk_mac_ref", 808 "clk_mac_refout", "aclk_mac", 809 "pclk_mac"; 810 resets = <&cru SRST_GMAC>; 811 reset-names = "stmmaceth"; 812 rockchip,grf = <&grf>; 813 status = "disabled"; 814 }; 815 816 gic: interrupt-controller@32010000 { 817 compatible = "arm,gic-400"; 818 interrupt-controller; 819 #interrupt-cells = <3>; 820 #address-cells = <0>; 821 822 reg = <0x32011000 0x1000>, 823 <0x32012000 0x2000>, 824 <0x32014000 0x2000>, 825 <0x32016000 0x2000>; 826 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 827 }; 828 829 pinctrl: pinctrl { 830 compatible = "rockchip,rk3228-pinctrl"; 831 rockchip,grf = <&grf>; 832 #address-cells = <1>; 833 #size-cells = <1>; 834 ranges; 835 836 gpio0: gpio0@11110000 { 837 compatible = "rockchip,gpio-bank"; 838 reg = <0x11110000 0x100>; 839 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 840 clock-names = "bus"; 841 clocks = <&cru PCLK_GPIO0>; 842 843 gpio-controller; 844 #gpio-cells = <2>; 845 846 interrupt-controller; 847 #interrupt-cells = <2>; 848 }; 849 850 gpio1: gpio1@11120000 { 851 compatible = "rockchip,gpio-bank"; 852 reg = <0x11120000 0x100>; 853 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 854 clock-names = "bus"; 855 clocks = <&cru PCLK_GPIO1>; 856 857 gpio-controller; 858 #gpio-cells = <2>; 859 860 interrupt-controller; 861 #interrupt-cells = <2>; 862 }; 863 864 gpio2: gpio2@11130000 { 865 compatible = "rockchip,gpio-bank"; 866 reg = <0x11130000 0x100>; 867 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 868 clock-names = "bus"; 869 clocks = <&cru PCLK_GPIO2>; 870 871 gpio-controller; 872 #gpio-cells = <2>; 873 874 interrupt-controller; 875 #interrupt-cells = <2>; 876 }; 877 878 gpio3: gpio3@11140000 { 879 compatible = "rockchip,gpio-bank"; 880 reg = <0x11140000 0x100>; 881 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 882 clock-names = "bus"; 883 clocks = <&cru PCLK_GPIO3>; 884 885 gpio-controller; 886 #gpio-cells = <2>; 887 888 interrupt-controller; 889 #interrupt-cells = <2>; 890 }; 891 892 pcfg_pull_up: pcfg-pull-up { 893 bias-pull-up; 894 }; 895 896 pcfg_pull_down: pcfg-pull-down { 897 bias-pull-down; 898 }; 899 900 pcfg_pull_none: pcfg-pull-none { 901 bias-disable; 902 }; 903 904 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { 905 drive-strength = <12>; 906 }; 907 908 sdmmc { 909 sdmmc_clk: sdmmc-clk { 910 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>; 911 }; 912 913 sdmmc_cmd: sdmmc-cmd { 914 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>; 915 }; 916 917 sdmmc_bus4: sdmmc-bus4 { 918 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>, 919 <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>, 920 <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>, 921 <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>; 922 }; 923 }; 924 925 sdio { 926 sdio_clk: sdio-clk { 927 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>; 928 }; 929 930 sdio_cmd: sdio-cmd { 931 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>; 932 }; 933 934 sdio_bus4: sdio-bus4 { 935 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>, 936 <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>, 937 <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>, 938 <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>; 939 }; 940 }; 941 942 emmc { 943 emmc_clk: emmc-clk { 944 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 945 }; 946 947 emmc_cmd: emmc-cmd { 948 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>; 949 }; 950 951 emmc_bus8: emmc-bus8 { 952 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, 953 <1 RK_PD1 2 &pcfg_pull_none>, 954 <1 RK_PD2 2 &pcfg_pull_none>, 955 <1 RK_PD3 2 &pcfg_pull_none>, 956 <1 RK_PD4 2 &pcfg_pull_none>, 957 <1 RK_PD5 2 &pcfg_pull_none>, 958 <1 RK_PD6 2 &pcfg_pull_none>, 959 <1 RK_PD7 2 &pcfg_pull_none>; 960 }; 961 }; 962 963 gmac { 964 rgmii_pins: rgmii-pins { 965 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, 966 <2 RK_PB4 1 &pcfg_pull_none>, 967 <2 RK_PD1 1 &pcfg_pull_none>, 968 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, 969 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, 970 <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>, 971 <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>, 972 <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>, 973 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, 974 <2 RK_PC1 1 &pcfg_pull_none>, 975 <2 RK_PC0 1 &pcfg_pull_none>, 976 <2 RK_PC5 2 &pcfg_pull_none>, 977 <2 RK_PC4 2 &pcfg_pull_none>, 978 <2 RK_PB3 1 &pcfg_pull_none>, 979 <2 RK_PB0 1 &pcfg_pull_none>; 980 }; 981 982 rmii_pins: rmii-pins { 983 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, 984 <2 RK_PB4 1 &pcfg_pull_none>, 985 <2 RK_PD1 1 &pcfg_pull_none>, 986 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, 987 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, 988 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, 989 <2 RK_PC1 1 &pcfg_pull_none>, 990 <2 RK_PC0 1 &pcfg_pull_none>, 991 <2 RK_PB0 1 &pcfg_pull_none>, 992 <2 RK_PB7 1 &pcfg_pull_none>; 993 }; 994 995 phy_pins: phy-pins { 996 rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>, 997 <2 RK_PB0 2 &pcfg_pull_none>; 998 }; 999 }; 1000 1001 hdmi { 1002 hdmi_hpd: hdmi-hpd { 1003 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>; 1004 }; 1005 1006 hdmii2c_xfer: hdmii2c-xfer { 1007 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 1008 <0 RK_PA7 2 &pcfg_pull_none>; 1009 }; 1010 1011 hdmi_cec: hdmi-cec { 1012 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; 1013 }; 1014 }; 1015 1016 i2c0 { 1017 i2c0_xfer: i2c0-xfer { 1018 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 1019 <0 RK_PA1 1 &pcfg_pull_none>; 1020 }; 1021 }; 1022 1023 i2c1 { 1024 i2c1_xfer: i2c1-xfer { 1025 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 1026 <0 RK_PA3 1 &pcfg_pull_none>; 1027 }; 1028 }; 1029 1030 i2c2 { 1031 i2c2_xfer: i2c2-xfer { 1032 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, 1033 <2 RK_PC5 1 &pcfg_pull_none>; 1034 }; 1035 }; 1036 1037 i2c3 { 1038 i2c3_xfer: i2c3-xfer { 1039 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 1040 <0 RK_PA7 1 &pcfg_pull_none>; 1041 }; 1042 }; 1043 1044 spi0 { 1045 spi0_clk: spi0-clk { 1046 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>; 1047 }; 1048 spi0_cs0: spi0-cs0 { 1049 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>; 1050 }; 1051 spi0_tx: spi0-tx { 1052 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>; 1053 }; 1054 spi0_rx: spi0-rx { 1055 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>; 1056 }; 1057 spi0_cs1: spi0-cs1 { 1058 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>; 1059 }; 1060 }; 1061 1062 spi1 { 1063 spi1_clk: spi1-clk { 1064 rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>; 1065 }; 1066 spi1_cs0: spi1-cs0 { 1067 rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>; 1068 }; 1069 spi1_rx: spi1-rx { 1070 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>; 1071 }; 1072 spi1_tx: spi1-tx { 1073 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>; 1074 }; 1075 spi1_cs1: spi1-cs1 { 1076 rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>; 1077 }; 1078 }; 1079 1080 i2s1 { 1081 i2s1_bus: i2s1-bus { 1082 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 1083 <0 RK_PB1 1 &pcfg_pull_none>, 1084 <0 RK_PB3 1 &pcfg_pull_none>, 1085 <0 RK_PB4 1 &pcfg_pull_none>, 1086 <0 RK_PB5 1 &pcfg_pull_none>, 1087 <0 RK_PB6 1 &pcfg_pull_none>, 1088 <1 RK_PA2 2 &pcfg_pull_none>, 1089 <1 RK_PA4 2 &pcfg_pull_none>, 1090 <1 RK_PA5 2 &pcfg_pull_none>; 1091 }; 1092 }; 1093 1094 pwm0 { 1095 pwm0_pin: pwm0-pin { 1096 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; 1097 }; 1098 1099 pwm0_pin_pull_down: pwm0-pin-pull-down { 1100 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_down>; 1101 }; 1102 }; 1103 1104 pwm1 { 1105 pwm1_pin: pwm1-pin { 1106 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1107 }; 1108 1109 pwm1_pin_pull_down: pwm1-pin-pull-down { 1110 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_down>; 1111 }; 1112 }; 1113 1114 pwm2 { 1115 pwm2_pin: pwm2-pin { 1116 rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>; 1117 }; 1118 1119 pwm2_pin_pull_down: pwm2-pin-pull-down { 1120 rockchip,pins = <1 RK_PB4 2 &pcfg_pull_down>; 1121 }; 1122 }; 1123 1124 pwm3 { 1125 pwm3_pin: pwm3-pin { 1126 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 1127 }; 1128 1129 pwm3_pin_pull_down: pwm3-pin-pull-down { 1130 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_down>; 1131 }; 1132 }; 1133 1134 spdif { 1135 spdif_tx: spdif-tx { 1136 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>; 1137 }; 1138 }; 1139 1140 tsadc { 1141 otp_pin: otp-pin { 1142 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 1143 }; 1144 1145 otp_out: otp-out { 1146 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; 1147 }; 1148 }; 1149 1150 uart0 { 1151 uart0_xfer: uart0-xfer { 1152 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>, 1153 <2 RK_PD3 1 &pcfg_pull_none>; 1154 }; 1155 1156 uart0_cts: uart0-cts { 1157 rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>; 1158 }; 1159 1160 uart0_rts: uart0-rts { 1161 rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>; 1162 }; 1163 }; 1164 1165 uart1 { 1166 uart1_xfer: uart1-xfer { 1167 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, 1168 <1 RK_PB2 1 &pcfg_pull_none>; 1169 }; 1170 1171 uart1_cts: uart1-cts { 1172 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>; 1173 }; 1174 1175 uart1_rts: uart1-rts { 1176 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1177 }; 1178 }; 1179 1180 uart2 { 1181 uart2_xfer: uart2-xfer { 1182 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, 1183 <1 RK_PC3 2 &pcfg_pull_none>; 1184 }; 1185 1186 uart21_xfer: uart21-xfer { 1187 rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>, 1188 <1 RK_PB1 2 &pcfg_pull_none>; 1189 }; 1190 1191 uart2_cts: uart2-cts { 1192 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 1193 }; 1194 1195 uart2_rts: uart2-rts { 1196 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 1197 }; 1198 }; 1199 }; 1200}; 1201