1/* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/clock/rockchip-ddr.h> 8#include <dt-bindings/dram/rockchip,rk322x.h> 9 10/ { 11 dram_timing: dram_timing { 12 compatible = "rockchip,dram-timing"; 13 dram_spd_bin = <DDR3_DEFAULT>; 14 sr_idle = <0x18>; 15 pd_idle = <0x20>; 16 dram_dll_disb_freq = <300>; 17 phy_dll_disb_freq = <400>; 18 dram_odt_disb_freq = <333>; 19 phy_odt_disb_freq = <333>; 20 ddr3_drv = <DDR3_DS_40ohm>; 21 ddr3_odt = <DDR3_ODT_120ohm>; 22 lpddr3_drv = <LP3_DS_34ohm>; 23 lpddr3_odt = <LP3_ODT_240ohm>; 24 lpddr2_drv = <LP2_DS_34ohm>; 25 /* lpddr2 not supported odt */ 26 phy_ddr3_clk_drv = <PHY_DDR3_RON_RTT_45ohm>; 27 phy_ddr3_cmd_drv = <PHY_DDR3_RON_RTT_45ohm>; 28 phy_ddr3_dqs_drv = <PHY_DDR3_RON_RTT_34ohm>; 29 phy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>; 30 phy_lp23_clk_drv = <PHY_LP23_RON_RTT_43ohm>; 31 phy_lp23_cmd_drv = <PHY_LP23_RON_RTT_34ohm>; 32 phy_lp23_dqs_drv = <PHY_LP23_RON_RTT_34ohm>; 33 phy_lp3_odt = <PHY_LP23_RON_RTT_240ohm>; 34 }; 35}; 36