xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/rk3229-at-common.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This file is dual-licensed: you can use it either under the terms
5*4882a593Smuzhiyun * of the GPL or the X11 license, at your option. Note that this dual
6*4882a593Smuzhiyun * licensing only applies to this file, and not this project as a
7*4882a593Smuzhiyun * whole.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun *  a) This file is free software; you can redistribute it and/or
10*4882a593Smuzhiyun *     modify it under the terms of the GNU General Public License as
11*4882a593Smuzhiyun *     published by the Free Software Foundation; either version 2 of the
12*4882a593Smuzhiyun *     License, or (at your option) any later version.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun *     This file is distributed in the hope that it will be useful,
15*4882a593Smuzhiyun *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16*4882a593Smuzhiyun *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17*4882a593Smuzhiyun *     GNU General Public License for more details.
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun *  Or, alternatively,
20*4882a593Smuzhiyun *
21*4882a593Smuzhiyun *  b) Permission is hereby granted, free of charge, to any person
22*4882a593Smuzhiyun *     obtaining a copy of this software and associated documentation
23*4882a593Smuzhiyun *     files (the "Software"), to deal in the Software without
24*4882a593Smuzhiyun *     restriction, including without limitation the rights to use,
25*4882a593Smuzhiyun *     copy, modify, merge, publish, distribute, sublicense, and/or
26*4882a593Smuzhiyun *     sell copies of the Software, and to permit persons to whom the
27*4882a593Smuzhiyun *     Software is furnished to do so, subject to the following
28*4882a593Smuzhiyun *     conditions:
29*4882a593Smuzhiyun *
30*4882a593Smuzhiyun *     The above copyright notice and this permission notice shall be
31*4882a593Smuzhiyun *     included in all copies or substantial portions of the Software.
32*4882a593Smuzhiyun *
33*4882a593Smuzhiyun *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34*4882a593Smuzhiyun *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35*4882a593Smuzhiyun *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36*4882a593Smuzhiyun *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37*4882a593Smuzhiyun *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38*4882a593Smuzhiyun *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39*4882a593Smuzhiyun *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40*4882a593Smuzhiyun *     OTHER DEALINGS IN THE SOFTWARE.
41*4882a593Smuzhiyun */
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun#include "rk322x.dtsi"
44*4882a593Smuzhiyun#include "rk3229-cpu-opp.dtsi"
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun/ {
47*4882a593Smuzhiyun	chosen {
48*4882a593Smuzhiyun		bootargs = "earlycon=uart8250,mmio32,0x11030000";
49*4882a593Smuzhiyun	};
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun	fiq-debugger {
52*4882a593Smuzhiyun		compatible = "rockchip,fiq-debugger";
53*4882a593Smuzhiyun		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
54*4882a593Smuzhiyun		rockchip,serial-id = <2>;
55*4882a593Smuzhiyun		rockchip,signal-irq = <159>;
56*4882a593Smuzhiyun		rockchip,wake-irq = <0>;
57*4882a593Smuzhiyun		rockchip,irq-mode-enable = <0>; /* If enable uart uses irq instead of fiq */
58*4882a593Smuzhiyun		rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
59*4882a593Smuzhiyun		pinctrl-names = "default";
60*4882a593Smuzhiyun		pinctrl-0 = <&uart21_xfer>;
61*4882a593Smuzhiyun	};
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun	psci {
64*4882a593Smuzhiyun		compatible = "arm,psci-1.0";
65*4882a593Smuzhiyun		method = "smc";
66*4882a593Smuzhiyun	};
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun	xin32k: xin32k {
69*4882a593Smuzhiyun		compatible = "fixed-clock";
70*4882a593Smuzhiyun		clock-frequency = <32768>;
71*4882a593Smuzhiyun		clock-output-names = "xin32k";
72*4882a593Smuzhiyun		#clock-cells = <0>;
73*4882a593Smuzhiyun	};
74*4882a593Smuzhiyun};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun&cpu0 {
77*4882a593Smuzhiyun	enable-method = "psci";
78*4882a593Smuzhiyun};
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun&cpu1 {
81*4882a593Smuzhiyun	enable-method = "psci";
82*4882a593Smuzhiyun};
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun&cpu2 {
85*4882a593Smuzhiyun	enable-method = "psci";
86*4882a593Smuzhiyun};
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun&cpu3 {
89*4882a593Smuzhiyun	enable-method = "psci";
90*4882a593Smuzhiyun};
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun&emmc {
93*4882a593Smuzhiyun	max-frequency = <125000000>;
94*4882a593Smuzhiyun	broken-cd;
95*4882a593Smuzhiyun	bus-width = <8>;
96*4882a593Smuzhiyun	cap-mmc-highspeed;
97*4882a593Smuzhiyun	no-sdio;
98*4882a593Smuzhiyun	no-sd;
99*4882a593Smuzhiyun	disable-wp;
100*4882a593Smuzhiyun	non-removable;
101*4882a593Smuzhiyun	num-slots = <1>;
102*4882a593Smuzhiyun	/delete-property/ default-sample-phase;
103*4882a593Smuzhiyun	/delete-property/ pinctrl-names;
104*4882a593Smuzhiyun	/delete-property/ pinctrl-0;
105*4882a593Smuzhiyun	status = "okay";
106*4882a593Smuzhiyun};
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun&cpu0 {
109*4882a593Smuzhiyun	cpu-supply = <&vdd_arm>;
110*4882a593Smuzhiyun};
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun&gpu {
113*4882a593Smuzhiyun	mali-supply = <&vdd_logic>;
114*4882a593Smuzhiyun};
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun&i2c0 {
117*4882a593Smuzhiyun	status = "okay";
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun	rk805: rk805@18 {
120*4882a593Smuzhiyun		compatible = "rockchip,rk805";
121*4882a593Smuzhiyun		status = "okay";
122*4882a593Smuzhiyun		reg = <0x18>;
123*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
124*4882a593Smuzhiyun		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
125*4882a593Smuzhiyun		spinctrl-names = "default";
126*4882a593Smuzhiyun		pinctrl-0 = <&pmic_int_l>;
127*4882a593Smuzhiyun		rockchip,system-power-controller;
128*4882a593Smuzhiyun		wakeup-source;
129*4882a593Smuzhiyun		gpio-controller;
130*4882a593Smuzhiyun		#gpio-cells = <2>;
131*4882a593Smuzhiyun		#clock-cells = <1>;
132*4882a593Smuzhiyun		clock-output-names = "rk805-clkout1", "rk805-clkout2";
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun		rtc {
135*4882a593Smuzhiyun			status = "okay";
136*4882a593Smuzhiyun		};
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun		pwrkey {
139*4882a593Smuzhiyun			status = "okay";
140*4882a593Smuzhiyun		};
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun		gpio {
143*4882a593Smuzhiyun			status = "okay";
144*4882a593Smuzhiyun		};
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun		regulators {
147*4882a593Smuzhiyun			vdd_arm: DCDC_REG1 {
148*4882a593Smuzhiyun				regulator-name = "vdd_arm";
149*4882a593Smuzhiyun				regulator-min-microvolt = <712500>;
150*4882a593Smuzhiyun				regulator-max-microvolt = <1450000>;
151*4882a593Smuzhiyun				regulator-initial-mode = <0x1>;
152*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
153*4882a593Smuzhiyun				regulator-boot-on;
154*4882a593Smuzhiyun				regulator-always-on;
155*4882a593Smuzhiyun				regulator-state-mem {
156*4882a593Smuzhiyun					regulator-mode = <0x2>;
157*4882a593Smuzhiyun					regulator-on-in-suspend;
158*4882a593Smuzhiyun					regulator-suspend-microvolt = <950000>;
159*4882a593Smuzhiyun				};
160*4882a593Smuzhiyun			};
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun			vdd_logic: DCDC_REG2 {
163*4882a593Smuzhiyun				regulator-name = "vdd_logic";
164*4882a593Smuzhiyun				regulator-min-microvolt = <712500>;
165*4882a593Smuzhiyun				regulator-max-microvolt = <1450000>;
166*4882a593Smuzhiyun				regulator-initial-mode = <0x1>;
167*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
168*4882a593Smuzhiyun				regulator-boot-on;
169*4882a593Smuzhiyun				regulator-always-on;
170*4882a593Smuzhiyun				regulator-state-mem {
171*4882a593Smuzhiyun					regulator-mode = <0x2>;
172*4882a593Smuzhiyun					regulator-on-in-suspend;
173*4882a593Smuzhiyun					regulator-suspend-microvolt = <1000000>;
174*4882a593Smuzhiyun				};
175*4882a593Smuzhiyun			};
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun			vcc_ddr: DCDC_REG3 {
178*4882a593Smuzhiyun				regulator-name = "vcc_ddr";
179*4882a593Smuzhiyun				regulator-boot-on;
180*4882a593Smuzhiyun				regulator-always-on;
181*4882a593Smuzhiyun				regulator-state-mem {
182*4882a593Smuzhiyun					regulator-mode = <0x2>;
183*4882a593Smuzhiyun					regulator-on-in-suspend;
184*4882a593Smuzhiyun				};
185*4882a593Smuzhiyun			};
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun			vcc_io: DCDC_REG4 {
188*4882a593Smuzhiyun				regulator-name = "vcc_io";
189*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
190*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
191*4882a593Smuzhiyun				regulator-initial-mode = <0x1>;
192*4882a593Smuzhiyun				regulator-boot-on;
193*4882a593Smuzhiyun				regulator-always-on;
194*4882a593Smuzhiyun				regulator-state-mem {
195*4882a593Smuzhiyun					regulator-mode = <0x2>;
196*4882a593Smuzhiyun					regulator-on-in-suspend;
197*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
198*4882a593Smuzhiyun				};
199*4882a593Smuzhiyun			};
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun			vcc_18: LDO_REG1 {
202*4882a593Smuzhiyun				regulator-name = "vcc_18";
203*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
204*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
205*4882a593Smuzhiyun				regulator-boot-on;
206*4882a593Smuzhiyun				regulator-always-on;
207*4882a593Smuzhiyun				regulator-state-mem {
208*4882a593Smuzhiyun					regulator-on-in-suspend;
209*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
210*4882a593Smuzhiyun				};
211*4882a593Smuzhiyun			};
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun			vcc_18emmc: LDO_REG2 {
214*4882a593Smuzhiyun				regulator-name = "vcc_18emmc";
215*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
216*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
217*4882a593Smuzhiyun				regulator-boot-on;
218*4882a593Smuzhiyun				regulator-always-on;
219*4882a593Smuzhiyun				regulator-state-mem {
220*4882a593Smuzhiyun					regulator-on-in-suspend;
221*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
222*4882a593Smuzhiyun				};
223*4882a593Smuzhiyun			};
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun			vdd_10: LDO_REG3 {
226*4882a593Smuzhiyun				regulator-name = "vdd_10";
227*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
228*4882a593Smuzhiyun				regulator-max-microvolt = <1000000>;
229*4882a593Smuzhiyun				regulator-boot-on;
230*4882a593Smuzhiyun				regulator-always-on;
231*4882a593Smuzhiyun				regulator-state-mem {
232*4882a593Smuzhiyun					regulator-on-in-suspend;
233*4882a593Smuzhiyun					regulator-suspend-microvolt = <1000000>;
234*4882a593Smuzhiyun				};
235*4882a593Smuzhiyun			};
236*4882a593Smuzhiyun		};
237*4882a593Smuzhiyun	};
238*4882a593Smuzhiyun};
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun&io_domains {
241*4882a593Smuzhiyun	status = "okay";
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun	vccio1-supply = <&vcc_io>;
244*4882a593Smuzhiyun	vccio2-supply = <&vcc_18>;
245*4882a593Smuzhiyun	vccio4-supply = <&vcc_io>;
246*4882a593Smuzhiyun};
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun&pinctrl {
249*4882a593Smuzhiyun	pmic {
250*4882a593Smuzhiyun		pmic_int_l: pmic-int-l {
251*4882a593Smuzhiyun			rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; /* gpio1_a1 */
252*4882a593Smuzhiyun		};
253*4882a593Smuzhiyun	};
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun};
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun&tsadc {
258*4882a593Smuzhiyun	rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
259*4882a593Smuzhiyun	status = "okay";
260*4882a593Smuzhiyun};
261