xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/rk312x.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)

/*
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/power/rk3128-power.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/soc/rockchip-system-status.h>
#include <dt-bindings/clock/rk3128-cru.h>
#include <dt-bindings/display/media-bus-format.h>
#include <dt-bindings/thermal/thermal.h>
#include "rk3128-dram-default-timing.dtsi"

/ {
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &gmac;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		mmc0 = &sdmmc;
		mmc1 = &sdio;
		mmc2 = &emmc;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		spi0 = &spi0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@f00 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf00>;
			operating-points-v2 = <&cpu0_opp_table>;
			clocks = <&cru ARMCLK>;
			#cooling-cells = <2>; /* min followed by max */
			dynamic-power-coefficient = <120>;
		};
		cpu1: cpu@f01 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf01>;
			operating-points-v2 = <&cpu0_opp_table>;
		};
		cpu2: cpu@f02 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf02>;
			operating-points-v2 = <&cpu0_opp_table>;
		};
		cpu3: cpu@f03 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf03>;
			operating-points-v2 = <&cpu0_opp_table>;
		};
	};

	cpu0_opp_table: opp_table0 {
		compatible = "operating-points-v2";
		opp-shared;

		rockchip,leakage-scaling-sel = <
			1   13   18
			14  254  0
		>;
		clocks = <&cru PLL_APLL>;
		rockchip,leakage-voltage-sel = <
			1   13   0
			14  49   1
			50  254  2
		>;
		nvmem-cells = <&cpu_leakage>;
		nvmem-cell-names = "cpu_leakage";

		opp-216000000 {
			opp-hz = /bits/ 64 <216000000>;
			opp-microvolt = <1000000 1000000 1425000>;
			opp-microvolt-L0 = <1000000 1000000 1425000>;
			opp-microvolt-L1 = <950000 950000 1425000>;
			opp-microvolt-L2 = <950000 950000 1425000>;
			clock-latency-ns = <40000>;
		};
		opp-408000000 {
			opp-hz = /bits/ 64 <408000000>;
			opp-microvolt = <1000000 1000000 1425000>;
			opp-microvolt-L0 = <1000000 1000000 1425000>;
			opp-microvolt-L1 = <950000 950000 1425000>;
			opp-microvolt-L2 = <950000 950000 1425000>;
			clock-latency-ns = <40000>;
		};
		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <1150000 1150000 1425000>;
			opp-microvolt-L0 = <1150000 1150000 1425000>;
			opp-microvolt-L1 = <1100000 1100000 1425000>;
			opp-microvolt-L2 = <1050000 1050000 1425000>;
			clock-latency-ns = <40000>;
		};
		opp-696000000 {
			opp-hz = /bits/ 64 <696000000>;
			opp-microvolt = <1150000 1150000 1425000>;
			opp-microvolt-L0 = <1150000 1150000 1425000>;
			opp-microvolt-L1 = <1100000 1100000 1425000>;
			opp-microvolt-L2 = <1050000 1050000 1425000>;
			clock-latency-ns = <40000>;
		};
		opp-816000000 {
			opp-hz = /bits/ 64 <816000000>;
			opp-microvolt = <1200000 1200000 1425000>;
			opp-microvolt-L0 = <1200000 1200000 1425000>;
			opp-microvolt-L1 = <1150000 1150000 1425000>;
			opp-microvolt-L2 = <1100000 1100000 1425000>;
			clock-latency-ns = <40000>;
			opp-suspend;
		};
		opp-1008000000 {
			opp-hz = /bits/ 64 <1008000000>;
			opp-microvolt = <1350000 1350000 1425000>;
			opp-microvolt-L0 = <1350000 1350000 1425000>;
			opp-microvolt-L1 = <1275000 1275000 1425000>;
			opp-microvolt-L2 = <1225000 1225000 1425000>;
			clock-latency-ns = <40000>;
		};
		opp-1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			opp-microvolt = <1425000 1425000 1425000>;
			opp-microvolt-L0 = <1425000 1425000 1425000>;
			opp-microvolt-L1 = <1425000 1425000 1425000>;
			opp-microvolt-L2 = <1375000 1375000 1425000>;
			clock-latency-ns = <40000>;
		};
	};

	amba {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		pdma: pdma@20078000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x20078000 0x4000>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			arm,pl330-broken-no-flushp;
			arm,pl330-periph-burst;
			clocks = <&cru ACLK_DMAC>;
			clock-names = "apb_pclk";
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	dfi: dfi {
		compatible = "rockchip,rk3128-dfi";
		rockchip,pmu = <&pmu>;
		rockchip,grf = <&grf>;
		status = "disabled";
	};

	display_subsystem: display-subsystem {
		compatible = "rockchip,display-subsystem";
		ports = <&vop_out>;
		status = "disabled";
	};

	dmc: dmc {
		compatible = "rockchip,rk3128-dmc";
		devfreq-events = <&dfi>;
		clocks = <&cru SCLK_DDRC>;
		clock-names = "dmc_clk";
		upthreshold = <55>;
		downdifferential = <10>;
		operating-points-v2 = <&dmc_opp_table>;
		vop-dclk-mode = <0>;
		min-cpu-freq = <600000>;
		rockchip,ddr_timing = <&ddr_timing>;
		system-status-freq = <
			/*system status		freq(KHz)*/
			SYS_STATUS_NORMAL	456000
			SYS_STATUS_SUSPEND	300000
			SYS_STATUS_REBOOT	456000
		>;
		auto-min-freq = <456000>;
		auto-freq-en = <0>;
		status = "disabled";
	};

	dmc_opp_table: opp_table2 {
		compatible = "operating-points-v2";

		opp-200000000 {
			opp-hz = /bits/ 64 <200000000>;
			opp-microvolt = <1025000>;
			status = "disabled";
		};
		opp-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			opp-microvolt = <1025000>;
		};
		opp-396000000 {
			opp-hz = /bits/ 64 <396000000>;
			opp-microvolt = <1100000>;
		};
		opp-456000000 {
			opp-hz = /bits/ 64 <456000000>;
			opp-microvolt = <1200000>;
		};
	};

	firmware {
		optee: optee {
			compatible = "linaro,optee-tz";
			method = "smc";
			status = "disabled";
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		clock-frequency = <24000000>;
	};

	thermal-zones {
		soc_thermal: soc-thermal {
			polling-delay-passive = <1000>;
			polling-delay = <2000>;
			sustainable-power = <200>;

			thermal-sensors = <&tsadc 0>;

			trips {
				threshold: trip-point0 {
					temperature = <80000>;
					hysteresis = <2000>;
					type = "passive";
				};
				target: trip-point1 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "passive";
				};
			};

			cooling-maps {
				map0 {
					trip = <&target>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
					contribution = <1024>;
				};
				map1 {
					trip = <&target>;
					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
					contribution = <1024>;
				};
			};
		};

	};

	tsadc: tsadc {
		compatible = "rockchip,rk3126-tsadc-virtual";
		nvmem-cells = <&cpu_leakage>;
		nvmem-cell-names = "cpu_leakage";
		#thermal-sensor-cells = <1>;
		status = "disabled";
	};

	xin24m: oscillator {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "xin24m";
		#clock-cells = <0>;
	};

	gpu: gpu@10090000 {
		compatible = "arm,mali400";
		reg = <0x10090000 0x10000>;
		upthreshold = <40>;
		downdifferential = <10>;

		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "Mali_GP_IRQ",
				  "Mali_GP_MMU_IRQ",
				  "Mali_PP0_IRQ",
				  "Mali_PP0_MMU_IRQ",
				  "Mali_PP1_IRQ",
				  "Mali_PP1_MMU_IRQ";
		clocks = <&cru ACLK_GPU>;
		#cooling-cells = <2>; /* min followed by max */
		clock-names = "clk_mali";
		power-domains = <&power RK3128_PD_GPU>;
		operating-points-v2 = <&gpu_opp_table>;
		status = "disabled";

		gpu_power_model: power_model {
			compatible = "arm,mali-simple-power-model";
			voltage = <900>;
			frequency = <500>;
			static-power = <300>;
			dynamic-power = <396>;
			ts = <32000 4700 (-80) 2>;
			thermal-zone = "soc-thermal";
		};
	};

	gpu_opp_table: opp-table2 {
		compatible = "operating-points-v2";

		opp-200000000 {
			opp-hz = /bits/ 64 <200000000>;
			opp-microvolt = <975000>;
		};
		opp-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			opp-microvolt = <1050000>;
		};
		opp-400000000 {
			opp-hz = /bits/ 64 <400000000>;
			opp-microvolt = <1150000>;
		};
		opp-480000000 {
			opp-hz = /bits/ 64 <480000000>;
			opp-microvolt = <1250000>;
		};
	};

	pmu: syscon@100a0000 {
		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
		reg = <0x100a0000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		power: power-controller {
			compatible = "rockchip,rk3128-power-controller";
			#power-domain-cells = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "okay";

			pd_vio: pd_vio@RK3128_PD_VIO {
				reg = <RK3128_PD_VIO>;
				clocks = <&cru ACLK_RGA>,
					 <&cru ACLK_LCDC0>,
					 <&cru ACLK_IEP>,
					 <&cru ACLK_CIF>,
					 <&cru ACLK_VIO0>,
					 <&cru ACLK_VIO1>,
					 <&cru DCLK_VOP>,
					 <&cru DCLK_EBC>,
					 <&cru HCLK_RGA>,
					 <&cru HCLK_VIO>,
					 <&cru HCLK_EBC>,
					 <&cru HCLK_LCDC0>,
					 <&cru HCLK_IEP>,
					 <&cru HCLK_CIF>,
					 <&cru HCLK_VIO_H2P>,
					 <&cru PCLK_MIPI>,
					 <&cru PCLK_MIPIPHY>,
					 <&cru SCLK_VOP>;
				pm_qos = <&qos_rga>,
					 <&qos_iep>,
					 <&qos_lcdc0>,
					 <&qos_vip0>;
			};
			pd_video@RK3128_PD_VIDEO {
				reg = <RK3128_PD_VIDEO>;
				clocks = <&cru ACLK_VEPU>,
					 <&cru ACLK_VDPU>,
					 <&cru HCLK_VEPU>,
					 <&cru HCLK_VDPU>,
					 <&cru SCLK_HEVC_CORE>;
				pm_qos = <&qos_vpu>;
			};
			pd_gpu@RK3128_PD_GPU {
				reg = <RK3128_PD_GPU>;
				clocks = <&cru ACLK_GPU>;
				pm_qos = <&qos_gpu>;
			};
		};

		reboot_mode: reboot-mode {
			compatible = "syscon-reboot-mode";
			offset = <0x38>;
			mode-bootloader = <BOOT_BL_DOWNLOAD>;
			mode-charge = <BOOT_CHARGING>;
			mode-fastboot = <BOOT_FASTBOOT>;
			mode-loader = <BOOT_BL_DOWNLOAD>;
			mode-normal = <BOOT_NORMAL>;
			mode-recovery = <BOOT_RECOVERY>;
			mode-ums = <BOOT_UMS>;
		};
	};

	mpp_srv: mpp-srv {
		compatible = "rockchip,mpp-service";
		rockchip,taskqueue-count = <1>;
		rockchip,resetgroup-count = <1>;
		rockchip,grf = <&grf>;
		rockchip,grf-offset = <0x0144>;
		rockchip,grf-values = <0x04000400>, <0x04000400>;
		rockchip,grf-names = "grf_vdpu1", "grf_vepu1";
		status = "disabled";
	};

	hevc: hevc@10104000 {
		compatible = "rockchip,hevc-decoder";
		reg = <0x10104000 0x400>;
		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "irq_dec";
		clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
			<&cru SCLK_HEVC_CORE>;
		clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
		resets = <&cru SRST_VCODEC_H>, <&cru SRST_VCODEC_A>,
			<&cru SRST_HEVC_CORE>;
		reset-names = "shared_video_h", "shared_video_a",
			      "video_core";
		iommus = <&hevc_mmu>;
		power-domains = <&power RK3128_PD_VIDEO>;
		rockchip,srv = <&mpp_srv>;
		rockchip,taskqueue-node = <0>;
		rockchip,resetgroup-node = <0>;
		status = "disabled";
	};

	hevc_mmu: iommu@10104440 {
		compatible = "rockchip,iommu";
		reg = <0x10104440 0x40>, <0x10104480 0x40>;
		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hevc_mmu";
		clock-names = "aclk", "iface";
		clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>;
		power-domains = <&power RK3128_PD_VIDEO>;
		#iommu-cells = <0>;
		status = "disabled";
	};

	vepu: vepu@0x10106000 {
		compatible = "rockchip,vpu-encoder-v1";
		reg = <0x10106000 0x400>;
		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "irq_enc";
		clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>;
		clock-names = "aclk_vcodec", "hclk_vcodec";
		resets = <&cru SRST_VCODEC_H>, <&cru SRST_VCODEC_A>;
		reset-names = "shared_video_h", "shared_video_a";
		iommus = <&vpu_mmu>;
		power-domains = <&power RK3128_PD_VIDEO>;
		rockchip,srv = <&mpp_srv>;
		rockchip,taskqueue-node = <0>;
		rockchip,resetgroup-node = <0>;
		status = "disabled";
	};

	vdpu: vdpu@10106400 {
		compatible = "rockchip,vpu-decoder-v1";
		reg = <0x10106400 0x400>;
		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "irq_dec";
		clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>;
		clock-names = "aclk_vcodec", "hclk_vcodec";
		resets = <&cru SRST_VCODEC_H>, <&cru SRST_VCODEC_A>;
		reset-names = "shared_video_h", "shared_video_a";
		iommus = <&vpu_mmu>;
		power-domains = <&power RK3128_PD_VIDEO>;
		rockchip,srv = <&mpp_srv>;
		rockchip,taskqueue-node = <0>;
		rockchip,resetgroup-node = <0>;
		status = "disabled";
	};

	vpu_mmu: iommu@10106800 {
		compatible = "rockchip,iommu";
		reg = <0x10106800 0x40>;
		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "vpu_mmu";
		clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>;
		clock-names = "aclk", "iface";
		power-domains = <&power RK3128_PD_VIDEO>;
		#iommu-cells = <0>;
		status = "disabled";
	};

	iep: iep@10108000 {
		compatible = "rockchip,iep";
		iommu_enabled = <1>;
		iommus = <&iep_mmu>;
		reg = <0x10108000 0x800>;
		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
		clock-names = "aclk_iep", "hclk_iep";
		power-domains = <&power RK3128_PD_VIO>;
		allocator = <1>;
		version = <1>;
		status = "disabled";
	};

	iep_mmu: iommu@10108800 {
		compatible = "rockchip,iommu";
		reg = <0x10108800 0x40>;
		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "iep_mmu";
		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
		clock-names = "aclk", "iface";
		power-domains = <&power RK3128_PD_VIO>;
		#iommu-cells = <0>;
		status = "disabled";
	};

	cif: cif@1010a000 {
		compatible = "rockchip,cif";
		reg = <0x1010a000 0x200>;
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>,
				<&cru SCLK_CIF_SRC>, <&cru SCLK_CIF_OUT>;
		clock-names = "aclk_cif0", "hclk_cif0",
				"cif0_in", "cif0_out";
		resets = <&cru SRST_CIF0>;
		reset-names = "rst_cif";
		power-domains = <&power RK3128_PD_VIO>;
		status = "disabled";
	};

	cif_new: cif-new@1010a000 {
		compatible = "rockchip,rk3128-cif";
		reg = <0x1010a000 0x200>;

		clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>,
			 <&cru SCLK_CIF_OUT>;
		clock-names = "aclk_cif", "hclk_cif",
			      "sclk_cif_out";
		resets = <&cru SRST_CIF0>;
		reset-names = "rst_cif";
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
		/* rk312x has not iommu attached */
		/* iommus = <&cif_mmu>; */
		power-domains = <&power RK3128_PD_VIO>;

		status = "disabled";
	};

	rga: rga@1010c000 {
		compatible = "rockchip,rk312x-rga";
		reg = <0x1010c000 0x1000>;
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
		clock-names = "aclk_rga", "hclk_rga", "sclk_rga";
		power-domains = <&power RK3128_PD_VIO>;
		status = "disabled";
	};

	vop: vop@1010e000 {
		compatible = "rockchip,rk3126-vop";
		reg = <0x1010e000 0x100>, <0x1010ec00 0x400>;
		reg-names = "regs", "gamma_lut";
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_LCDC0>, <&cru DCLK_VOP>, <&cru HCLK_LCDC0>;
		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
		resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_D>, <&cru SRST_VOP_H>;
		reset-names = "axi", "ahb", "dclk";
		iommus = <&vop_mmu>;
		power-domains = <&power RK3128_PD_VIO>;
		status = "disabled";

		vop_out: port {
			#address-cells = <1>;
			#size-cells = <0>;

			vop_out_dsi: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&dsi_in_vop>;
			};

			vop_out_lvds: endpoint@1 {
				reg = <1>;
				remote-endpoint = <&lvds_in_vop>;
			};

			vop_out_rgb: endpoint@2 {
				reg = <2>;
				remote-endpoint = <&rgb_in_vop>;
			};
		};
	};

	vop_mmu: iommu@1010e300 {
		compatible = "rockchip,iommu";
		reg = <0x1010e300 0x100>;
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "vop_mmu";
		clocks = <&cru ACLK_LCDC0>, <&cru HCLK_LCDC0>;
		clock-names = "aclk", "iface";
		power-domains = <&power RK3128_PD_VIO>;
		#iommu-cells = <0>;
		rockchip,disable-device-link-resume;
		status = "disabled";
	};

	dsi: dsi@10110000 {
		compatible = "rockchip,rk3128-mipi-dsi";
		reg = <0x10110000 0x4000>;
		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru PCLK_MIPI>, <&cru HCLK_VIO_H2P>;
		clock-names = "pclk", "hclk";
		resets = <&cru SRST_VIO_MIPI_DSI>;
		reset-names = "apb";
		phys = <&video_phy>;
		phy-names = "dphy";
		power-domains = <&power RK3128_PD_VIO>;
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";

		ports {
			port {
				dsi_in_vop: endpoint {
					remote-endpoint = <&vop_out_dsi>;
				};
			};
		};
	};

	qos_gpu: qos@1012d000 {
		compatible = "syscon";
		reg = <0x1012d000 0x20>;
	};

	qos_vpu: qos@1012e000 {
		compatible = "syscon";
		reg = <0x1012e000 0x20>;
	};

	qos_rga: qos@1012f000 {
		compatible = "syscon";
		reg = <0x1012f000 0x20>;
	};

	qos_iep: qos@1012f100 {
		compatible = "syscon";
		reg = <0x1012f100 0x20>;
	};

	qos_lcdc0: qos@1012f180 {
		compatible = "syscon";
		reg = <0x1012f180 0x20>;
	};

	qos_vip0: qos@1012f200 {
		compatible = "syscon";
		reg = <0x1012f200 0x20>;
	};

	gic: interrupt-controller@10139000 {
		compatible = "arm,cortex-a7-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		#address-cells = <0>;

		reg = <0x10139000 0x1000>,
		      <0x1013a000 0x1000>,
		      <0x1013c000 0x2000>,
		      <0x1013e000 0x2000>;
		interrupts = <GIC_PPI 9 0xf04>;
	};

	usb_otg: usb@10180000 {
		compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb",
			     "snps,dwc2";
		reg = <0x10180000 0x40000>;
		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_OTG>;
		clock-names = "otg";
		dr_mode = "otg";
		g-np-tx-fifo-size = <16>;
		g-rx-fifo-size = <280>;
		g-tx-fifo-size = <256 128 128 64 32 16>;
		g-use-dma;
		phys = <&u2phy_otg>;
		phy-names = "usb2-phy";
		status = "disabled";
	};

	usb_host_ehci: usb@101c0000 {
		compatible = "generic-ehci";
		reg = <0x101c0000 0x20000>;
		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_HOST2>, <&u2phy>;
		clock-names = "usbhost", "utmi";
		phys = <&u2phy_host>;
		phy-names = "usb";
		status = "disabled";
	};

	usb_host_ohci: usb@101e0000 {
		compatible = "generic-ohci";
		reg = <0x101e0000 0x20000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_HOST2>, <&u2phy>;
		clock-names = "usbhost", "utmi";
		phys = <&u2phy_host>;
		phy-names = "usb";
		status = "disabled";
	};

	i2s_8ch: i2s-8ch@10200000 {
		compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s";
		reg = <0x10200000 0x1000>;
		clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S_8CH>;
		clock-names = "i2s_clk", "i2s_hclk";
		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
		dmas = <&pdma 14>, <&pdma 15>;
		dma-names = "tx", "rx";
		resets = <&cru SRST_I2S_8CH>;
		reset-names = "reset-m";
		status = "disabled";
	};

	spdif: spdif@10204000 {
		compatible = "rockchip,rk3128-spdif";
		reg = <0x10204000 0x1000>;
		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>;
		clock-names = "mclk", "hclk";
		dmas = <&pdma 13>;
		dma-names = "tx";
		pinctrl-names = "default";
		pinctrl-0 = <&spdif_tx>;
		status = "disabled";
	};

	sfc: sfc@1020c000 {
		compatible = "rockchip,sfc";
		reg = <0x1020c000 0x8000>;
		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
		clock-names = "clk_sfc", "hclk_sfc";
		assigned-clocks = <&cru SCLK_SFC>;
		assigned-clock-rates = <60000000>;
		status = "disabled";
	};

	i2s_2ch: i2s-2ch@10220000 {
		compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s";
		reg = <0x10220000 0x1000>;
		clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S_2CH>;
		clock-names = "i2s_clk", "i2s_hclk";
		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
		dmas = <&pdma 0>, <&pdma 1>;
		dma-names = "tx", "rx";
		resets = <&cru SRST_I2S_2CH>;
		reset-names = "reset-m";
		status = "disabled";
	};

	sdmmc: dwmmc@10214000 {
		compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc";
		reg = <0x10214000 0x4000>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
		max-frequency = <50000000>;
		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
		dmas = <&pdma 10>;
		dma-names = "rx-tx";
		fifo-depth = <0x100>;
		bus-width = <4>;
		status = "disabled";
	};

	sdio: dwmmc@10218000 {
		compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc";
		reg = <0x10218000 0x4000>;
		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&sdio_pwren &sdio_cmd &sdio_clk &sdio_bus4>;
		clock-freq-min-max = <400000 50000000>;
		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
		clock-names = "biu", "ciu";
		dmas = <&pdma 11>;
		dma-names = "rx-tx";
		num-slots = <1>;
		fifo-depth = <0x100>;
		bus-width = <4>;
		status = "disabled";
	};

	emmc: dwmmc@1021c000 {
		compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc";
		reg = <0x1021c000 0x4000>;
		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-freq-min-max = <400000 50000000>;
		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
		clock-names = "biu", "ciu";
		dmas = <&pdma 12>;
		dma-names = "rx-tx";
		num-slots = <1>;
		fifo-depth = <0x100>;
		bus-width = <8>;
		status = "disabled";
	};

	nandc: nandc@10500000 {
		compatible = "rockchip,rk-nandc";
		reg = <0x10500000 0x4000>;
		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
		nandc_id = <0>;
		clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>;
		clock-names = "clk_nandc", "hclk_nandc";
		status = "disabled";
	};

	cru: clock-controller@20000000 {
		compatible = "rockchip,rk3128-cru";
		reg = <0x20000000 0x1000>;
		rockchip,grf = <&grf>;
		#clock-cells = <1>;
		#reset-cells = <1>;
		assigned-clocks = <&cru PLL_GPLL>,
				  <&cru ACLK_CPU>, <&cru HCLK_CPU>,
				  <&cru PCLK_CPU>, <&cru ACLK_PERI>,
				  <&cru HCLK_PERI>, <&cru PCLK_PERI>;
		assigned-clock-rates = <594000000>,
				       <300000000>, <150000000>,
				       <75000000>, <300000000>,
				       <150000000>, <75000000>;
	};

	grf: syscon@20008000 {
		compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd";
		reg = <0x20008000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		lvds: lvds {
			compatible = "rockchip,rk3126-lvds";
			phys = <&video_phy>;
			phy-names = "phy";
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					lvds_in_vop: endpoint {
						remote-endpoint = <&vop_out_lvds>;
					};
				};
			};
		};

		rgb: rgb {
			compatible = "rockchip,rk3128-rgb";
			phys = <&video_phy>;
			phy-names = "phy";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&lcdc_rgb_pins>;
			pinctrl-1 = <&lcdc_sleep_pins>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					rgb_in_vop: endpoint {
						remote-endpoint = <&vop_out_rgb>;
					};
				};
			};
		};

		u2phy: usb2-phy@17c {
			compatible = "rockchip,rk3128-usb2phy";
			reg = <0x017c 0x0c>;
			clocks = <&cru SCLK_OTGPHY0>;
			clock-names = "phyclk";
			#clock-cells = <0>;
			clock-output-names = "usb480m_phy";
			assigned-clocks = <&cru SCLK_USB480M>;
			assigned-clock-parents = <&u2phy>;
			status = "disabled";

			u2phy_otg: otg-port {
				#phy-cells = <0>;
				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "otg-bvalid", "otg-id",
						  "linestate";
				status = "disabled";
			};

			u2phy_host: host-port {
				#phy-cells = <0>;
				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "linestate";
				status = "disabled";
			};
		};
	};

	codec: codec@20030000 {
		compatible = "rockchip,rk3128-codec";
		reg = <0x20030000 0x4000>;
		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
		boot_depop = <1>;
		pa_enable_time = <1000>;
		rockchip,grf = <&grf>;
		clocks = <&cru PCLK_ACODEC>, <&cru SCLK_I2S1>;
		clock-names = "g_pclk_acodec", "i2s_clk";
		status = "disabled";
	};

	video_phy: video-phy@20038000 {
		compatible = "rockchip,rk3128-dsi-dphy", "rockchip,rk3128-video-phy";
		reg = <0x20038000 0x4000>, <0x10110000 0x4000>;
		reg-names = "phy", "host";
		clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>,
			 <&cru PCLK_MIPI>;
		clock-names = "ref", "pclk", "pclk_host";
		#clock-cells = <0>;
		resets = <&cru SRST_MIPIPHY_P>;
		reset-names = "apb";
		power-domains = <&power RK3128_PD_VIO>;
		#phy-cells = <0>;
		status = "disabled";
	};

	timer@20044000 {
		compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
		reg = <0x20044000 0x20>;
		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&xin24m>, <&cru PCLK_TIMER>;
		clock-names = "timer", "pclk";
	};

	watchdog@2004c000 {
		compatible = "snps,dw-wdt";
		reg = <0x2004c000 0x100>;
		clocks = <&cru PCLK_WDT>;
		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	pwm0: pwm@20050000 {
		compatible = "rockchip,rk3288-pwm";
		reg = <0x20050000 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm0_pin>;
		clocks = <&cru PCLK_PWM>;
		clock-names = "pwm";
		status = "disabled";
	};

	pwm1: pwm@20050010 {
		compatible = "rockchip,rk3288-pwm";
		reg = <0x20050010 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm1_pin>;
		clocks = <&cru PCLK_PWM>;
		clock-names = "pwm";
		status = "disabled";
	};

	pwm2: pwm@20050020 {
		compatible = "rockchip,rk3288-pwm";
		reg = <0x20050020 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm2_pin>;
		clocks = <&cru PCLK_PWM>;
		clock-names = "pwm";
		status = "disabled";
	};

	pwm3: pwm@20050030 {
		compatible = "rockchip,rk3288-pwm";
		reg = <0x20050030 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm3_pin>;
		clocks = <&cru PCLK_PWM>;
		clock-names = "pwm";
		status = "disabled";
	};

	i2c1: i2c@20056000 {
		compatible = "rockchip,rk3288-i2c";
		reg = <0x20056000 0x1000>;
		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2c";
		clocks = <&cru PCLK_I2C1>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c1_xfer>;
		status = "disabled";
	};

	i2c2: i2c@2005a000 {
		compatible = "rockchip,rk3288-i2c";
		reg = <0x2005a000 0x1000>;
		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2c";
		clocks = <&cru PCLK_I2C2>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c2_xfer>;
		status = "disabled";
	};

	i2c3: i2c@2005e000 {
		compatible = "rockchip,rk3288-i2c";
		reg = <0x2005e000 0x1000>;
		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2c";
		clocks = <&cru PCLK_I2C3>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c3_xfer>;
		status = "disabled";
	};

	uart0: serial@20060000 {
		compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
		reg = <0x20060000 0x100>;
		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <24000000>;
		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <2>;
		reg-io-width = <4>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
		status = "disabled";
	};

	uart1: serial@20064000 {
		compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
		reg = <0x20064000 0x100>;
		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <24000000>;
		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <2>;
		reg-io-width = <4>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
		status = "disabled";
	};

	uart2: serial@20068000 {
		compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
		reg = <0x20068000 0x100>;
		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <24000000>;
		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <2>;
		reg-io-width = <4>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart2_xfer>;
		status = "disabled";
	};

	saradc: saradc@2006c000 {
		compatible = "rockchip,saradc";
		reg = <0x2006c000 0x100>;
		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
		#io-channel-cells = <1>;
		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
		clock-names = "saradc", "apb_pclk";
		resets = <&cru SRST_SARADC>;
		reset-names = "saradc-apb";
		status = "disabled";
	};

	i2c0: i2c@20072000 {
		compatible = "rockchip,rk3288-i2c";
		reg = <0x20072000 0x1000>;
		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2c";
		clocks = <&cru PCLK_I2C0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c0_xfer>;
		status = "disabled";
	};

	spi0: spi@20074000 {
		compatible = "rockchip,rk3288-spi";
		reg = <0x20074000 0x1000>;
		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&spi0m0_tx &spi0m0_rx &spi0m0_clk &spi0m0_cs0 &spi0m0_cs1>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <&pdma 8>, <&pdma 9>;
		dma-names = "tx", "rx";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	gmac: eth@2008c000 {
		compatible = "rockchip,rk3128-gmac";
		reg = <0x2008c000 0x4000>;
		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "macirq", "eth_wake_irq";
		rockchip,grf = <&grf>;
		clocks = <&cru SCLK_MAC>,
			 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
			 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
			 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
		clock-names = "stmmaceth",
			      "mac_clk_rx", "mac_clk_tx",
			      "clk_mac_ref", "clk_mac_refout",
			      "aclk_mac", "pclk_mac";
		resets = <&cru SRST_GMAC>;
		reset-names = "stmmaceth";
		status = "disabled";
	};

	efuse: efuse@20090000 {
		compatible = "rockchip,rk3128-efuse";
		reg = <0x20090000 0x20>;
		#address-cells = <1>;
		#size-cells = <1>;
		clocks = <&cru PCLK_EFUSE>;
		clock-names = "pclk_efuse";

		efuse_id: id@7 {
			reg = <0x7 0x10>;
		};
		cpu_leakage: cpu_leakage@17 {
			reg = <0x17 0x1>;
		};
	};

	rockchip_system_monitor: rockchip-system-monitor {
		compatible = "rockchip,system-monitor";
	};

	pinctrl: pinctrl {
		compatible = "rockchip,rk3128-pinctrl";
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		gpio0: gpio0@2007c000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2007c000 0x100>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO0>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio1@20080000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20080000 0x100>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO1>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio2@20084000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20084000 0x100>;
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO2>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio3@20088000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20088000 0x100>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO3>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		pcfg_pull_default: pcfg_pull_default {
			bias-pull-pin-default;
		};

		pcfg_output_high: pcfg-output-high {
			output-high;
		};

		pcfg_pull_none: pcfg-pull-none {
			bias-disable;
		};

		emmc {
			emmc_clk: emmc-clk {
				rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
			};

			emmc_cmd: emmc-cmd {
				rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>;
			};

			emmc_cmd1: emmc-cmd1 {
				rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>;
			};

			emmc_pwr: emmc-pwr {
				rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>;
			};

			emmc_bus1: emmc-bus1 {
				rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>;
			};

			emmc_bus4: emmc-bus4 {
				rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
						<1 RK_PD1 2 &pcfg_pull_default>,
						<1 RK_PD2 2 &pcfg_pull_default>,
						<1 RK_PD3 2 &pcfg_pull_default>;
			};

			emmc_bus8: emmc-bus8 {
				rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
						<1 RK_PD1 2 &pcfg_pull_default>,
						<1 RK_PD2 2 &pcfg_pull_default>,
						<1 RK_PD3 2 &pcfg_pull_default>,
						<1 RK_PD4 2 &pcfg_pull_default>,
						<1 RK_PD5 2 &pcfg_pull_default>,
						<1 RK_PD6 2 &pcfg_pull_default>,
						<1 RK_PD7 2 &pcfg_pull_default>;
			};
		};

		i2c0 {
			i2c0_xfer: i2c0-xfer {
				rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
						<0 RK_PA1 1 &pcfg_pull_none>;
			};
		};

		i2c1 {
			i2c1_xfer: i2c1-xfer {
				rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
						<0 RK_PA3 1 &pcfg_pull_none>;
			};
		};

		i2c2 {
			i2c2_xfer: i2c2-xfer {
				rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>,
						<2 RK_PC5 3 &pcfg_pull_none>;
			};
		};

		i2c3 {
			i2c3_xfer: i2c3-xfer {
				rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
						<0 RK_PA7 1 &pcfg_pull_none>;
			};
		};

		lcdc {
			lcdc_rgb_pins: lcdc-rgb-pins {
				rockchip,pins =
					<2 RK_PB0 1 &pcfg_pull_none>,	/* LCDC_DCLK */
					<2 RK_PB1 1 &pcfg_pull_none>,	/* LCDC_HSYNC */
					<2 RK_PB2 1 &pcfg_pull_none>,	/* LCDC_VSYNC */
					<2 RK_PB3 1 &pcfg_pull_none>,	/* LCDC_DEN */
					<2 RK_PB4 1 &pcfg_pull_none>,	/* LCDC_DATA10 */
					<2 RK_PB5 1 &pcfg_pull_none>,	/* LCDC_DATA11 */
					<2 RK_PB6 1 &pcfg_pull_none>,	/* LCDC_DATA12 */
					<2 RK_PB7 1 &pcfg_pull_none>,	/* LCDC_DATA13 */
					<2 RK_PC0 1 &pcfg_pull_none>,	/* LCDC_DATA14 */
					<2 RK_PC1 1 &pcfg_pull_none>,	/* LCDC_DATA15 */
					<2 RK_PC2 1 &pcfg_pull_none>,	/* LCDC_DATA16 */
					<2 RK_PC3 1 &pcfg_pull_none>,	/* LCDC_DATA17 */
					<2 RK_PC4 1 &pcfg_pull_none>,	/* LCDC_DATA18 */
					<2 RK_PC5 1 &pcfg_pull_none>,	/* LCDC_DATA19 */
					<2 RK_PC6 1 &pcfg_pull_none>,	/* LCDC_DATA20 */
					<2 RK_PC7 1 &pcfg_pull_none>,	/* LCDC_DATA21 */
					<2 RK_PD0 1 &pcfg_pull_none>,	/* LCDC_DATA22 */
					<2 RK_PD1 1 &pcfg_pull_none>;	/* LCDC_DATA23 */
			};

			lcdc_sleep_pins: lcdc-sleep-pins {
				rockchip,pins =
					<2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>,	/* LCDC_DCLK */
					<2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>,	/* LCDC_HSYNC */
					<2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>,	/* LCDC_VSYNC */
					<2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>,	/* LCDC_DEN */
					<2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>,	/* LCDC_DATA10 */
					<2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>,	/* LCDC_DATA11 */
					<2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>,	/* LCDC_DATA12 */
					<2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>,	/* LCDC_DATA13 */
					<2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>,	/* LCDC_DATA14 */
					<2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>,	/* LCDC_DATA15 */
					<2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,	/* LCDC_DATA16 */
					<2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>,	/* LCDC_DATA17 */
					<2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>,	/* LCDC_DATA18 */
					<2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>,	/* LCDC_DATA19 */
					<2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>,	/* LCDC_DATA20 */
					<2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>,	/* LCDC_DATA21 */
					<2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>,	/* LCDC_DATA22 */
					<2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;	/* LCDC_DATA23 */
			};
		};

		uart0 {
			uart0_xfer: uart0-xfer {
				rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>,
						<2 RK_PD3 2 &pcfg_pull_none>;
			};

			uart0_cts: uart0-cts {
				rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>;
			};

			uart0_rts: uart0-rts {
				rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>;
			};
		};

		uart1 {
			uart1_xfer: uart1-xfer {
				rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>,
						<1 RK_PB2 2 &pcfg_pull_default>;
			};

			uart1_cts: uart1-cts {
				rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
			};

			uart1_rts: uart1-rts {
				rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
			};
		};

		uart2 {
			uart2_xfer: uart2-xfer {
				rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
						<1 RK_PC3 2 &pcfg_pull_none>;
			};

			uart2_cts: uart2-cts {
				rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
			};

			uart2_rts: uart2-rts {
				rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
			};
		};

		sdmmc {
			sdmmc_clk: sdmmc-clk {
				rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
			};

			sdmmc_det: sdmmc-det {
				rockchip,pins = <1 RK_PC1 1 &pcfg_pull_none>;
			};

			sdmmc_cmd: sdmmc-cmd {
				rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
			};

			sdmmc_wp: sdmmc-wp {
				rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
			};

			sdmmc_pwren: sdmmc-pwren {
				rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>;
			};

			sdmmc_bus4: sdmmc-bus4 {
				rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
						<1 RK_PC3 1 &pcfg_pull_default>,
						<1 RK_PC4 1 &pcfg_pull_default>,
						<1 RK_PC5 1 &pcfg_pull_default>;
			};
		};

		sdio {
			sdio_clk: sdio-clk {
				rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>;
			};

			sdio_cmd: sdio-cmd {
				rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>;
			};

			sdio_pwren: sdio-pwren {
				rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>;
			};

			sdio_bus4: sdio-bus4 {
				rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>,
						<1 RK_PA2 2 &pcfg_pull_default>,
						<1 RK_PA4 2 &pcfg_pull_default>,
						<1 RK_PA5 2 &pcfg_pull_default>;
			};
		};

		hdmi {
			hdmii2c_xfer: hdmii2c-xfer {
				rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
						<0 RK_PA7 2 &pcfg_pull_none>;
			};

			hdmi_hpd: hdmi-hpd {
				rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
			};

			hdmi_cec: hdmi-cec {
				rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
			};
		};

		i2s {
			i2s_bus: i2s-bus {
				rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
						<0 RK_PB1 1 &pcfg_pull_none>,
						<0 RK_PB3 1 &pcfg_pull_none>,
						<0 RK_PB4 1 &pcfg_pull_none>,
						<0 RK_PB5 1 &pcfg_pull_none>,
						<0 RK_PB6 1 &pcfg_pull_none>;
			};

			i2s1_bus: i2s1-bus {
				rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>,
						<1 RK_PA1 1 &pcfg_pull_none>,
						<1 RK_PA2 1 &pcfg_pull_none>,
						<1 RK_PA3 1 &pcfg_pull_none>,
						<1 RK_PA4 1 &pcfg_pull_none>,
						<1 RK_PA5 1 &pcfg_pull_none>;
			};
		};

		pwm0 {
			pwm0_pin: pwm0-pin {
				rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>;
			};
		};

		pwm1 {
			pwm1_pin: pwm1-pin {
				rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
			};
		};

		pwm2 {
			pwm2_pin: pwm2-pin {
				rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
			};
		};

		pwm3 {
			pwm3_pin: pwm3-pin {
				rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>;
			};
		};

		gmac {
			rgmii_pins: rgmii-pins {
				rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
						<2 RK_PB1 3 &pcfg_pull_default>,
						<2 RK_PB3 3 &pcfg_pull_default>,
						<2 RK_PB4 3 &pcfg_pull_default>,
						<2 RK_PB5 3 &pcfg_pull_default>,
						<2 RK_PB6 3 &pcfg_pull_default>,
						<2 RK_PC0 3 &pcfg_pull_default>,
						<2 RK_PC1 3 &pcfg_pull_default>,
						<2 RK_PC2 3 &pcfg_pull_default>,
						<2 RK_PC3 3 &pcfg_pull_default>,
						<2 RK_PD1 3 &pcfg_pull_default>,
						<2 RK_PC4 4 &pcfg_pull_default>,
						<2 RK_PC5 4 &pcfg_pull_default>,
						<2 RK_PC6 4 &pcfg_pull_default>,
						<2 RK_PC7 4 &pcfg_pull_default>;
			};

			rmii_pins: rmii-pins {
				rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
						<2 RK_PB4 3 &pcfg_pull_default>,
						<2 RK_PB5 3 &pcfg_pull_default>,
						<2 RK_PB6 3 &pcfg_pull_default>,
						<2 RK_PB7 3 &pcfg_pull_default>,
						<2 RK_PC0 3 &pcfg_pull_default>,
						<2 RK_PC1 3 &pcfg_pull_default>,
						<2 RK_PC2 3 &pcfg_pull_default>,
						<2 RK_PC3 3 &pcfg_pull_default>,
						<2 RK_PD1 3 &pcfg_pull_default>;
			};
		};

		spdif {
			spdif_tx: spdif-tx {
				rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
			};
		};

		spi0 {
			spi0m0_clk: spi0m0-clk {
				rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>;
			};

			spi0m0_cs0: spi0m0-cs0 {
				rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>;
			};

			spi0m0_tx: spi0m0-tx {
				rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>;
			};

			spi0m0_rx: spi0m0-rx {
				rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>;
			};

			spi0m0_cs1: spi0m0-cs1 {
				rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>;
			};

			spi0m1_clk: spi0m1-clk {
				rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
			};

			spi0m1_cs0: spi0m1-cs0 {
				rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
			};

			spi0m1_tx: spi0m1-tx {
				rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
			};

			spi0m1_rx: spi0m1-rx {
				rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
			};

			spi0m1_cs1: spi0m1-cs1 {
				rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
			};

			spi0m2_clk: spi0m2-clk {
				rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>;
			};

			spi0m2_cs0: spi0m2-cs0 {
				rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>;
			};

			spi0m2_tx: spi0m2-tx {
				rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>;
			};

			spi0m2_rx: spi0m2-rx {
				rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>;
			};
		};
	};
};