1/* 2 * This file is dual-licensed: you can use it either under the terms 3 * of the GPL or the X11 license, at your option. Note that this dual 4 * licensing only applies to this file, and not this project as a 5 * whole. 6 * 7 * a) This file is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of the 10 * License, or (at your option) any later version. 11 * 12 * This file is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * Or, alternatively, 18 * 19 * b) Permission is hereby granted, free of charge, to any person 20 * obtaining a copy of this software and associated documentation 21 * files (the "Software"), to deal in the Software without 22 * restriction, including without limitation the rights to use, 23 * copy, modify, merge, publish, distribute, sublicense, and/or 24 * sell copies of the Software, and to permit persons to whom the 25 * Software is furnished to do so, subject to the following 26 * conditions: 27 * 28 * The above copyright notice and this permission notice shall be 29 * included in all copies or substantial portions of the Software. 30 * 31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 38 * OTHER DEALINGS IN THE SOFTWARE. 39 */ 40 41#include <dt-bindings/gpio/gpio.h> 42#include <dt-bindings/interrupt-controller/irq.h> 43#include <dt-bindings/interrupt-controller/arm-gic.h> 44#include <dt-bindings/pinctrl/rockchip.h> 45#include <dt-bindings/power/rk3128-power.h> 46#include <dt-bindings/soc/rockchip,boot-mode.h> 47#include <dt-bindings/soc/rockchip-system-status.h> 48#include <dt-bindings/clock/rk3128-cru.h> 49#include <dt-bindings/display/media-bus-format.h> 50#include <dt-bindings/thermal/thermal.h> 51#include "rk3128-dram-default-timing.dtsi" 52 53/ { 54 interrupt-parent = <&gic>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 58 aliases { 59 ethernet0 = &gmac; 60 i2c0 = &i2c0; 61 i2c1 = &i2c1; 62 i2c2 = &i2c2; 63 i2c3 = &i2c3; 64 mmc0 = &sdmmc; 65 mmc1 = &sdio; 66 mmc2 = &emmc; 67 serial0 = &uart0; 68 serial1 = &uart1; 69 serial2 = &uart2; 70 spi0 = &spi0; 71 }; 72 73 cpus { 74 #address-cells = <1>; 75 #size-cells = <0>; 76 77 cpu0: cpu@f00 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a7"; 80 reg = <0xf00>; 81 operating-points-v2 = <&cpu0_opp_table>; 82 clocks = <&cru ARMCLK>; 83 #cooling-cells = <2>; /* min followed by max */ 84 dynamic-power-coefficient = <120>; 85 }; 86 cpu1: cpu@f01 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a7"; 89 reg = <0xf01>; 90 operating-points-v2 = <&cpu0_opp_table>; 91 }; 92 cpu2: cpu@f02 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a7"; 95 reg = <0xf02>; 96 operating-points-v2 = <&cpu0_opp_table>; 97 }; 98 cpu3: cpu@f03 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a7"; 101 reg = <0xf03>; 102 operating-points-v2 = <&cpu0_opp_table>; 103 }; 104 }; 105 106 cpu0_opp_table: opp_table0 { 107 compatible = "operating-points-v2"; 108 opp-shared; 109 110 rockchip,leakage-scaling-sel = < 111 1 13 18 112 14 254 0 113 >; 114 clocks = <&cru PLL_APLL>; 115 rockchip,leakage-voltage-sel = < 116 1 13 0 117 14 49 1 118 50 254 2 119 >; 120 nvmem-cells = <&cpu_leakage>; 121 nvmem-cell-names = "cpu_leakage"; 122 123 opp-216000000 { 124 opp-hz = /bits/ 64 <216000000>; 125 opp-microvolt = <1000000 1000000 1425000>; 126 opp-microvolt-L0 = <1000000 1000000 1425000>; 127 opp-microvolt-L1 = <950000 950000 1425000>; 128 opp-microvolt-L2 = <950000 950000 1425000>; 129 clock-latency-ns = <40000>; 130 }; 131 opp-408000000 { 132 opp-hz = /bits/ 64 <408000000>; 133 opp-microvolt = <1000000 1000000 1425000>; 134 opp-microvolt-L0 = <1000000 1000000 1425000>; 135 opp-microvolt-L1 = <950000 950000 1425000>; 136 opp-microvolt-L2 = <950000 950000 1425000>; 137 clock-latency-ns = <40000>; 138 }; 139 opp-600000000 { 140 opp-hz = /bits/ 64 <600000000>; 141 opp-microvolt = <1150000 1150000 1425000>; 142 opp-microvolt-L0 = <1150000 1150000 1425000>; 143 opp-microvolt-L1 = <1100000 1100000 1425000>; 144 opp-microvolt-L2 = <1050000 1050000 1425000>; 145 clock-latency-ns = <40000>; 146 }; 147 opp-696000000 { 148 opp-hz = /bits/ 64 <696000000>; 149 opp-microvolt = <1150000 1150000 1425000>; 150 opp-microvolt-L0 = <1150000 1150000 1425000>; 151 opp-microvolt-L1 = <1100000 1100000 1425000>; 152 opp-microvolt-L2 = <1050000 1050000 1425000>; 153 clock-latency-ns = <40000>; 154 }; 155 opp-816000000 { 156 opp-hz = /bits/ 64 <816000000>; 157 opp-microvolt = <1200000 1200000 1425000>; 158 opp-microvolt-L0 = <1200000 1200000 1425000>; 159 opp-microvolt-L1 = <1150000 1150000 1425000>; 160 opp-microvolt-L2 = <1100000 1100000 1425000>; 161 clock-latency-ns = <40000>; 162 opp-suspend; 163 }; 164 opp-1008000000 { 165 opp-hz = /bits/ 64 <1008000000>; 166 opp-microvolt = <1350000 1350000 1425000>; 167 opp-microvolt-L0 = <1350000 1350000 1425000>; 168 opp-microvolt-L1 = <1275000 1275000 1425000>; 169 opp-microvolt-L2 = <1225000 1225000 1425000>; 170 clock-latency-ns = <40000>; 171 }; 172 opp-1200000000 { 173 opp-hz = /bits/ 64 <1200000000>; 174 opp-microvolt = <1425000 1425000 1425000>; 175 opp-microvolt-L0 = <1425000 1425000 1425000>; 176 opp-microvolt-L1 = <1425000 1425000 1425000>; 177 opp-microvolt-L2 = <1375000 1375000 1425000>; 178 clock-latency-ns = <40000>; 179 }; 180 }; 181 182 amba { 183 compatible = "simple-bus"; 184 #address-cells = <1>; 185 #size-cells = <1>; 186 ranges; 187 188 pdma: pdma@20078000 { 189 compatible = "arm,pl330", "arm,primecell"; 190 reg = <0x20078000 0x4000>; 191 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 193 #dma-cells = <1>; 194 arm,pl330-broken-no-flushp; 195 arm,pl330-periph-burst; 196 clocks = <&cru ACLK_DMAC>; 197 clock-names = "apb_pclk"; 198 }; 199 }; 200 201 arm-pmu { 202 compatible = "arm,cortex-a7-pmu"; 203 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 207 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 208 }; 209 210 dfi: dfi { 211 compatible = "rockchip,rk3128-dfi"; 212 rockchip,pmu = <&pmu>; 213 rockchip,grf = <&grf>; 214 status = "disabled"; 215 }; 216 217 display_subsystem: display-subsystem { 218 compatible = "rockchip,display-subsystem"; 219 ports = <&vop_out>; 220 status = "disabled"; 221 }; 222 223 dmc: dmc { 224 compatible = "rockchip,rk3128-dmc"; 225 devfreq-events = <&dfi>; 226 clocks = <&cru SCLK_DDRC>; 227 clock-names = "dmc_clk"; 228 upthreshold = <55>; 229 downdifferential = <10>; 230 operating-points-v2 = <&dmc_opp_table>; 231 vop-dclk-mode = <0>; 232 min-cpu-freq = <600000>; 233 rockchip,ddr_timing = <&ddr_timing>; 234 system-status-freq = < 235 /*system status freq(KHz)*/ 236 SYS_STATUS_NORMAL 456000 237 SYS_STATUS_SUSPEND 300000 238 SYS_STATUS_REBOOT 456000 239 >; 240 auto-min-freq = <456000>; 241 auto-freq-en = <0>; 242 status = "disabled"; 243 }; 244 245 dmc_opp_table: opp_table2 { 246 compatible = "operating-points-v2"; 247 248 opp-200000000 { 249 opp-hz = /bits/ 64 <200000000>; 250 opp-microvolt = <1025000>; 251 status = "disabled"; 252 }; 253 opp-300000000 { 254 opp-hz = /bits/ 64 <300000000>; 255 opp-microvolt = <1025000>; 256 }; 257 opp-396000000 { 258 opp-hz = /bits/ 64 <396000000>; 259 opp-microvolt = <1100000>; 260 }; 261 opp-456000000 { 262 opp-hz = /bits/ 64 <456000000>; 263 opp-microvolt = <1200000>; 264 }; 265 }; 266 267 firmware { 268 optee: optee { 269 compatible = "linaro,optee-tz"; 270 method = "smc"; 271 status = "disabled"; 272 }; 273 }; 274 275 psci { 276 compatible = "arm,psci-1.0"; 277 method = "smc"; 278 }; 279 280 timer { 281 compatible = "arm,armv7-timer"; 282 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 283 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 284 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 285 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 286 clock-frequency = <24000000>; 287 }; 288 289 thermal-zones { 290 soc_thermal: soc-thermal { 291 polling-delay-passive = <1000>; 292 polling-delay = <2000>; 293 sustainable-power = <200>; 294 295 thermal-sensors = <&tsadc 0>; 296 297 trips { 298 threshold: trip-point0 { 299 temperature = <80000>; 300 hysteresis = <2000>; 301 type = "passive"; 302 }; 303 target: trip-point1 { 304 temperature = <90000>; 305 hysteresis = <2000>; 306 type = "passive"; 307 }; 308 }; 309 310 cooling-maps { 311 map0 { 312 trip = <&target>; 313 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 314 contribution = <1024>; 315 }; 316 map1 { 317 trip = <&target>; 318 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 319 contribution = <1024>; 320 }; 321 }; 322 }; 323 324 }; 325 326 tsadc: tsadc { 327 compatible = "rockchip,rk3126-tsadc-virtual"; 328 nvmem-cells = <&cpu_leakage>; 329 nvmem-cell-names = "cpu_leakage"; 330 #thermal-sensor-cells = <1>; 331 status = "disabled"; 332 }; 333 334 xin24m: oscillator { 335 compatible = "fixed-clock"; 336 clock-frequency = <24000000>; 337 clock-output-names = "xin24m"; 338 #clock-cells = <0>; 339 }; 340 341 gpu: gpu@10090000 { 342 compatible = "arm,mali400"; 343 reg = <0x10090000 0x10000>; 344 upthreshold = <40>; 345 downdifferential = <10>; 346 347 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 353 354 interrupt-names = "Mali_GP_IRQ", 355 "Mali_GP_MMU_IRQ", 356 "Mali_PP0_IRQ", 357 "Mali_PP0_MMU_IRQ", 358 "Mali_PP1_IRQ", 359 "Mali_PP1_MMU_IRQ"; 360 clocks = <&cru ACLK_GPU>; 361 #cooling-cells = <2>; /* min followed by max */ 362 clock-names = "clk_mali"; 363 power-domains = <&power RK3128_PD_GPU>; 364 operating-points-v2 = <&gpu_opp_table>; 365 status = "disabled"; 366 367 gpu_power_model: power_model { 368 compatible = "arm,mali-simple-power-model"; 369 voltage = <900>; 370 frequency = <500>; 371 static-power = <300>; 372 dynamic-power = <396>; 373 ts = <32000 4700 (-80) 2>; 374 thermal-zone = "soc-thermal"; 375 }; 376 }; 377 378 gpu_opp_table: opp-table2 { 379 compatible = "operating-points-v2"; 380 381 opp-200000000 { 382 opp-hz = /bits/ 64 <200000000>; 383 opp-microvolt = <975000>; 384 }; 385 opp-300000000 { 386 opp-hz = /bits/ 64 <300000000>; 387 opp-microvolt = <1050000>; 388 }; 389 opp-400000000 { 390 opp-hz = /bits/ 64 <400000000>; 391 opp-microvolt = <1150000>; 392 }; 393 opp-480000000 { 394 opp-hz = /bits/ 64 <480000000>; 395 opp-microvolt = <1250000>; 396 }; 397 }; 398 399 pmu: syscon@100a0000 { 400 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 401 reg = <0x100a0000 0x1000>; 402 #address-cells = <1>; 403 #size-cells = <1>; 404 405 power: power-controller { 406 compatible = "rockchip,rk3128-power-controller"; 407 #power-domain-cells = <1>; 408 #address-cells = <1>; 409 #size-cells = <0>; 410 status = "okay"; 411 412 pd_vio: pd_vio@RK3128_PD_VIO { 413 reg = <RK3128_PD_VIO>; 414 clocks = <&cru ACLK_RGA>, 415 <&cru ACLK_LCDC0>, 416 <&cru ACLK_IEP>, 417 <&cru ACLK_CIF>, 418 <&cru ACLK_VIO0>, 419 <&cru ACLK_VIO1>, 420 <&cru DCLK_VOP>, 421 <&cru DCLK_EBC>, 422 <&cru HCLK_RGA>, 423 <&cru HCLK_VIO>, 424 <&cru HCLK_EBC>, 425 <&cru HCLK_LCDC0>, 426 <&cru HCLK_IEP>, 427 <&cru HCLK_CIF>, 428 <&cru HCLK_VIO_H2P>, 429 <&cru PCLK_MIPI>, 430 <&cru PCLK_MIPIPHY>, 431 <&cru SCLK_VOP>; 432 pm_qos = <&qos_rga>, 433 <&qos_iep>, 434 <&qos_lcdc0>, 435 <&qos_vip0>; 436 }; 437 pd_video@RK3128_PD_VIDEO { 438 reg = <RK3128_PD_VIDEO>; 439 clocks = <&cru ACLK_VEPU>, 440 <&cru ACLK_VDPU>, 441 <&cru HCLK_VEPU>, 442 <&cru HCLK_VDPU>, 443 <&cru SCLK_HEVC_CORE>; 444 pm_qos = <&qos_vpu>; 445 }; 446 pd_gpu@RK3128_PD_GPU { 447 reg = <RK3128_PD_GPU>; 448 clocks = <&cru ACLK_GPU>; 449 pm_qos = <&qos_gpu>; 450 }; 451 }; 452 453 reboot_mode: reboot-mode { 454 compatible = "syscon-reboot-mode"; 455 offset = <0x38>; 456 mode-bootloader = <BOOT_BL_DOWNLOAD>; 457 mode-charge = <BOOT_CHARGING>; 458 mode-fastboot = <BOOT_FASTBOOT>; 459 mode-loader = <BOOT_BL_DOWNLOAD>; 460 mode-normal = <BOOT_NORMAL>; 461 mode-recovery = <BOOT_RECOVERY>; 462 mode-ums = <BOOT_UMS>; 463 }; 464 }; 465 466 mpp_srv: mpp-srv { 467 compatible = "rockchip,mpp-service"; 468 rockchip,taskqueue-count = <1>; 469 rockchip,resetgroup-count = <1>; 470 rockchip,grf = <&grf>; 471 rockchip,grf-offset = <0x0144>; 472 rockchip,grf-values = <0x04000400>, <0x04000400>; 473 rockchip,grf-names = "grf_vdpu1", "grf_vepu1"; 474 status = "disabled"; 475 }; 476 477 hevc: hevc@10104000 { 478 compatible = "rockchip,hevc-decoder"; 479 reg = <0x10104000 0x400>; 480 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 481 interrupt-names = "irq_dec"; 482 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>, 483 <&cru SCLK_HEVC_CORE>; 484 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 485 resets = <&cru SRST_VCODEC_H>, <&cru SRST_VCODEC_A>, 486 <&cru SRST_HEVC_CORE>; 487 reset-names = "shared_video_h", "shared_video_a", 488 "video_core"; 489 iommus = <&hevc_mmu>; 490 power-domains = <&power RK3128_PD_VIDEO>; 491 rockchip,srv = <&mpp_srv>; 492 rockchip,taskqueue-node = <0>; 493 rockchip,resetgroup-node = <0>; 494 status = "disabled"; 495 }; 496 497 hevc_mmu: iommu@10104440 { 498 compatible = "rockchip,iommu"; 499 reg = <0x10104440 0x40>, <0x10104480 0x40>; 500 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 501 interrupt-names = "hevc_mmu"; 502 clock-names = "aclk", "iface"; 503 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>; 504 power-domains = <&power RK3128_PD_VIDEO>; 505 #iommu-cells = <0>; 506 status = "disabled"; 507 }; 508 509 vepu: vepu@0x10106000 { 510 compatible = "rockchip,vpu-encoder-v1"; 511 reg = <0x10106000 0x400>; 512 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 513 interrupt-names = "irq_enc"; 514 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>; 515 clock-names = "aclk_vcodec", "hclk_vcodec"; 516 resets = <&cru SRST_VCODEC_H>, <&cru SRST_VCODEC_A>; 517 reset-names = "shared_video_h", "shared_video_a"; 518 iommus = <&vpu_mmu>; 519 power-domains = <&power RK3128_PD_VIDEO>; 520 rockchip,srv = <&mpp_srv>; 521 rockchip,taskqueue-node = <0>; 522 rockchip,resetgroup-node = <0>; 523 status = "disabled"; 524 }; 525 526 vdpu: vdpu@10106400 { 527 compatible = "rockchip,vpu-decoder-v1"; 528 reg = <0x10106400 0x400>; 529 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 530 interrupt-names = "irq_dec"; 531 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>; 532 clock-names = "aclk_vcodec", "hclk_vcodec"; 533 resets = <&cru SRST_VCODEC_H>, <&cru SRST_VCODEC_A>; 534 reset-names = "shared_video_h", "shared_video_a"; 535 iommus = <&vpu_mmu>; 536 power-domains = <&power RK3128_PD_VIDEO>; 537 rockchip,srv = <&mpp_srv>; 538 rockchip,taskqueue-node = <0>; 539 rockchip,resetgroup-node = <0>; 540 status = "disabled"; 541 }; 542 543 vpu_mmu: iommu@10106800 { 544 compatible = "rockchip,iommu"; 545 reg = <0x10106800 0x40>; 546 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 547 interrupt-names = "vpu_mmu"; 548 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>; 549 clock-names = "aclk", "iface"; 550 power-domains = <&power RK3128_PD_VIDEO>; 551 #iommu-cells = <0>; 552 status = "disabled"; 553 }; 554 555 iep: iep@10108000 { 556 compatible = "rockchip,iep"; 557 iommu_enabled = <1>; 558 iommus = <&iep_mmu>; 559 reg = <0x10108000 0x800>; 560 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 561 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 562 clock-names = "aclk_iep", "hclk_iep"; 563 power-domains = <&power RK3128_PD_VIO>; 564 allocator = <1>; 565 version = <1>; 566 status = "disabled"; 567 }; 568 569 iep_mmu: iommu@10108800 { 570 compatible = "rockchip,iommu"; 571 reg = <0x10108800 0x40>; 572 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 573 interrupt-names = "iep_mmu"; 574 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 575 clock-names = "aclk", "iface"; 576 power-domains = <&power RK3128_PD_VIO>; 577 #iommu-cells = <0>; 578 status = "disabled"; 579 }; 580 581 cif: cif@1010a000 { 582 compatible = "rockchip,cif"; 583 reg = <0x1010a000 0x200>; 584 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, 586 <&cru SCLK_CIF_SRC>, <&cru SCLK_CIF_OUT>; 587 clock-names = "aclk_cif0", "hclk_cif0", 588 "cif0_in", "cif0_out"; 589 resets = <&cru SRST_CIF0>; 590 reset-names = "rst_cif"; 591 power-domains = <&power RK3128_PD_VIO>; 592 status = "disabled"; 593 }; 594 595 cif_new: cif-new@1010a000 { 596 compatible = "rockchip,rk3128-cif"; 597 reg = <0x1010a000 0x200>; 598 599 clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, 600 <&cru SCLK_CIF_OUT>; 601 clock-names = "aclk_cif", "hclk_cif", 602 "sclk_cif_out"; 603 resets = <&cru SRST_CIF0>; 604 reset-names = "rst_cif"; 605 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 606 /* rk312x has not iommu attached */ 607 /* iommus = <&cif_mmu>; */ 608 power-domains = <&power RK3128_PD_VIO>; 609 610 status = "disabled"; 611 }; 612 613 rga: rga@1010c000 { 614 compatible = "rockchip,rk312x-rga"; 615 reg = <0x1010c000 0x1000>; 616 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; 618 clock-names = "aclk_rga", "hclk_rga", "sclk_rga"; 619 power-domains = <&power RK3128_PD_VIO>; 620 status = "disabled"; 621 }; 622 623 vop: vop@1010e000 { 624 compatible = "rockchip,rk3126-vop"; 625 reg = <0x1010e000 0x100>, <0x1010ec00 0x400>; 626 reg-names = "regs", "gamma_lut"; 627 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_VOP>, <&cru HCLK_LCDC0>; 629 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 630 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_D>, <&cru SRST_VOP_H>; 631 reset-names = "axi", "ahb", "dclk"; 632 iommus = <&vop_mmu>; 633 power-domains = <&power RK3128_PD_VIO>; 634 status = "disabled"; 635 636 vop_out: port { 637 #address-cells = <1>; 638 #size-cells = <0>; 639 640 vop_out_dsi: endpoint@0 { 641 reg = <0>; 642 remote-endpoint = <&dsi_in_vop>; 643 }; 644 645 vop_out_lvds: endpoint@1 { 646 reg = <1>; 647 remote-endpoint = <&lvds_in_vop>; 648 }; 649 650 vop_out_rgb: endpoint@2 { 651 reg = <2>; 652 remote-endpoint = <&rgb_in_vop>; 653 }; 654 }; 655 }; 656 657 vop_mmu: iommu@1010e300 { 658 compatible = "rockchip,iommu"; 659 reg = <0x1010e300 0x100>; 660 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 661 interrupt-names = "vop_mmu"; 662 clocks = <&cru ACLK_LCDC0>, <&cru HCLK_LCDC0>; 663 clock-names = "aclk", "iface"; 664 power-domains = <&power RK3128_PD_VIO>; 665 #iommu-cells = <0>; 666 rockchip,disable-device-link-resume; 667 status = "disabled"; 668 }; 669 670 dsi: dsi@10110000 { 671 compatible = "rockchip,rk3128-mipi-dsi"; 672 reg = <0x10110000 0x4000>; 673 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 674 clocks = <&cru PCLK_MIPI>, <&cru HCLK_VIO_H2P>; 675 clock-names = "pclk", "hclk"; 676 resets = <&cru SRST_VIO_MIPI_DSI>; 677 reset-names = "apb"; 678 phys = <&video_phy>; 679 phy-names = "dphy"; 680 power-domains = <&power RK3128_PD_VIO>; 681 rockchip,grf = <&grf>; 682 #address-cells = <1>; 683 #size-cells = <0>; 684 status = "disabled"; 685 686 ports { 687 port { 688 dsi_in_vop: endpoint { 689 remote-endpoint = <&vop_out_dsi>; 690 }; 691 }; 692 }; 693 }; 694 695 qos_gpu: qos@1012d000 { 696 compatible = "syscon"; 697 reg = <0x1012d000 0x20>; 698 }; 699 700 qos_vpu: qos@1012e000 { 701 compatible = "syscon"; 702 reg = <0x1012e000 0x20>; 703 }; 704 705 qos_rga: qos@1012f000 { 706 compatible = "syscon"; 707 reg = <0x1012f000 0x20>; 708 }; 709 710 qos_iep: qos@1012f100 { 711 compatible = "syscon"; 712 reg = <0x1012f100 0x20>; 713 }; 714 715 qos_lcdc0: qos@1012f180 { 716 compatible = "syscon"; 717 reg = <0x1012f180 0x20>; 718 }; 719 720 qos_vip0: qos@1012f200 { 721 compatible = "syscon"; 722 reg = <0x1012f200 0x20>; 723 }; 724 725 gic: interrupt-controller@10139000 { 726 compatible = "arm,cortex-a7-gic"; 727 interrupt-controller; 728 #interrupt-cells = <3>; 729 #address-cells = <0>; 730 731 reg = <0x10139000 0x1000>, 732 <0x1013a000 0x1000>, 733 <0x1013c000 0x2000>, 734 <0x1013e000 0x2000>; 735 interrupts = <GIC_PPI 9 0xf04>; 736 }; 737 738 usb_otg: usb@10180000 { 739 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", 740 "snps,dwc2"; 741 reg = <0x10180000 0x40000>; 742 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 743 clocks = <&cru HCLK_OTG>; 744 clock-names = "otg"; 745 dr_mode = "otg"; 746 g-np-tx-fifo-size = <16>; 747 g-rx-fifo-size = <280>; 748 g-tx-fifo-size = <256 128 128 64 32 16>; 749 g-use-dma; 750 phys = <&u2phy_otg>; 751 phy-names = "usb2-phy"; 752 status = "disabled"; 753 }; 754 755 usb_host_ehci: usb@101c0000 { 756 compatible = "generic-ehci"; 757 reg = <0x101c0000 0x20000>; 758 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 759 clocks = <&cru HCLK_HOST2>, <&u2phy>; 760 clock-names = "usbhost", "utmi"; 761 phys = <&u2phy_host>; 762 phy-names = "usb"; 763 status = "disabled"; 764 }; 765 766 usb_host_ohci: usb@101e0000 { 767 compatible = "generic-ohci"; 768 reg = <0x101e0000 0x20000>; 769 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 770 clocks = <&cru HCLK_HOST2>, <&u2phy>; 771 clock-names = "usbhost", "utmi"; 772 phys = <&u2phy_host>; 773 phy-names = "usb"; 774 status = "disabled"; 775 }; 776 777 i2s_8ch: i2s-8ch@10200000 { 778 compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s"; 779 reg = <0x10200000 0x1000>; 780 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S_8CH>; 781 clock-names = "i2s_clk", "i2s_hclk"; 782 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 783 dmas = <&pdma 14>, <&pdma 15>; 784 dma-names = "tx", "rx"; 785 resets = <&cru SRST_I2S_8CH>; 786 reset-names = "reset-m"; 787 status = "disabled"; 788 }; 789 790 spdif: spdif@10204000 { 791 compatible = "rockchip,rk3128-spdif"; 792 reg = <0x10204000 0x1000>; 793 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 794 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>; 795 clock-names = "mclk", "hclk"; 796 dmas = <&pdma 13>; 797 dma-names = "tx"; 798 pinctrl-names = "default"; 799 pinctrl-0 = <&spdif_tx>; 800 status = "disabled"; 801 }; 802 803 sfc: sfc@1020c000 { 804 compatible = "rockchip,sfc"; 805 reg = <0x1020c000 0x8000>; 806 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 807 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 808 clock-names = "clk_sfc", "hclk_sfc"; 809 assigned-clocks = <&cru SCLK_SFC>; 810 assigned-clock-rates = <60000000>; 811 status = "disabled"; 812 }; 813 814 i2s_2ch: i2s-2ch@10220000 { 815 compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s"; 816 reg = <0x10220000 0x1000>; 817 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S_2CH>; 818 clock-names = "i2s_clk", "i2s_hclk"; 819 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 820 dmas = <&pdma 0>, <&pdma 1>; 821 dma-names = "tx", "rx"; 822 resets = <&cru SRST_I2S_2CH>; 823 reset-names = "reset-m"; 824 status = "disabled"; 825 }; 826 827 sdmmc: dwmmc@10214000 { 828 compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc"; 829 reg = <0x10214000 0x4000>; 830 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 831 #address-cells = <1>; 832 #size-cells = <0>; 833 pinctrl-names = "default"; 834 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 835 max-frequency = <50000000>; 836 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 837 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 838 dmas = <&pdma 10>; 839 dma-names = "rx-tx"; 840 fifo-depth = <0x100>; 841 bus-width = <4>; 842 status = "disabled"; 843 }; 844 845 sdio: dwmmc@10218000 { 846 compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc"; 847 reg = <0x10218000 0x4000>; 848 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 849 #address-cells = <1>; 850 #size-cells = <0>; 851 pinctrl-names = "default"; 852 pinctrl-0 = <&sdio_pwren &sdio_cmd &sdio_clk &sdio_bus4>; 853 clock-freq-min-max = <400000 50000000>; 854 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; 855 clock-names = "biu", "ciu"; 856 dmas = <&pdma 11>; 857 dma-names = "rx-tx"; 858 num-slots = <1>; 859 fifo-depth = <0x100>; 860 bus-width = <4>; 861 status = "disabled"; 862 }; 863 864 emmc: dwmmc@1021c000 { 865 compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc"; 866 reg = <0x1021c000 0x4000>; 867 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 868 #address-cells = <1>; 869 #size-cells = <0>; 870 clock-freq-min-max = <400000 50000000>; 871 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; 872 clock-names = "biu", "ciu"; 873 dmas = <&pdma 12>; 874 dma-names = "rx-tx"; 875 num-slots = <1>; 876 fifo-depth = <0x100>; 877 bus-width = <8>; 878 status = "disabled"; 879 }; 880 881 nandc: nandc@10500000 { 882 compatible = "rockchip,rk-nandc"; 883 reg = <0x10500000 0x4000>; 884 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 885 nandc_id = <0>; 886 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 887 clock-names = "clk_nandc", "hclk_nandc"; 888 status = "disabled"; 889 }; 890 891 cru: clock-controller@20000000 { 892 compatible = "rockchip,rk3128-cru"; 893 reg = <0x20000000 0x1000>; 894 rockchip,grf = <&grf>; 895 #clock-cells = <1>; 896 #reset-cells = <1>; 897 assigned-clocks = <&cru PLL_GPLL>, 898 <&cru ACLK_CPU>, <&cru HCLK_CPU>, 899 <&cru PCLK_CPU>, <&cru ACLK_PERI>, 900 <&cru HCLK_PERI>, <&cru PCLK_PERI>; 901 assigned-clock-rates = <594000000>, 902 <300000000>, <150000000>, 903 <75000000>, <300000000>, 904 <150000000>, <75000000>; 905 }; 906 907 grf: syscon@20008000 { 908 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd"; 909 reg = <0x20008000 0x1000>; 910 #address-cells = <1>; 911 #size-cells = <1>; 912 913 lvds: lvds { 914 compatible = "rockchip,rk3126-lvds"; 915 phys = <&video_phy>; 916 phy-names = "phy"; 917 status = "disabled"; 918 919 ports { 920 #address-cells = <1>; 921 #size-cells = <0>; 922 923 port@0 { 924 reg = <0>; 925 926 lvds_in_vop: endpoint { 927 remote-endpoint = <&vop_out_lvds>; 928 }; 929 }; 930 }; 931 }; 932 933 rgb: rgb { 934 compatible = "rockchip,rk3128-rgb"; 935 phys = <&video_phy>; 936 phy-names = "phy"; 937 pinctrl-names = "default", "sleep"; 938 pinctrl-0 = <&lcdc_rgb_pins>; 939 pinctrl-1 = <&lcdc_sleep_pins>; 940 status = "disabled"; 941 942 ports { 943 #address-cells = <1>; 944 #size-cells = <0>; 945 946 port@0 { 947 reg = <0>; 948 949 rgb_in_vop: endpoint { 950 remote-endpoint = <&vop_out_rgb>; 951 }; 952 }; 953 }; 954 }; 955 956 u2phy: usb2-phy@17c { 957 compatible = "rockchip,rk3128-usb2phy"; 958 reg = <0x017c 0x0c>; 959 clocks = <&cru SCLK_OTGPHY0>; 960 clock-names = "phyclk"; 961 #clock-cells = <0>; 962 clock-output-names = "usb480m_phy"; 963 assigned-clocks = <&cru SCLK_USB480M>; 964 assigned-clock-parents = <&u2phy>; 965 status = "disabled"; 966 967 u2phy_otg: otg-port { 968 #phy-cells = <0>; 969 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 972 interrupt-names = "otg-bvalid", "otg-id", 973 "linestate"; 974 status = "disabled"; 975 }; 976 977 u2phy_host: host-port { 978 #phy-cells = <0>; 979 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 980 interrupt-names = "linestate"; 981 status = "disabled"; 982 }; 983 }; 984 }; 985 986 codec: codec@20030000 { 987 compatible = "rockchip,rk3128-codec"; 988 reg = <0x20030000 0x4000>; 989 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 990 boot_depop = <1>; 991 pa_enable_time = <1000>; 992 rockchip,grf = <&grf>; 993 clocks = <&cru PCLK_ACODEC>, <&cru SCLK_I2S1>; 994 clock-names = "g_pclk_acodec", "i2s_clk"; 995 status = "disabled"; 996 }; 997 998 video_phy: video-phy@20038000 { 999 compatible = "rockchip,rk3128-dsi-dphy", "rockchip,rk3128-video-phy"; 1000 reg = <0x20038000 0x4000>, <0x10110000 0x4000>; 1001 reg-names = "phy", "host"; 1002 clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>, 1003 <&cru PCLK_MIPI>; 1004 clock-names = "ref", "pclk", "pclk_host"; 1005 #clock-cells = <0>; 1006 resets = <&cru SRST_MIPIPHY_P>; 1007 reset-names = "apb"; 1008 power-domains = <&power RK3128_PD_VIO>; 1009 #phy-cells = <0>; 1010 status = "disabled"; 1011 }; 1012 1013 timer@20044000 { 1014 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; 1015 reg = <0x20044000 0x20>; 1016 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1017 clocks = <&xin24m>, <&cru PCLK_TIMER>; 1018 clock-names = "timer", "pclk"; 1019 }; 1020 1021 watchdog@2004c000 { 1022 compatible = "snps,dw-wdt"; 1023 reg = <0x2004c000 0x100>; 1024 clocks = <&cru PCLK_WDT>; 1025 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1026 status = "disabled"; 1027 }; 1028 1029 pwm0: pwm@20050000 { 1030 compatible = "rockchip,rk3288-pwm"; 1031 reg = <0x20050000 0x10>; 1032 #pwm-cells = <3>; 1033 pinctrl-names = "active"; 1034 pinctrl-0 = <&pwm0_pin>; 1035 clocks = <&cru PCLK_PWM>; 1036 clock-names = "pwm"; 1037 status = "disabled"; 1038 }; 1039 1040 pwm1: pwm@20050010 { 1041 compatible = "rockchip,rk3288-pwm"; 1042 reg = <0x20050010 0x10>; 1043 #pwm-cells = <3>; 1044 pinctrl-names = "active"; 1045 pinctrl-0 = <&pwm1_pin>; 1046 clocks = <&cru PCLK_PWM>; 1047 clock-names = "pwm"; 1048 status = "disabled"; 1049 }; 1050 1051 pwm2: pwm@20050020 { 1052 compatible = "rockchip,rk3288-pwm"; 1053 reg = <0x20050020 0x10>; 1054 #pwm-cells = <3>; 1055 pinctrl-names = "active"; 1056 pinctrl-0 = <&pwm2_pin>; 1057 clocks = <&cru PCLK_PWM>; 1058 clock-names = "pwm"; 1059 status = "disabled"; 1060 }; 1061 1062 pwm3: pwm@20050030 { 1063 compatible = "rockchip,rk3288-pwm"; 1064 reg = <0x20050030 0x10>; 1065 #pwm-cells = <3>; 1066 pinctrl-names = "active"; 1067 pinctrl-0 = <&pwm3_pin>; 1068 clocks = <&cru PCLK_PWM>; 1069 clock-names = "pwm"; 1070 status = "disabled"; 1071 }; 1072 1073 i2c1: i2c@20056000 { 1074 compatible = "rockchip,rk3288-i2c"; 1075 reg = <0x20056000 0x1000>; 1076 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1077 #address-cells = <1>; 1078 #size-cells = <0>; 1079 clock-names = "i2c"; 1080 clocks = <&cru PCLK_I2C1>; 1081 pinctrl-names = "default"; 1082 pinctrl-0 = <&i2c1_xfer>; 1083 status = "disabled"; 1084 }; 1085 1086 i2c2: i2c@2005a000 { 1087 compatible = "rockchip,rk3288-i2c"; 1088 reg = <0x2005a000 0x1000>; 1089 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 clock-names = "i2c"; 1093 clocks = <&cru PCLK_I2C2>; 1094 pinctrl-names = "default"; 1095 pinctrl-0 = <&i2c2_xfer>; 1096 status = "disabled"; 1097 }; 1098 1099 i2c3: i2c@2005e000 { 1100 compatible = "rockchip,rk3288-i2c"; 1101 reg = <0x2005e000 0x1000>; 1102 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1103 #address-cells = <1>; 1104 #size-cells = <0>; 1105 clock-names = "i2c"; 1106 clocks = <&cru PCLK_I2C3>; 1107 pinctrl-names = "default"; 1108 pinctrl-0 = <&i2c3_xfer>; 1109 status = "disabled"; 1110 }; 1111 1112 uart0: serial@20060000 { 1113 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 1114 reg = <0x20060000 0x100>; 1115 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1116 clock-frequency = <24000000>; 1117 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 1118 clock-names = "baudclk", "apb_pclk"; 1119 reg-shift = <2>; 1120 reg-io-width = <4>; 1121 pinctrl-names = "default"; 1122 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 1123 status = "disabled"; 1124 }; 1125 1126 uart1: serial@20064000 { 1127 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 1128 reg = <0x20064000 0x100>; 1129 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1130 clock-frequency = <24000000>; 1131 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1132 clock-names = "baudclk", "apb_pclk"; 1133 reg-shift = <2>; 1134 reg-io-width = <4>; 1135 pinctrl-names = "default"; 1136 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 1137 status = "disabled"; 1138 }; 1139 1140 uart2: serial@20068000 { 1141 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 1142 reg = <0x20068000 0x100>; 1143 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1144 clock-frequency = <24000000>; 1145 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1146 clock-names = "baudclk", "apb_pclk"; 1147 reg-shift = <2>; 1148 reg-io-width = <4>; 1149 pinctrl-names = "default"; 1150 pinctrl-0 = <&uart2_xfer>; 1151 status = "disabled"; 1152 }; 1153 1154 saradc: saradc@2006c000 { 1155 compatible = "rockchip,saradc"; 1156 reg = <0x2006c000 0x100>; 1157 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1158 #io-channel-cells = <1>; 1159 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 1160 clock-names = "saradc", "apb_pclk"; 1161 resets = <&cru SRST_SARADC>; 1162 reset-names = "saradc-apb"; 1163 status = "disabled"; 1164 }; 1165 1166 i2c0: i2c@20072000 { 1167 compatible = "rockchip,rk3288-i2c"; 1168 reg = <0x20072000 0x1000>; 1169 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1170 #address-cells = <1>; 1171 #size-cells = <0>; 1172 clock-names = "i2c"; 1173 clocks = <&cru PCLK_I2C0>; 1174 pinctrl-names = "default"; 1175 pinctrl-0 = <&i2c0_xfer>; 1176 status = "disabled"; 1177 }; 1178 1179 spi0: spi@20074000 { 1180 compatible = "rockchip,rk3288-spi"; 1181 reg = <0x20074000 0x1000>; 1182 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1183 pinctrl-names = "default"; 1184 pinctrl-0 = <&spi0m0_tx &spi0m0_rx &spi0m0_clk &spi0m0_cs0 &spi0m0_cs1>; 1185 clock-names = "spiclk", "apb_pclk"; 1186 dmas = <&pdma 8>, <&pdma 9>; 1187 dma-names = "tx", "rx"; 1188 #address-cells = <1>; 1189 #size-cells = <0>; 1190 status = "disabled"; 1191 }; 1192 1193 gmac: eth@2008c000 { 1194 compatible = "rockchip,rk3128-gmac"; 1195 reg = <0x2008c000 0x4000>; 1196 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1198 interrupt-names = "macirq", "eth_wake_irq"; 1199 rockchip,grf = <&grf>; 1200 clocks = <&cru SCLK_MAC>, 1201 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 1202 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>, 1203 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 1204 clock-names = "stmmaceth", 1205 "mac_clk_rx", "mac_clk_tx", 1206 "clk_mac_ref", "clk_mac_refout", 1207 "aclk_mac", "pclk_mac"; 1208 resets = <&cru SRST_GMAC>; 1209 reset-names = "stmmaceth"; 1210 status = "disabled"; 1211 }; 1212 1213 efuse: efuse@20090000 { 1214 compatible = "rockchip,rk3128-efuse"; 1215 reg = <0x20090000 0x20>; 1216 #address-cells = <1>; 1217 #size-cells = <1>; 1218 clocks = <&cru PCLK_EFUSE>; 1219 clock-names = "pclk_efuse"; 1220 1221 efuse_id: id@7 { 1222 reg = <0x7 0x10>; 1223 }; 1224 cpu_leakage: cpu_leakage@17 { 1225 reg = <0x17 0x1>; 1226 }; 1227 }; 1228 1229 rockchip_system_monitor: rockchip-system-monitor { 1230 compatible = "rockchip,system-monitor"; 1231 }; 1232 1233 pinctrl: pinctrl { 1234 compatible = "rockchip,rk3128-pinctrl"; 1235 rockchip,grf = <&grf>; 1236 #address-cells = <1>; 1237 #size-cells = <1>; 1238 ranges; 1239 1240 gpio0: gpio0@2007c000 { 1241 compatible = "rockchip,gpio-bank"; 1242 reg = <0x2007c000 0x100>; 1243 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1244 clocks = <&cru PCLK_GPIO0>; 1245 1246 gpio-controller; 1247 #gpio-cells = <2>; 1248 1249 interrupt-controller; 1250 #interrupt-cells = <2>; 1251 }; 1252 1253 gpio1: gpio1@20080000 { 1254 compatible = "rockchip,gpio-bank"; 1255 reg = <0x20080000 0x100>; 1256 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1257 clocks = <&cru PCLK_GPIO1>; 1258 1259 gpio-controller; 1260 #gpio-cells = <2>; 1261 1262 interrupt-controller; 1263 #interrupt-cells = <2>; 1264 }; 1265 1266 gpio2: gpio2@20084000 { 1267 compatible = "rockchip,gpio-bank"; 1268 reg = <0x20084000 0x100>; 1269 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1270 clocks = <&cru PCLK_GPIO2>; 1271 1272 gpio-controller; 1273 #gpio-cells = <2>; 1274 1275 interrupt-controller; 1276 #interrupt-cells = <2>; 1277 }; 1278 1279 gpio3: gpio3@20088000 { 1280 compatible = "rockchip,gpio-bank"; 1281 reg = <0x20088000 0x100>; 1282 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1283 clocks = <&cru PCLK_GPIO3>; 1284 1285 gpio-controller; 1286 #gpio-cells = <2>; 1287 1288 interrupt-controller; 1289 #interrupt-cells = <2>; 1290 }; 1291 1292 pcfg_pull_default: pcfg_pull_default { 1293 bias-pull-pin-default; 1294 }; 1295 1296 pcfg_output_high: pcfg-output-high { 1297 output-high; 1298 }; 1299 1300 pcfg_pull_none: pcfg-pull-none { 1301 bias-disable; 1302 }; 1303 1304 emmc { 1305 emmc_clk: emmc-clk { 1306 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; 1307 }; 1308 1309 emmc_cmd: emmc-cmd { 1310 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>; 1311 }; 1312 1313 emmc_cmd1: emmc-cmd1 { 1314 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>; 1315 }; 1316 1317 emmc_pwr: emmc-pwr { 1318 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>; 1319 }; 1320 1321 emmc_bus1: emmc-bus1 { 1322 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>; 1323 }; 1324 1325 emmc_bus4: emmc-bus4 { 1326 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 1327 <1 RK_PD1 2 &pcfg_pull_default>, 1328 <1 RK_PD2 2 &pcfg_pull_default>, 1329 <1 RK_PD3 2 &pcfg_pull_default>; 1330 }; 1331 1332 emmc_bus8: emmc-bus8 { 1333 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 1334 <1 RK_PD1 2 &pcfg_pull_default>, 1335 <1 RK_PD2 2 &pcfg_pull_default>, 1336 <1 RK_PD3 2 &pcfg_pull_default>, 1337 <1 RK_PD4 2 &pcfg_pull_default>, 1338 <1 RK_PD5 2 &pcfg_pull_default>, 1339 <1 RK_PD6 2 &pcfg_pull_default>, 1340 <1 RK_PD7 2 &pcfg_pull_default>; 1341 }; 1342 }; 1343 1344 i2c0 { 1345 i2c0_xfer: i2c0-xfer { 1346 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 1347 <0 RK_PA1 1 &pcfg_pull_none>; 1348 }; 1349 }; 1350 1351 i2c1 { 1352 i2c1_xfer: i2c1-xfer { 1353 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 1354 <0 RK_PA3 1 &pcfg_pull_none>; 1355 }; 1356 }; 1357 1358 i2c2 { 1359 i2c2_xfer: i2c2-xfer { 1360 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, 1361 <2 RK_PC5 3 &pcfg_pull_none>; 1362 }; 1363 }; 1364 1365 i2c3 { 1366 i2c3_xfer: i2c3-xfer { 1367 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 1368 <0 RK_PA7 1 &pcfg_pull_none>; 1369 }; 1370 }; 1371 1372 lcdc { 1373 lcdc_rgb_pins: lcdc-rgb-pins { 1374 rockchip,pins = 1375 <2 RK_PB0 1 &pcfg_pull_none>, /* LCDC_DCLK */ 1376 <2 RK_PB1 1 &pcfg_pull_none>, /* LCDC_HSYNC */ 1377 <2 RK_PB2 1 &pcfg_pull_none>, /* LCDC_VSYNC */ 1378 <2 RK_PB3 1 &pcfg_pull_none>, /* LCDC_DEN */ 1379 <2 RK_PB4 1 &pcfg_pull_none>, /* LCDC_DATA10 */ 1380 <2 RK_PB5 1 &pcfg_pull_none>, /* LCDC_DATA11 */ 1381 <2 RK_PB6 1 &pcfg_pull_none>, /* LCDC_DATA12 */ 1382 <2 RK_PB7 1 &pcfg_pull_none>, /* LCDC_DATA13 */ 1383 <2 RK_PC0 1 &pcfg_pull_none>, /* LCDC_DATA14 */ 1384 <2 RK_PC1 1 &pcfg_pull_none>, /* LCDC_DATA15 */ 1385 <2 RK_PC2 1 &pcfg_pull_none>, /* LCDC_DATA16 */ 1386 <2 RK_PC3 1 &pcfg_pull_none>, /* LCDC_DATA17 */ 1387 <2 RK_PC4 1 &pcfg_pull_none>, /* LCDC_DATA18 */ 1388 <2 RK_PC5 1 &pcfg_pull_none>, /* LCDC_DATA19 */ 1389 <2 RK_PC6 1 &pcfg_pull_none>, /* LCDC_DATA20 */ 1390 <2 RK_PC7 1 &pcfg_pull_none>, /* LCDC_DATA21 */ 1391 <2 RK_PD0 1 &pcfg_pull_none>, /* LCDC_DATA22 */ 1392 <2 RK_PD1 1 &pcfg_pull_none>; /* LCDC_DATA23 */ 1393 }; 1394 1395 lcdc_sleep_pins: lcdc-sleep-pins { 1396 rockchip,pins = 1397 <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DCLK */ 1398 <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_HSYNC */ 1399 <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_VSYNC */ 1400 <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DEN */ 1401 <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DATA10 */ 1402 <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DATA11 */ 1403 <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DATA12 */ 1404 <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DATA13 */ 1405 <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DATA14 */ 1406 <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DATA15 */ 1407 <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DATA16 */ 1408 <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DATA17 */ 1409 <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DATA18 */ 1410 <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DATA19 */ 1411 <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DATA20 */ 1412 <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DATA21 */ 1413 <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DATA22 */ 1414 <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; /* LCDC_DATA23 */ 1415 }; 1416 }; 1417 1418 uart0 { 1419 uart0_xfer: uart0-xfer { 1420 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>, 1421 <2 RK_PD3 2 &pcfg_pull_none>; 1422 }; 1423 1424 uart0_cts: uart0-cts { 1425 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>; 1426 }; 1427 1428 uart0_rts: uart0-rts { 1429 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>; 1430 }; 1431 }; 1432 1433 uart1 { 1434 uart1_xfer: uart1-xfer { 1435 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, 1436 <1 RK_PB2 2 &pcfg_pull_default>; 1437 }; 1438 1439 uart1_cts: uart1-cts { 1440 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; 1441 }; 1442 1443 uart1_rts: uart1-rts { 1444 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; 1445 }; 1446 }; 1447 1448 uart2 { 1449 uart2_xfer: uart2-xfer { 1450 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 1451 <1 RK_PC3 2 &pcfg_pull_none>; 1452 }; 1453 1454 uart2_cts: uart2-cts { 1455 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; 1456 }; 1457 1458 uart2_rts: uart2-rts { 1459 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; 1460 }; 1461 }; 1462 1463 sdmmc { 1464 sdmmc_clk: sdmmc-clk { 1465 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 1466 }; 1467 1468 sdmmc_det: sdmmc-det { 1469 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_none>; 1470 }; 1471 1472 sdmmc_cmd: sdmmc-cmd { 1473 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 1474 }; 1475 1476 sdmmc_wp: sdmmc-wp { 1477 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; 1478 }; 1479 1480 sdmmc_pwren: sdmmc-pwren { 1481 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>; 1482 }; 1483 1484 sdmmc_bus4: sdmmc-bus4 { 1485 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 1486 <1 RK_PC3 1 &pcfg_pull_default>, 1487 <1 RK_PC4 1 &pcfg_pull_default>, 1488 <1 RK_PC5 1 &pcfg_pull_default>; 1489 }; 1490 }; 1491 1492 sdio { 1493 sdio_clk: sdio-clk { 1494 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>; 1495 }; 1496 1497 sdio_cmd: sdio-cmd { 1498 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>; 1499 }; 1500 1501 sdio_pwren: sdio-pwren { 1502 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>; 1503 }; 1504 1505 sdio_bus4: sdio-bus4 { 1506 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>, 1507 <1 RK_PA2 2 &pcfg_pull_default>, 1508 <1 RK_PA4 2 &pcfg_pull_default>, 1509 <1 RK_PA5 2 &pcfg_pull_default>; 1510 }; 1511 }; 1512 1513 hdmi { 1514 hdmii2c_xfer: hdmii2c-xfer { 1515 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, 1516 <0 RK_PA7 2 &pcfg_pull_none>; 1517 }; 1518 1519 hdmi_hpd: hdmi-hpd { 1520 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; 1521 }; 1522 1523 hdmi_cec: hdmi-cec { 1524 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; 1525 }; 1526 }; 1527 1528 i2s { 1529 i2s_bus: i2s-bus { 1530 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, 1531 <0 RK_PB1 1 &pcfg_pull_none>, 1532 <0 RK_PB3 1 &pcfg_pull_none>, 1533 <0 RK_PB4 1 &pcfg_pull_none>, 1534 <0 RK_PB5 1 &pcfg_pull_none>, 1535 <0 RK_PB6 1 &pcfg_pull_none>; 1536 }; 1537 1538 i2s1_bus: i2s1-bus { 1539 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>, 1540 <1 RK_PA1 1 &pcfg_pull_none>, 1541 <1 RK_PA2 1 &pcfg_pull_none>, 1542 <1 RK_PA3 1 &pcfg_pull_none>, 1543 <1 RK_PA4 1 &pcfg_pull_none>, 1544 <1 RK_PA5 1 &pcfg_pull_none>; 1545 }; 1546 }; 1547 1548 pwm0 { 1549 pwm0_pin: pwm0-pin { 1550 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>; 1551 }; 1552 }; 1553 1554 pwm1 { 1555 pwm1_pin: pwm1-pin { 1556 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1557 }; 1558 }; 1559 1560 pwm2 { 1561 pwm2_pin: pwm2-pin { 1562 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 1563 }; 1564 }; 1565 1566 pwm3 { 1567 pwm3_pin: pwm3-pin { 1568 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>; 1569 }; 1570 }; 1571 1572 gmac { 1573 rgmii_pins: rgmii-pins { 1574 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 1575 <2 RK_PB1 3 &pcfg_pull_default>, 1576 <2 RK_PB3 3 &pcfg_pull_default>, 1577 <2 RK_PB4 3 &pcfg_pull_default>, 1578 <2 RK_PB5 3 &pcfg_pull_default>, 1579 <2 RK_PB6 3 &pcfg_pull_default>, 1580 <2 RK_PC0 3 &pcfg_pull_default>, 1581 <2 RK_PC1 3 &pcfg_pull_default>, 1582 <2 RK_PC2 3 &pcfg_pull_default>, 1583 <2 RK_PC3 3 &pcfg_pull_default>, 1584 <2 RK_PD1 3 &pcfg_pull_default>, 1585 <2 RK_PC4 4 &pcfg_pull_default>, 1586 <2 RK_PC5 4 &pcfg_pull_default>, 1587 <2 RK_PC6 4 &pcfg_pull_default>, 1588 <2 RK_PC7 4 &pcfg_pull_default>; 1589 }; 1590 1591 rmii_pins: rmii-pins { 1592 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, 1593 <2 RK_PB4 3 &pcfg_pull_default>, 1594 <2 RK_PB5 3 &pcfg_pull_default>, 1595 <2 RK_PB6 3 &pcfg_pull_default>, 1596 <2 RK_PB7 3 &pcfg_pull_default>, 1597 <2 RK_PC0 3 &pcfg_pull_default>, 1598 <2 RK_PC1 3 &pcfg_pull_default>, 1599 <2 RK_PC2 3 &pcfg_pull_default>, 1600 <2 RK_PC3 3 &pcfg_pull_default>, 1601 <2 RK_PD1 3 &pcfg_pull_default>; 1602 }; 1603 }; 1604 1605 spdif { 1606 spdif_tx: spdif-tx { 1607 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 1608 }; 1609 }; 1610 1611 spi0 { 1612 spi0m0_clk: spi0m0-clk { 1613 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>; 1614 }; 1615 1616 spi0m0_cs0: spi0m0-cs0 { 1617 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>; 1618 }; 1619 1620 spi0m0_tx: spi0m0-tx { 1621 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>; 1622 }; 1623 1624 spi0m0_rx: spi0m0-rx { 1625 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>; 1626 }; 1627 1628 spi0m0_cs1: spi0m0-cs1 { 1629 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>; 1630 }; 1631 1632 spi0m1_clk: spi0m1-clk { 1633 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 1634 }; 1635 1636 spi0m1_cs0: spi0m1-cs0 { 1637 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 1638 }; 1639 1640 spi0m1_tx: spi0m1-tx { 1641 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 1642 }; 1643 1644 spi0m1_rx: spi0m1-rx { 1645 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 1646 }; 1647 1648 spi0m1_cs1: spi0m1-cs1 { 1649 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 1650 }; 1651 1652 spi0m2_clk: spi0m2-clk { 1653 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>; 1654 }; 1655 1656 spi0m2_cs0: spi0m2-cs0 { 1657 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>; 1658 }; 1659 1660 spi0m2_tx: spi0m2-tx { 1661 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>; 1662 }; 1663 1664 spi0m2_rx: spi0m2-rx { 1665 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>; 1666 }; 1667 }; 1668 }; 1669}; 1670