1*4882a593Smuzhiyun* Rockchip RV1126 Clock and Reset Unit 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe RV1126 clock controller generates and supplies clock to various 4*4882a593Smuzhiyuncontrollers within the SoC and also implements a reset controller for SoC 5*4882a593Smuzhiyunperipherals. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired Properties: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- compatible: PMU for CRU should be "rockchip,rv1126-pmucru" 10*4882a593Smuzhiyun- compatible: CRU should be "rockchip,rv1126-cru" 11*4882a593Smuzhiyun- reg: physical base address of the controller and length of memory mapped 12*4882a593Smuzhiyun region. 13*4882a593Smuzhiyun- #clock-cells: should be 1. 14*4882a593Smuzhiyun- #reset-cells: should be 1. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunOptional Properties: 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun- rockchip,grf: phandle to the syscon managing the "general register files" 19*4882a593Smuzhiyun If missing, pll rates are not changeable, due to the missing pll lock status. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunEach clock is assigned an identifier and client nodes can use this identifier 22*4882a593Smuzhiyunto specify the clock which they consume. All available clocks are defined as 23*4882a593Smuzhiyunpreprocessor macros in the dt-bindings/clock/rv1126-cru.h headers and can be 24*4882a593Smuzhiyunused in device tree sources. Similar macros exist for the reset sources in 25*4882a593Smuzhiyunthese files. 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunExternal clocks: 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunThere are several clocks that are generated outside the SoC. It is expected 30*4882a593Smuzhiyunthat they are defined using standard clock bindings with following 31*4882a593Smuzhiyunclock-output-names: 32*4882a593Smuzhiyun - "xin24m" - crystal input - required, 33*4882a593Smuzhiyun - "xin32k" - rtc clock - optional, 34*4882a593Smuzhiyun - "i2s8ch_mclkin" - external I2S clock - optional, 35*4882a593Smuzhiyun - "i2s2ch0_mclkin" - external I2S clock - optional, 36*4882a593Smuzhiyun - "i2s2ch1_mclkin" - external I2S clock - optional, 37*4882a593Smuzhiyun - "clk_gmac_rgmii_clkin_m0" - external GMAC clock - optional 38*4882a593Smuzhiyun - "clk_gmac_rgmii_clkin_m1" - external GMAC clock - optional 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunExample: Clock controller node: 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun pmucru: clock-controller@ff480000 { 43*4882a593Smuzhiyun compatible = "rockchip,rv1126-pmucru"; 44*4882a593Smuzhiyun reg = <0x0 0xff480000 0x0 0x1000>; 45*4882a593Smuzhiyun #clock-cells = <1>; 46*4882a593Smuzhiyun #reset-cells = <1>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun cru: clock-controller@ff490000 { 50*4882a593Smuzhiyun compatible = "rockchip,rv1126-cru"; 51*4882a593Smuzhiyun reg = <0x0 0xff490000 0x0 0x1000>; 52*4882a593Smuzhiyun rockchip,grf = <&grf>; 53*4882a593Smuzhiyun #clock-cells = <1>; 54*4882a593Smuzhiyun #reset-cells = <1>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593SmuzhiyunExample: UART controller node that consumes the clock generated by the clock 58*4882a593Smuzhiyun controller: 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun uart0: serial@ff560000 { 61*4882a593Smuzhiyun compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 62*4882a593Smuzhiyun reg = <0xff560000 0x100>; 63*4882a593Smuzhiyun interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 64*4882a593Smuzhiyun reg-shift = <2>; 65*4882a593Smuzhiyun reg-io-width = <4>; 66*4882a593Smuzhiyun clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 67*4882a593Smuzhiyun clock-names = "baudclk", "apb_pclk"; 68*4882a593Smuzhiyun }; 69