1* Rockchip RK3568 Clock and Reset Unit 2 3The RK3568 clock controller generates and supplies clock to various 4controllers within the SoC and also implements a reset controller for SoC 5peripherals. 6 7Required Properties: 8 9- compatible: PMU for CRU should be "rockchip,rk3568-pmucru" 10- compatible: CRU should be "rockchip,rk3568-cru" 11- reg: physical base address of the controller and length of memory mapped 12 region. 13- #clock-cells: should be 1. 14- #reset-cells: should be 1. 15 16Optional Properties: 17 18- rockchip,grf: phandle to the syscon managing the "general register files" 19 If missing, pll rates are not changeable, due to the missing pll lock status. 20 21Each clock is assigned an identifier and client nodes can use this identifier 22to specify the clock which they consume. All available clocks are defined as 23preprocessor macros in the dt-bindings/clock/rk3568-cru.h headers and can be 24used in device tree sources. Similar macros exist for the reset sources in 25these files. 26 27External clocks: 28 29There are several clocks that are generated outside the SoC. It is expected 30that they are defined using standard clock bindings with following 31clock-output-names: 32 - "xin24m" - crystal input - required, 33 - "xin32k" - rtc clock - optional, 34 - "i2sx_mclkin" - external I2S clock - optional, 35 - "xin_osc0_usbphyx_g" - external USBPHY clock - optional, 36 - "xin_osc0_mipidsiphyx_g" - external MIPIDSIPHY clock - optional, 37 38Example: Clock controller node: 39 40 pmucru: clock-controller@fdd00000 { 41 compatible = "rockchip,rK3568-pmucru"; 42 reg = <0x0 0xfdd00000 0x0 0x1000>; 43 #clock-cells = <1>; 44 #reset-cells = <1>; 45 }; 46 47 cru: clock-controller@fdd20000 { 48 compatible = "rockchip,rK3568-cru"; 49 reg = <0x0 0xfdd20000 0x0 0x1000>; 50 rockchip,grf = <&grf>; 51 #clock-cells = <1>; 52 #reset-cells = <1>; 53 }; 54 55Example: UART controller node that consumes the clock generated by the clock 56 controller: 57 58 uart1: serial@fe650000 { 59 compatible = "rockchip,rK3568-uart", "snps,dw-apb-uart"; 60 reg = <0x0 0xfe650000 0x0 0x100>; 61 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 62 reg-shift = <2>; 63 reg-io-width = <4>; 64 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 65 clock-names = "baudclk", "apb_pclk"; 66 }; 67