1 /****************************************************************************** 2 * 3 * Copyright(c) 2019 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef __PHL_TRX_DEF_H_ 16 #define __PHL_TRX_DEF_H_ 17 18 /* core / phl common structrue */ 19 20 #ifndef MAX_PHL_TX_RING_ENTRY_NUM 21 #define MAX_PHL_TX_RING_ENTRY_NUM 4096 22 #endif /*MAX_PHL_TX_RING_ENTRY_NUM*/ 23 24 #ifndef MAX_PHL_RX_RING_ENTRY_NUM 25 #define MAX_PHL_RX_RING_ENTRY_NUM 4096 26 #endif /*MAX_PHL_RX_RING_ENTRY_NUM*/ 27 #define MAX_PHL_RING_CAT_NUM 10 /* 8 tid + 1 mgnt + 1 hiq*/ 28 29 30 #ifdef CONFIG_RTW_REDUCE_MEM 31 #define MAX_PHL_RING_RX_PKT_NUM MAX_PHL_RX_RING_ENTRY_NUM 32 #else 33 #define MAX_PHL_RING_RX_PKT_NUM 8192 34 #endif 35 #define MAX_RX_BUF_SEG_NUM 4 36 37 #define _H2CB_CMD_QLEN 32 38 #define _H2CB_DATA_QLEN 32 39 #define _H2CB_LONG_DATA_QLEN 200 /* should be refined */ 40 #define MAX_H2C_PKT_NUM (_H2CB_CMD_QLEN + _H2CB_DATA_QLEN + _H2CB_LONG_DATA_QLEN) 41 42 #define FWCMD_HDR_LEN 8 43 #define _WD_BODY_LEN 24 44 #define H2C_CMD_LEN 64 45 #define H2C_DATA_LEN 256 46 #define H2C_LONG_DATA_LEN 2048 47 48 #define get_h2c_size_by_range(i) \ 49 ((i < _H2CB_CMD_QLEN) ? \ 50 (FWCMD_HDR_LEN + _WD_BODY_LEN + H2C_CMD_LEN) : \ 51 ((i < (_H2CB_CMD_QLEN + _H2CB_DATA_QLEN)) ? \ 52 (FWCMD_HDR_LEN + _WD_BODY_LEN + H2C_DATA_LEN) : \ 53 (FWCMD_HDR_LEN + _WD_BODY_LEN + H2C_LONG_DATA_LEN))) 54 55 struct rtw_h2c_pkt { 56 _os_list list; 57 u8 *vir_head; /* should not reset */ 58 u8 *vir_data; 59 u8 *vir_end; 60 u8 *vir_tail; 61 void *os_rsvd[1]; 62 u8 type; 63 u32 id; /* h2c id */ 64 u32 buf_len; 65 u32 data_len; 66 67 u32 phy_addr_l; 68 u32 phy_addr_h; 69 u8 cache; 70 u16 host_idx; 71 u8 h2c_seq; /* h2c seq */ 72 }; 73 74 /** 75 * the category of phl ring 76 */ 77 enum rtw_phl_ring_cat { 78 RTW_PHL_RING_CAT_TID0 = 0, 79 RTW_PHL_RING_CAT_TID1 = 1, 80 RTW_PHL_RING_CAT_TID2 = 2, 81 RTW_PHL_RING_CAT_TID3 = 3, 82 RTW_PHL_RING_CAT_TID4 = 4, 83 RTW_PHL_RING_CAT_TID5 = 5, 84 RTW_PHL_RING_CAT_TID6 = 6, 85 RTW_PHL_RING_CAT_TID7 = 7, 86 RTW_PHL_RING_CAT_MGNT = 8, 87 RTW_PHL_RING_CAT_HIQ = 9, 88 RTW_PHL_RING_CAT_MAX = 0xff 89 }; 90 91 92 /** 93 * @RTW_PHL_TREQ_TYPE_PHL_UPDATE_TXSC: 94 * this is for phl tx shortcut entry to update 95 * @RTW_PHL_TREQ_TYPE_CORE_TXSC: 96 * it means this txreq is a shortcut pkt, so it need a txsc recycle 97 * @RTW_PHL_TREQ_TYPE_PHL_ADD_TXSC: 98 * it means this txreq is a new cache in core layer and also need cache 99 * in phl layer 100 */ 101 102 enum rtw_treq_type { 103 #if defined(CONFIG_CORE_TXSC) || defined(CONFIG_PHL_TXSC) 104 RTW_PHL_TREQ_TYPE_PHL_UPDATE_TXSC = 0x80, 105 #endif 106 RTW_PHL_TREQ_TYPE_NORMAL = 0, 107 RTW_PHL_TREQ_TYPE_TEST_PATTERN = 1, 108 #if defined(CONFIG_CORE_TXSC) || defined(CONFIG_PHL_TXSC) 109 RTW_PHL_TREQ_TYPE_CORE_TXSC = 2, 110 RTW_PHL_TREQ_TYPE_PHL_ADD_TXSC = 3, 111 #endif 112 RTW_PHL_TREQ_TYPE_MAX = 0xFF 113 }; 114 115 116 enum rtw_packet_type { 117 RTW_PHL_PKT_TYPE_DATA = 0, 118 RTW_PHL_PKT_TYPE_MGNT = 1, 119 RTW_PHL_PKT_TYPE_H2C = 2, 120 RTW_PHL_PKT_TYPE_CTRL = 3, 121 RTW_PHL_PKT_TYPE_FWDL = 4, 122 RTW_PHL_PKT_TYPE_MAX = 0xFF 123 }; 124 125 126 /** 127 * struct rtw_t_mdata_non_dcpu: 128 * this settings are only used in non-dcpu mode. 129 */ 130 struct rtw_t_mdata_non_dcpu { 131 u8 tbd; 132 }; 133 134 /** 135 * struct rtw_t_mdata_dcpu: 136 * this settings are only used in dcpu mode. 137 */ 138 struct rtw_t_mdata_dcpu { 139 u8 tbd; 140 }; 141 142 /** 143 * tx packet descrption 144 * 145 * @u: the union separates dpcu mode and non-dpcu mode unique settings 146 * @mac_priv: the mac private struture only used by HV tool. 147 * normal driver won't allocate memory for this pointer. 148 */ 149 struct rtw_t_meta_data { 150 /* basic */ 151 u8 *ta; 152 u8 *ra; 153 u8 da[6]; 154 u8 sa[6]; 155 u8 to_ds; 156 u8 from_ds; 157 u8 band; /*0 or 1*/ 158 u8 wmm; /*0 or 1*/ 159 enum rtw_packet_type type; 160 u8 tid; 161 u8 bc; 162 u8 mc; 163 u16 pktlen; /* MAC header length + frame body length */ 164 165 u16 macid; 166 u8 hal_port; 167 168 /* sequence */ 169 u8 hw_seq_mode; 170 u8 hw_ssn_sel; 171 u16 sw_seq; 172 173 /* hdr conversion & hw amsdu */ 174 u8 smh_en; 175 u8 hw_amsdu; 176 u8 hdr_len; 177 u8 wp_offset; 178 u8 shcut_camid; 179 u8 upd_wlan_hdr; 180 u8 reuse_start_num; 181 u8 reuse_size; 182 183 /* sec */ 184 u8 hw_sec_iv; 185 u8 sw_sec_iv; 186 u8 sec_keyid; 187 u8 sec_cam_idx; 188 u8 sec_hw_enc; 189 u8 sec_type; 190 u8 force_key_en; 191 u8 iv[6]; 192 193 /* dma */ 194 u8 dma_ch; 195 u8 wd_page_size; 196 u8 wdinfo_en; 197 u8 addr_info_num; 198 u8 usb_pkt_ofst; 199 u8 usb_txagg_num; 200 201 /* ampdu */ 202 u8 ampdu_en; 203 u8 max_agg_num; 204 u8 bk; 205 u8 ampdu_density; 206 207 /* rate */ 208 u8 data_bw_er; 209 u8 f_ldpc; 210 u8 f_stbc; 211 u8 f_dcm; 212 u8 f_er; 213 u16 f_rate; 214 u8 f_gi_ltf; 215 u8 f_bw; 216 u8 userate_sel; 217 218 /* a ctrl */ 219 u8 a_ctrl_bqr; 220 u8 a_ctrl_uph; 221 u8 a_ctrl_bsr; 222 u8 a_ctrl_cas; 223 224 /* tx cnt & rty rate */ 225 u8 dis_rts_rate_fb; 226 u8 dis_data_rate_fb; 227 u16 data_rty_lowest_rate; 228 u8 data_tx_cnt_lmt; 229 u8 data_tx_cnt_lmt_en; 230 231 /* protection */ 232 u8 rts_en; 233 u8 cts2self; 234 u8 rts_cca_mode; 235 u8 hw_rts_en; 236 237 /* misc */ 238 u8 mbssid; 239 u8 nav_use_hdr; 240 u8 ack_ch_info; 241 u8 life_time_sel; 242 u8 no_ack; 243 u8 ndpa; 244 u8 snd_pkt_sel; 245 u8 sifs_tx; 246 u8 rtt_en; 247 u8 spe_rpt; 248 u8 raw; 249 u8 sw_define; 250 251 union { 252 struct rtw_t_mdata_non_dcpu non_dcpu; 253 struct rtw_t_mdata_dcpu dcpu; 254 } u; 255 256 void *mac_priv; 257 }; 258 259 260 /** 261 * packet recv information 262 */ 263 struct rtw_r_meta_data { 264 u8 dma_ch; 265 u8 hal_port; 266 u8 ta[6]; /* Transmitter Address */ 267 u8 ppdu_cnt_chg; 268 #ifdef CONFIG_PHL_CSUM_OFFLOAD_RX 269 u8 chksum_status; /*return mac_chk_rx_tcpip_chksum_ofd,0 is ok ,1 is fail*/ 270 #endif 271 272 u16 pktlen; /* DW0 [0:13] */ 273 u8 shift; /* DW0 [14:15] */ 274 u8 wl_hd_iv_len; /* DW0 [16:21] */ 275 u8 bb_sel; /* DW0 [22:22] */ 276 u8 mac_info_vld; /* DW0 [23:23] */ 277 u8 rpkt_type; /* DW0 [24:27] */ 278 u8 drv_info_size; /* DW0 [28:30] */ 279 u8 long_rxd; /* DW0 [31:31] */ 280 281 u8 ppdu_type; /* DW1 [0:3] */ 282 u8 ppdu_cnt; /* DW1 [4:6] */ 283 u8 sr_en; /* DW1 [7:7] */ 284 u8 user_id; /* DW1 [8:15] */ 285 u16 rx_rate; /* DW1 [16:24] */ 286 u8 rx_gi_ltf; /* DW1 [25:27] */ 287 u8 non_srg_ppdu; /* DW1 [28:28] */ 288 u8 inter_ppdu; /* DW1 [29:29] */ 289 u8 bw; /* DW1 [30:31] */ 290 291 u32 freerun_cnt; /* DW2 [0:31] */ 292 293 u8 a1_match; /* DW3 [0:0] */ 294 u8 sw_dec; /* DW3 [1:1] */ 295 u8 hw_dec; /* DW3 [2:2] */ 296 u8 ampdu; /* DW3 [3:3] */ 297 u8 ampdu_end_pkt; /* DW3 [4:4] */ 298 u8 amsdu; /* DW3 [5:5] */ 299 u8 amsdu_cut; /* DW3 [6:6] */ 300 u8 last_msdu; /* DW3 [7:7] */ 301 u8 bypass; /* DW3 [8:8] */ 302 u8 crc32; /* DW3 [9:9] */ 303 u8 icverr; /* DW3 [10:10] */ 304 u8 magic_wake; /* DW3 [11:11] */ 305 u8 unicast_wake; /* DW3 [12:12] */ 306 u8 pattern_wake; /* DW3 [13:13] */ 307 u8 get_ch_info; /* DW3 [14:15] */ 308 u8 pattern_idx; /* DW3 [16:20] */ 309 u8 target_idc; /* DW3 [21:23] */ 310 u8 chksum_ofld_en; /* DW3 [24:24] */ 311 u8 with_llc; /* DW3 [25:25] */ 312 u8 rx_statistics; /* DW3 [26:26] */ 313 314 u8 frame_type; /* DW4 [0:1] */ 315 u8 mc; /* DW4 [2:2] */ 316 u8 bc; /* DW4 [3:3] */ 317 u8 more_data; /* DW4 [4:4] */ 318 u8 more_frag; /* DW4 [5:5] */ 319 u8 pwr_bit; /* DW4 [6:6] */ 320 u8 qos; /* DW4 [7:7] */ 321 u8 tid; /* DW4 [8:11] */ 322 u8 eosp; /* DW4 [12:12] */ 323 u8 htc; /* DW4 [13:13] */ 324 u8 q_null; /* DW4 [14:14] */ 325 u16 seq; /* DW4 [16:27] */ 326 u8 frag_num; /* DW4 [28:31] */ 327 328 u8 sec_cam_idx; /* DW5 [0:7] */ 329 u8 addr_cam; /* DW5 [8:15] */ 330 u16 macid; /* DW5 [16:23] */ 331 u8 rx_pl_id; /* DW5 [24:27] */ 332 u8 addr_cam_vld; /* DW5 [28:28] */ 333 u8 addr_fwd_en; /* DW5 [29:29] */ 334 u8 rx_pl_match; /* DW5 [30:30] */ 335 336 u8 mac_addr[6]; /* DW6 [0:31] DW7 [0:15] */ 337 u8 smart_ant; /* DW7 [16:16] */ 338 u8 sec_type; /* DW7 [17:20] */ 339 }; 340 341 342 /** 343 * rtw_pkt_buf_list -- store pakcet from upper layer(ex. ndis, kernel, ethernet..) 344 * @vir_addr: virtual address of this packet 345 * @phy_addr_l: lower 32-bit physical address of this packet 346 * @phy_addr_h: higher 32-bit physical address of this packet 347 * @length: length of this packet 348 * @type: tbd 349 */ 350 struct rtw_pkt_buf_list { 351 u8 *vir_addr; 352 u32 phy_addr_l; 353 u32 phy_addr_h; 354 u16 length; 355 }; 356 357 enum rtw_tx_status { 358 TX_STATUS_TX_DONE, 359 TX_STATUS_TX_FAIL_REACH_RTY_LMT, 360 TX_STATUS_TX_FAIL_LIFETIME_DROP, 361 TX_STATUS_TX_FAIL_MACID_DROP, 362 TX_STATUS_TX_FAIL_SW_DROP, 363 TX_STATUS_TX_FAIL_MAX 364 }; 365 366 #ifdef CONFIG_PHL_TX_DBG 367 typedef 368 void 369 (*CORE_TX_HANDLE_CALLBACK) 370 ( 371 void *drv_priv, 372 void *pctx, 373 bool btx_ok 374 ); 375 376 /** 377 * @en_dbg: if en_dbg = true, phl tx will print tx dbg info for this dbg pkt. set the flag from core layer. 378 * @tx_dbg_pkt_type: Identification type, define by core layer 379 * @core_add_tx_t: core layer add tx req to phl time 380 * @enq_pending_wd_t: phl tx enqueue pending wd page time 381 * @recycle_wd_t: phl tx handle the wp report and recycle wd time 382 */ 383 struct rtw_tx_dbg { 384 bool en_dbg; 385 u16 tx_dbg_pkt_type; 386 u32 core_add_tx_t; 387 u32 enq_pending_wd_t; 388 u32 recycle_wd_t; 389 CORE_TX_HANDLE_CALLBACK statecb; 390 void *pctx; 391 }; 392 #endif /* CONFIG_PHL_TX_DBG */ 393 394 /** 395 * context for tx feedback handler 396 * @drvpriv: driver private 397 * @ctx: private context 398 * @id: module id of this tx packet 399 * @txsts: detail tx status 400 * @txfb_cb: tx feedback handler, currently assign by core layer 401 */ 402 struct rtw_txfb_t { 403 void *drvpriv; 404 void *ctx; 405 enum phl_module_id id; 406 enum rtw_tx_status txsts; 407 void (*txfb_cb)(struct rtw_txfb_t *txfb); 408 }; 409 410 411 /** 412 * the xmit request from core layer, store in xmit phl ring 413 * @list: list 414 * @os_priv: the private context from core layer 415 * @mdata: see structure rtw_t_meta_data 416 * @tx_time: xmit requset tx time, unit in ms 417 * @shortcut_id: short cut id this packet will use in phl/hal 418 * @total_len: the total length of pkt_list 419 * @pkt_cnt: the packet number of pkt_list 420 * @pkt_list: see structure rtw_pkt_buf_list 421 * @txfb: tx feedback context 422 * 423 * Note, this structure are visible to core, phl and hal layer 424 */ 425 struct rtw_xmit_req { 426 _os_list list; 427 void *os_priv; 428 enum rtw_treq_type treq_type; 429 struct rtw_t_meta_data mdata; 430 u32 tx_time; 431 u8 shortcut_id; 432 u32 total_len; 433 u8 pkt_cnt; 434 u8 *pkt_list; 435 struct rtw_txfb_t *txfb; 436 #ifdef CONFIG_PHL_TX_DBG 437 struct rtw_tx_dbg tx_dbg; 438 #endif /* CONFIG_PHL_TX_DBG */ 439 }; 440 441 /** 442 * the recv packet to core layer, store in recv phl ring 443 * @os_priv: the private context from core layer 444 * @mdata: see structure rtw_r_meta_data 445 * @shortcut_id: short cut id this packet will use in phl/hal 446 * @pkt_cnt: the packet counts of pkt_list 447 * @rx_role: the role to which the RX packet is targeted 448 * @tx_sta: the phl sta that sends this packet 449 * @pkt_list: see structure rtw_pkt_buf_list 450 * 451 * Note, this structure are visible to core, phl and hal layer 452 */ 453 struct rtw_recv_pkt { 454 void *os_priv; 455 struct rtw_r_meta_data mdata; 456 u8 shortcut_id; 457 u8 pkt_cnt; 458 u16 os_netbuf_len; 459 struct rtw_wifi_role_t *rx_role; 460 struct rtw_phl_stainfo_t *tx_sta; 461 struct rtw_pkt_buf_list pkt_list[MAX_RX_BUF_SEG_NUM]; 462 struct rtw_phl_ppdu_phy_info phy_info; 463 }; 464 465 466 /** 467 * the phl ring which stores XMIT requests can be access by both 468 * core and phl, and all the requests in this ring have the same TID value 469 * @tid: the TID value of this phl ring 470 * @dma_ch: dma channel of this phl ring, query by rtw_hal_tx_chnl_mapping() 471 * @tx_thres: tx threshold of this phl ring for batch handling tx requests 472 * @core_idx: record the index of latest entry accessed by core layer 473 * @phl_idx: record the index of handling done by phl layer 474 * @phl_next_idx: record the index of latest entry accessed by phl layer 475 * @entry: store the pointer of requests assigned to this phl ring 476 */ 477 struct rtw_phl_tx_ring { 478 u8 tid; 479 u8 dma_ch; 480 u16 tx_thres; 481 u16 core_idx; 482 _os_atomic phl_idx; 483 _os_atomic phl_next_idx; 484 u8 *entry[MAX_PHL_TX_RING_ENTRY_NUM];/* change to dynamic allocation */ 485 }; 486 487 /** 488 * this structure stores sorted tx rings having frames to tx to the same sta 489 * it will change everytime _phl_check_tring_list() executed 490 * @list: link to the next sta which has frames to transmit 491 * @sleep: true if this macid is under power-saving mode 492 * @has_mgnt: true if this macid has management frames to transmit 493 * @has_hiq: true if this macid has hiq frames to transmit 494 * @sorted_ring: pre-sorted phl ring status list of this macid 495 */ 496 struct phl_tx_plan { 497 _os_list list; 498 bool sleep; 499 bool has_mgnt; 500 bool has_hiq; 501 _os_list sorted_ring; 502 }; 503 504 /** 505 * this phl ring list contains a list of phl TX rings that have the same macid 506 * and different tid, and it can be access by both core and phl 507 * @list: link to next phl ring list with other macid 508 * @macid: the MACID value of this phl ring list 509 * @band: band of this phl ring list, band idx 0~1 510 * @wmm: wmm of this phl ring list, wmm idx 0~1 511 * @port: port of this phl ring list, port idx 0~4 512 * @mbssid: TODO 513 * @phl_ring: the phl rings with same macid but different tid, see rtw_phl_tx_ring 514 * @tx_plan: transmission plan for this macid, decide by _phl_check_tring_list() 515 */ 516 struct rtw_phl_tring_list { 517 _os_list list; 518 u16 macid; 519 u8 band;/*0 or 1*/ 520 u8 wmm;/*0 or 1*/ 521 u8 port; 522 /*u8 mbssid*/ 523 struct rtw_phl_tx_ring phl_ring[MAX_PHL_RING_CAT_NUM];/* tid 0~7, 8:mgnt, 9:hiq */ 524 struct phl_tx_plan tx_plan; 525 }; 526 527 /** 528 * this phl RX ring can be access by both core and phl 529 * @core_idx: record the index of latest entry accessed by core layer 530 * @phl_idx: record the index of handling done by phl layer 531 * @entry: store the pointer of requests assigned to this phl ring 532 */ 533 struct rtw_phl_rx_ring { 534 _os_atomic core_idx; 535 _os_atomic phl_idx; 536 struct rtw_recv_pkt *entry[MAX_PHL_RX_RING_ENTRY_NUM];/* change to dynamic allocation */ 537 }; 538 539 540 /** 541 * the physical address list 542 */ 543 struct rtw_phy_addr_list { 544 _os_list list; 545 u32 phy_addr_l; 546 u32 phy_addr_h; 547 }; 548 549 /** 550 * the phl pkt tx request from phl layer to hal layer 551 * @wd_page: the buffer of wd page allocated by phl and filled by hal 552 * @wd_len: the phl tx shortcut cached wd_page length, if wd_len = 0 means no phl txsc 553 * @wp_seq: pcie only, wp sequence of this phl packet request 554 * @tx_req: see struct rtw_xmit_req 555 * 556 * Note, this structure should be visible to phl and hal layer (hana_todo) 557 */ 558 struct rtw_phl_pkt_req { 559 u8 *wd_page; 560 u8 wd_len; 561 u16 wp_seq; 562 struct rtw_xmit_req *tx_req; 563 }; 564 565 /* 566 0000: WIFI packet 567 0001: PPDU status 568 0010: channel info 569 0011: BB scope mode 570 0100: F2P TX CMD report 571 0101: SS2FW report 572 0110: TX report 573 0111: TX payload release to host 574 1000: DFS report 575 1001: TX payload release to WLCPU 576 1010: C2H packet */ 577 enum rtw_rx_type { 578 RTW_RX_TYPE_WIFI = 0, 579 RTW_RX_TYPE_PPDU_STATUS = 1, 580 RTW_RX_TYPE_CHANNEL_INFO = 2, 581 RTW_RX_TYPE_TX_RPT = 3, 582 RTW_RX_TYPE_TX_WP_RELEASE_HOST = 4, 583 RTW_RX_TYPE_DFS_RPT = 5, 584 RTW_RX_TYPE_C2H = 6, 585 RTW_RX_TYPE_MAX = 0xFF 586 }; 587 588 struct rtw_phl_rx_pkt { 589 _os_list list; 590 enum rtw_rx_type type; 591 u8 *rxbuf_ptr; 592 struct rtw_recv_pkt r; 593 }; 594 595 596 struct rtw_xmit_recycle { 597 u16 wp_seq; 598 struct rtw_xmit_req *tx_req; 599 }; 600 601 enum rtw_traffic_dir { 602 TRAFFIC_UL = 0, /* Uplink */ 603 TRAFFIC_DL, /* Downlink */ 604 TRAFFIC_BALANCE, 605 TRAFFIC_MAX 606 }; 607 608 enum rtw_rx_fltr_mode { 609 RX_FLTR_MODE_SNIFFER, /* 0 */ 610 RX_FLTR_MODE_SCAN, 611 RX_FLTR_MODE_STA_LINKING, 612 RX_FLTR_MODE_STA_NORMAL, 613 RX_FLTR_MODE_AP_NORMAL, 614 RX_FLTR_MODE_RESTORE = 0xFF 615 }; 616 617 #endif /* __PHL_TRX_DEF_H_ */ 618