1 /******************************************************************************
2 *
3 * Copyright(c) 2019 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #define _PHL_CMD_DISPR_CONTROLLER_C_
16 #include "phl_headers.h"
17
18 #ifdef CONFIG_CMD_DISP
19
20 struct cmd_controller {
21 struct phl_info_t *phl_info;
22 u32 mon_mdl_id; /* monitor module id */
23 bool mon_mdl;
24 };
25
26
27 /* Each dispr has a controller.
28 * A dispr controller is designed for phl instance to interact with dispr modules that are belonged to a specific hw band,
29 * phl instance can perform follwing actions via dedicated controller:
30 * 1. allow (phl status/non-dispr phl modules) to monitor & drop msg
31 * 2. allow dispr modules, that are belonged to same dispr, to sequentially communicate with phl instance & call phl api,
32 * and also allow (phl status/non-dispr phl modules) to notify dispr by hw band.
33 * *Note*
34 * 1. when cmd dispatch engine is in solo thread mode (each dispr has its own dedicated thread).
35 * phl instance might receive msg from different dispr simutaneously and
36 * currently using semaphore (dispr_ctrl_sema) to prevent multi-thread condition.
37 * 2. when cmd dispatch engine is in share thread mode, msg from different dispr would pass to controller sequentially.
38
39 * PS:
40 * phl instance: means phl_info_t, which include phl mgnt status & non-dispr phl modules
41 * dispr modules: all existing background & foreground modules.
42 * non-dispr phl module : Data path (TX/Rx), etc
43 * phl mgnt status : stop/surprise remove/cannot io
44 */
45
46 enum phl_mdl_ret_code
_dispr_resume_io_ctrl(struct phl_info_t * phl_info,struct phl_msg * msg)47 _dispr_resume_io_ctrl(struct phl_info_t *phl_info,
48 struct phl_msg *msg)
49 {
50 enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
51 enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
52 struct phl_data_ctl_t ctl = {0};
53
54 do {
55 ctl.cmd = PHL_DATA_CTL_SW_TX_RESUME;
56 ctl.id = MSG_MDL_ID_FIELD(msg->msg_id);
57 sts = phl_data_ctrler(phl_info, &ctl, msg);
58 if (RTW_PHL_STATUS_SUCCESS != sts) {
59 PHL_TRACE(COMP_PHL_XMIT, _PHL_WARNING_,
60 "[DATA_CTRL] SW Tx paused by module(0x%x) resume fail by module(%d) with event(%d)\n",
61 phl_info->pause_tx_id, ctl.id,
62 MSG_EVT_ID_FIELD(msg->msg_id));
63 ret = MDL_RET_FAIL;
64 break;
65 }
66
67 ctl.cmd = PHL_DATA_CTL_SW_RX_RESUME;
68 ctl.id = MSG_MDL_ID_FIELD(msg->msg_id);
69 sts = phl_data_ctrler(phl_info, &ctl, msg);
70 if (RTW_PHL_STATUS_SUCCESS != sts) {
71 PHL_TRACE(COMP_PHL_RECV, _PHL_WARNING_,
72 "[DATA_CTRL] SW Rx paused by module(0x%x) resume fail by module(%d) with event(%d)\n",
73 phl_info->pause_rx_id, ctl.id,
74 MSG_EVT_ID_FIELD(msg->msg_id));
75 ret = MDL_RET_FAIL;
76 break;
77 }
78
79 ret = MDL_RET_SUCCESS;
80 } while (false);
81
82 return ret;
83 }
84
85
86 enum phl_mdl_ret_code
_dispr_cannot_io_ctrl(struct phl_info_t * phl_info,struct phl_msg * msg)87 _dispr_cannot_io_ctrl(struct phl_info_t *phl_info,
88 struct phl_msg *msg)
89 {
90 enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
91 enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
92 struct phl_data_ctl_t ctl = {0};
93
94 ctl.cmd = PHL_DATA_CTL_TRX_SW_PAUSE;
95 ctl.id = MSG_MDL_ID_FIELD(msg->msg_id);
96 sts = phl_data_ctrler(phl_info, &ctl, msg);
97 if (RTW_PHL_STATUS_SUCCESS != sts) {
98 PHL_TRACE(COMP_PHL_XMIT, _PHL_WARNING_,
99 "[DATA_CTRL] SW T/Rx pause fail by module(%d) with event(%d)\n",
100 ctl.id, MSG_EVT_ID_FIELD(msg->msg_id));
101 ret = MDL_RET_FAIL;
102 } else {
103 ret = MDL_RET_SUCCESS;
104 }
105
106 return ret;
107 }
108
109 enum phl_mdl_ret_code
_dispr_hw_trx_rst_resume_ctrl(struct phl_info_t * phl_info,struct phl_msg * msg)110 _dispr_hw_trx_rst_resume_ctrl(struct phl_info_t *phl_info,
111 struct phl_msg *msg)
112 {
113 enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
114 enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
115 struct phl_data_ctl_t ctl = {0};
116
117 ctl.cmd = PHL_DATA_CTL_HW_TRX_RST_RESUME;
118 ctl.id = MSG_MDL_ID_FIELD(msg->msg_id);
119 sts = phl_data_ctrler(phl_info, &ctl, msg);
120 if (RTW_PHL_STATUS_SUCCESS != sts) {
121 PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
122 "[DATA_CTRL] HW T/Rx reset and resume fail by module(%d) with event(%d)\n",
123 ctl.id, MSG_EVT_ID_FIELD(msg->msg_id));
124 ret = MDL_RET_FAIL;
125 } else {
126 ret = MDL_RET_SUCCESS;
127 }
128
129 return ret;
130 }
131
132 enum phl_mdl_ret_code
_dispr_hw_trx_pause_ctrl(struct phl_info_t * phl_info,struct phl_msg * msg)133 _dispr_hw_trx_pause_ctrl(struct phl_info_t *phl_info,
134 struct phl_msg *msg)
135 {
136 enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
137 enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
138 struct phl_data_ctl_t ctl = {0};
139
140 ctl.cmd = PHL_DATA_CTL_HW_TRX_PAUSE;
141 ctl.id = MSG_MDL_ID_FIELD(msg->msg_id);
142 sts = phl_data_ctrler(phl_info, &ctl, msg);
143 if (RTW_PHL_STATUS_SUCCESS != sts) {
144 PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
145 "[DATA_CTRL] HW T/Rx pause fail by module(%d) with event(%d)\n",
146 ctl.id, MSG_EVT_ID_FIELD(msg->msg_id));
147 ret = MDL_RET_FAIL;
148 } else {
149 ret = MDL_RET_SUCCESS;
150 }
151
152 return ret;
153 }
154
155 enum phl_mdl_ret_code
_dispr_sw_tx_resume_ctrl(struct phl_info_t * phl_info,struct phl_msg * msg)156 _dispr_sw_tx_resume_ctrl(struct phl_info_t *phl_info,
157 struct phl_msg *msg)
158 {
159 enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
160 enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
161 struct phl_data_ctl_t ctl = {0};
162 enum phl_module_id mdl_id = MSG_MDL_ID_FIELD(msg->msg_id);
163
164 /* tx pause by MDL_POWER_MGNT, tx resume by MDL_TX/MDL_RX */
165 if (mdl_id == PHL_MDL_TX || mdl_id == PHL_MDL_RX)
166 ctl.id = PHL_MDL_POWER_MGNT;
167 else
168 ctl.id = mdl_id;
169 ctl.cmd = PHL_DATA_CTL_SW_TX_RESUME;
170
171 sts = phl_data_ctrler(phl_info, &ctl, msg);
172 if (RTW_PHL_STATUS_SUCCESS != sts) {
173 PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
174 "[DATA_CTRL] SW Tx paused by module(0x%x) resume fail by module(%d) with event(%d)\n",
175 phl_info->pause_tx_id, ctl.id,
176 MSG_EVT_ID_FIELD(msg->msg_id));
177 ret = MDL_RET_FAIL;
178 } else {
179 ret = MDL_RET_SUCCESS;
180 }
181
182 return ret;
183 }
184
185 enum phl_mdl_ret_code
_dispr_sw_rx_resume_ctrl(struct phl_info_t * phl_info,struct phl_msg * msg)186 _dispr_sw_rx_resume_ctrl(struct phl_info_t *phl_info,
187 struct phl_msg *msg)
188 {
189 enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
190 enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
191 struct phl_data_ctl_t ctl = {0};
192 enum phl_module_id mdl_id = MSG_MDL_ID_FIELD(msg->msg_id);
193
194 /* rx pause by MDL_POWER_MGNT, rx resume by MDL_TX/MDL_RX */
195 if (mdl_id == PHL_MDL_TX || mdl_id == PHL_MDL_RX)
196 ctl.id = PHL_MDL_POWER_MGNT;
197 else
198 ctl.id = mdl_id;
199 ctl.cmd = PHL_DATA_CTL_SW_RX_RESUME;
200
201 sts = phl_data_ctrler(phl_info, &ctl, msg);
202 if (RTW_PHL_STATUS_SUCCESS != sts) {
203 PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
204 "[DATA_CTRL] SW Rx paused by module(0x%x) resume fail by module(%d) with event(%d)\n",
205 phl_info->pause_rx_id, ctl.id,
206 MSG_EVT_ID_FIELD(msg->msg_id));
207 ret = MDL_RET_FAIL;
208 } else {
209 ret = MDL_RET_SUCCESS;
210 }
211
212 return ret;
213 }
214
215 enum phl_mdl_ret_code
_dispr_sw_tx_pause_ctrl(struct phl_info_t * phl_info,struct phl_msg * msg)216 _dispr_sw_tx_pause_ctrl(struct phl_info_t *phl_info,
217 struct phl_msg *msg)
218 {
219 enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
220 enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
221 struct phl_data_ctl_t ctl = {0};
222
223 ctl.cmd = PHL_DATA_CTL_SW_TX_PAUSE;
224 ctl.id = MSG_MDL_ID_FIELD(msg->msg_id);
225 sts = phl_data_ctrler(phl_info, &ctl, msg);
226 if (RTW_PHL_STATUS_SUCCESS != sts) {
227 PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
228 "[DATA_CTRL] SW Tx pause fail by module(%d) with event(%d)\n",
229 ctl.id, MSG_EVT_ID_FIELD(msg->msg_id));
230 ret = MDL_RET_FAIL;
231 } else {
232 ret = MDL_RET_SUCCESS;
233 }
234
235 return ret;
236 }
237
238 enum phl_mdl_ret_code
_dispr_sw_rx_pause_ctrl(struct phl_info_t * phl_info,struct phl_msg * msg)239 _dispr_sw_rx_pause_ctrl(struct phl_info_t *phl_info,
240 struct phl_msg *msg)
241 {
242 enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
243 enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
244 struct phl_data_ctl_t ctl = {0};
245
246 ctl.cmd = PHL_DATA_CTL_SW_RX_PAUSE;
247 ctl.id = MSG_MDL_ID_FIELD(msg->msg_id);
248 sts = phl_data_ctrler(phl_info, &ctl, msg);
249 if (RTW_PHL_STATUS_SUCCESS != sts) {
250 PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
251 "[DATA_CTRL] SW Rx pause fail by module(%d) with event(%d)\n",
252 ctl.id, MSG_EVT_ID_FIELD(msg->msg_id));
253 ret = MDL_RET_FAIL;
254 } else {
255 ret = MDL_RET_SUCCESS;
256 }
257
258 return ret;
259 }
260
261 enum phl_mdl_ret_code
_dispr_sw_tx_reset_ctrl(struct phl_info_t * phl_info,struct phl_msg * msg)262 _dispr_sw_tx_reset_ctrl(struct phl_info_t *phl_info,
263 struct phl_msg *msg)
264 {
265 enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
266 enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
267 struct phl_data_ctl_t ctl = {0};
268
269 ctl.cmd = PHL_DATA_CTL_SW_TX_RESET;
270 ctl.id = MSG_MDL_ID_FIELD(msg->msg_id);
271 sts = phl_data_ctrler(phl_info, &ctl, msg);
272 if (RTW_PHL_STATUS_SUCCESS != sts) {
273 PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
274 "[DATA_CTRL] SW Tx reset fail by module(%d) with event(%d)\n",
275 ctl.id, MSG_EVT_ID_FIELD(msg->msg_id));
276 ret = MDL_RET_FAIL;
277 } else {
278 ret = MDL_RET_SUCCESS;
279 }
280
281 return ret;
282 }
283
284 enum phl_mdl_ret_code
_dispr_sw_rx_reset_ctrl(struct phl_info_t * phl_info,struct phl_msg * msg)285 _dispr_sw_rx_reset_ctrl(struct phl_info_t *phl_info,
286 struct phl_msg *msg)
287 {
288 enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
289 enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
290 struct phl_data_ctl_t ctl = {0};
291
292 ctl.cmd = PHL_DATA_CTL_SW_RX_RESET;
293 ctl.id = MSG_MDL_ID_FIELD(msg->msg_id);
294 sts = phl_data_ctrler(phl_info, &ctl, msg);
295 if (RTW_PHL_STATUS_SUCCESS != sts) {
296 PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
297 "[DATA_CTRL] SW Rx reset fail by module(%d) with event(%d)\n",
298 ctl.id, MSG_EVT_ID_FIELD(msg->msg_id));
299 ret = MDL_RET_FAIL;
300 } else {
301 ret = MDL_RET_SUCCESS;
302 }
303
304 return ret;
305 }
306
307 enum phl_mdl_ret_code
_dispr_trx_sw_pause_ctrl(struct phl_info_t * phl_info,struct phl_msg * msg)308 _dispr_trx_sw_pause_ctrl(struct phl_info_t *phl_info,
309 struct phl_msg *msg)
310 {
311 enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
312 enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
313 struct phl_data_ctl_t ctl = {0};
314
315 ctl.cmd = PHL_DATA_CTL_TRX_SW_PAUSE;
316 ctl.id = MSG_MDL_ID_FIELD(msg->msg_id);
317 sts = phl_data_ctrler(phl_info, &ctl, msg);
318 if (RTW_PHL_STATUS_SUCCESS != sts) {
319 PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
320 "[DATA_CTRL] SW T/Rx pause fail by module(%d) with event(%d)\n",
321 ctl.id, MSG_EVT_ID_FIELD(msg->msg_id));
322 ret = MDL_RET_FAIL;
323 } else {
324 ret = MDL_RET_SUCCESS;
325 }
326
327 return ret;
328 }
329
330 enum phl_mdl_ret_code
_dispr_trx_sw_resume_ctrl(struct phl_info_t * phl_info,struct phl_msg * msg)331 _dispr_trx_sw_resume_ctrl(struct phl_info_t *phl_info,
332 struct phl_msg *msg)
333 {
334 enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
335 enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
336 struct phl_data_ctl_t ctl = {0};
337
338 ctl.cmd = PHL_DATA_CTL_TRX_SW_RESUME;
339 ctl.id = MSG_MDL_ID_FIELD(msg->msg_id);
340 sts = phl_data_ctrler(phl_info, &ctl, msg);
341 if (RTW_PHL_STATUS_SUCCESS != sts) {
342 PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
343 "[DATA_CTRL] SW T/Rx resume fail by module(%d) with event(%d)\n",
344 ctl.id, MSG_EVT_ID_FIELD(msg->msg_id));
345 ret = MDL_RET_FAIL;
346 } else {
347 ret = MDL_RET_SUCCESS;
348 }
349
350 return ret;
351 }
352
353 enum phl_mdl_ret_code
_dispr_trx_pause_w_rst_ctrl(struct phl_info_t * phl_info,struct phl_msg * msg)354 _dispr_trx_pause_w_rst_ctrl(struct phl_info_t *phl_info,
355 struct phl_msg *msg)
356 {
357 enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
358 enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
359 struct phl_data_ctl_t ctl = {0};
360
361 ctl.cmd = PHL_DATA_CTL_TRX_PAUSE_W_RST;
362 ctl.id = MSG_MDL_ID_FIELD(msg->msg_id);
363 sts = phl_data_ctrler(phl_info, &ctl, msg);
364 if (RTW_PHL_STATUS_SUCCESS != sts) {
365 PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
366 "[DATA_CTRL] SW T/Rx pause with reset fail by module(%d) with event(%d)\n",
367 ctl.id, MSG_EVT_ID_FIELD(msg->msg_id));
368 ret = MDL_RET_FAIL;
369 } else {
370 ret = MDL_RET_SUCCESS;
371 }
372
373 return ret;
374 }
375
376 enum phl_mdl_ret_code
_dispr_trx_resume_w_rst_ctrl(struct phl_info_t * phl_info,struct phl_msg * msg)377 _dispr_trx_resume_w_rst_ctrl(struct phl_info_t *phl_info,
378 struct phl_msg *msg)
379 {
380 enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
381 enum rtw_phl_status sts = RTW_PHL_STATUS_FAILURE;
382 struct phl_data_ctl_t ctl = {0};
383
384 ctl.cmd = PHL_DATA_CTL_TRX_RESUME_W_RST;
385 ctl.id = MSG_MDL_ID_FIELD(msg->msg_id);
386 sts = phl_data_ctrler(phl_info, &ctl, msg);
387 if (RTW_PHL_STATUS_SUCCESS != sts) {
388 PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
389 "[DATA_CTRL] SW T/Rx resume with reset fail by module(%d) with event(%d)\n",
390 ctl.id, MSG_EVT_ID_FIELD(msg->msg_id));
391 ret = MDL_RET_FAIL;
392 } else {
393 ret = MDL_RET_SUCCESS;
394 }
395
396 return ret;
397 }
398
399 enum phl_mdl_ret_code
_dispr_mdl_stop_ctrl(struct phl_info_t * phl_info,struct cmd_controller * cmd_ctrl)400 _dispr_mdl_stop_ctrl(struct phl_info_t *phl_info,
401 struct cmd_controller *cmd_ctrl)
402 {
403 if (cmd_ctrl->mon_mdl_id != 0) {
404 cmd_ctrl->mon_mdl = true;
405 return MDL_RET_PENDING;
406 } else {
407 return MDL_RET_SUCCESS;
408 }
409 }
410
411 enum phl_mdl_ret_code
_dispr_ctrl_init(void * phl,void * dispr,void ** priv)412 _dispr_ctrl_init(void *phl,
413 void *dispr,
414 void **priv)
415 {
416 struct phl_info_t *phl_info = (struct phl_info_t *)phl;
417 struct cmd_controller *cmd_ctrl = NULL;
418 void *drv = phl_to_drvpriv(phl_info);
419
420 PHL_INFO("%s(): \n", __func__);
421
422 (*priv) = NULL;
423 cmd_ctrl = (struct cmd_controller *)_os_mem_alloc(drv,
424 sizeof(struct cmd_controller));
425
426 if (cmd_ctrl == NULL) {
427 PHL_ERR(" %s, alloc fail\n",__FUNCTION__);
428 return MDL_RET_FAIL;
429 }
430
431 cmd_ctrl->phl_info = phl_info;
432 (*priv) = (void*)cmd_ctrl;
433 return MDL_RET_SUCCESS;
434 }
435
_dispr_ctrl_deinit(void * dispr,void * priv)436 void _dispr_ctrl_deinit(void *dispr, void *priv)
437 {
438 struct cmd_controller *cmd_ctrl = (struct cmd_controller *)priv;
439 void *drv = phl_to_drvpriv(cmd_ctrl->phl_info);
440
441 _os_mem_free(drv, cmd_ctrl, sizeof(struct cmd_controller));
442
443 PHL_INFO("%s(): \n", __func__);
444 }
445
_dispr_ctrl_start(void * dispr,void * priv)446 enum phl_mdl_ret_code _dispr_ctrl_start(void *dispr, void *priv)
447 {
448 enum phl_mdl_ret_code ret = MDL_RET_SUCCESS;
449 struct cmd_controller *cmd_ctrl = (struct cmd_controller *)priv;
450 struct phl_info_t *phl_info = (struct phl_info_t *)cmd_ctrl->phl_info;
451 void *drv = phl_to_drvpriv(cmd_ctrl->phl_info);
452
453 PHL_INFO("%s(): \n", __func__);
454
455 _os_mem_set(drv, cmd_ctrl, 0, sizeof(struct cmd_controller));
456 cmd_ctrl->phl_info = phl_info;
457
458 return ret;
459 }
460
_dispr_ctrl_stop(void * dispr,void * priv)461 enum phl_mdl_ret_code _dispr_ctrl_stop(void *dispr, void *priv)
462 {
463 enum phl_mdl_ret_code ret = MDL_RET_SUCCESS;
464
465 PHL_INFO("%s(): \n", __func__);
466
467 return ret;
468 }
469
_fail_hdlr(void * dispr,struct phl_info_t * phl_info,struct phl_msg * msg)470 static void _fail_hdlr(void *dispr, struct phl_info_t *phl_info, struct phl_msg *msg)
471 {
472
473 }
474
475 static enum phl_mdl_ret_code
_ctrler_msg_hdlr(struct phl_info_t * phl_info,struct phl_msg * msg)476 _ctrler_msg_hdlr(struct phl_info_t *phl_info, struct phl_msg *msg)
477 {
478 enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
479
480 switch (MSG_EVT_ID_FIELD(msg->msg_id)) {
481 case MSG_EVT_DEV_RESUME_IO:
482 ret = _dispr_resume_io_ctrl(phl_info, msg);
483 break;
484 case MSG_EVT_DEV_CANNOT_IO:
485 ret = _dispr_cannot_io_ctrl(phl_info, msg);
486 break;
487 default:
488 break;
489 }
490
491 return ret;
492 }
493
494 static enum phl_mdl_ret_code
_tx_msg_hdlr(struct phl_info_t * phl_info,struct phl_msg * msg)495 _tx_msg_hdlr(struct phl_info_t *phl_info, struct phl_msg *msg)
496 {
497 enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
498
499 switch (MSG_EVT_ID_FIELD(msg->msg_id)) {
500 case MSG_EVT_TRX_PWR_REQ:
501 /* ps module handle MSG_EVT_TRX_PWR_REQ itself */
502 default:
503 break;
504 }
505
506 return ret;
507 }
508
509 static enum phl_mdl_ret_code
_rx_msg_hdlr(struct phl_info_t * phl_info,struct phl_msg * msg)510 _rx_msg_hdlr(struct phl_info_t *phl_info, struct phl_msg *msg)
511 {
512 enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
513
514 switch (MSG_EVT_ID_FIELD(msg->msg_id)) {
515 case MSG_EVT_TRX_PWR_REQ:
516 /* ps module handle MSG_EVT_TRX_PWR_REQ itself */
517 default:
518 break;
519 }
520
521 return ret;
522 }
523
_mon_msg_hdlr(struct cmd_controller * cmd_ctrl,struct phl_msg * msg)524 static void _mon_msg_hdlr(struct cmd_controller *cmd_ctrl,
525 struct phl_msg *msg)
526 {
527 switch (MSG_EVT_ID_FIELD(msg->msg_id)) {
528 case MSG_EVT_SER_L0_RESET:
529 case MSG_EVT_SER_M1_PAUSE_TRX:
530 case MSG_EVT_SER_M3_DO_RECOV:
531 cmd_ctrl->mon_mdl_id = PHL_MDL_SER;
532 break;
533 case MSG_EVT_SER_M5_READY:
534 cmd_ctrl->mon_mdl_id = 0;
535 if (cmd_ctrl->mon_mdl)
536 phl_disp_eng_clr_pending_msg(cmd_ctrl->phl_info, msg->band_idx);
537 cmd_ctrl->mon_mdl = false;
538 break;
539 }
540 }
541
_internal_msg_hdlr(void * dispr,struct cmd_controller * cmd_ctrl,struct phl_msg * msg)542 static enum phl_mdl_ret_code _internal_msg_hdlr(void *dispr,
543 struct cmd_controller *cmd_ctrl, struct phl_msg *msg)
544 {
545 enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
546 struct phl_info_t *phl_info = cmd_ctrl->phl_info;
547
548 /* sender is controller itself */
549 if (MSG_MDL_ID_FIELD(msg->msg_id) == PHL_MDL_PHY_MGNT) {
550 ret = _ctrler_msg_hdlr(phl_info, msg);
551 } else if (MSG_MDL_ID_FIELD(msg->msg_id) == PHL_MDL_TX) {
552 ret = _tx_msg_hdlr(phl_info, msg);
553 } else if (MSG_MDL_ID_FIELD(msg->msg_id) == PHL_MDL_RX) {
554 ret = _rx_msg_hdlr(phl_info, msg);
555 }
556
557 return ret;
558 }
559
560 static enum phl_mdl_ret_code
_external_msg_hdlr(void * dispr,struct cmd_controller * cmd_ctrl,struct phl_msg * msg)561 _external_msg_hdlr(void *dispr,
562 struct cmd_controller *cmd_ctrl, struct phl_msg *msg)
563 {
564 struct phl_info_t *phl_info = cmd_ctrl->phl_info;
565 struct rtw_phl_com_t *phl_com = phl_info->phl_com;
566 enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
567
568 if (phl_com->dev_state & RTW_DEV_RESUMING) {
569 PHL_WARN("Controller: MDL_ID(%d)-EVT_ID(%d) is sent during RTW_DEV_RESUMING!\n",
570 MSG_MDL_ID_FIELD(msg->msg_id), MSG_EVT_ID_FIELD(msg->msg_id));
571 }
572
573 if (phl_com->dev_state & RTW_DEV_SURPRISE_REMOVAL) {
574 PHL_TRACE(COMP_PHL_CMDDISP, _PHL_INFO_, "Controller: msg fail due to invalid device state\n");
575 return MDL_RET_FAIL;
576 }
577
578 _mon_msg_hdlr(cmd_ctrl, msg);
579
580 switch (MSG_EVT_ID_FIELD(msg->msg_id)) {
581 case MSG_EVT_HW_TRX_RST_RESUME:
582 ret = _dispr_hw_trx_rst_resume_ctrl(phl_info, msg);
583 break;
584 case MSG_EVT_HW_TRX_PAUSE:
585 ret = _dispr_hw_trx_pause_ctrl(phl_info, msg);
586 break;
587 case MSG_EVT_SW_TX_RESUME:
588 ret = _dispr_sw_tx_resume_ctrl(phl_info, msg);
589 break;
590 case MSG_EVT_SW_RX_RESUME:
591 ret = _dispr_sw_rx_resume_ctrl(phl_info, msg);
592 break;
593 case MSG_EVT_SW_TX_PAUSE:
594 ret = _dispr_sw_tx_pause_ctrl(phl_info, msg);
595 break;
596 case MSG_EVT_SW_RX_PAUSE:
597 ret = _dispr_sw_rx_pause_ctrl(phl_info, msg);
598 break;
599 case MSG_EVT_SW_TX_RESET:
600 ret = _dispr_sw_tx_reset_ctrl(phl_info, msg);
601 break;
602 case MSG_EVT_SW_RX_RESET:
603 ret = _dispr_sw_rx_reset_ctrl(phl_info, msg);
604 break;
605 case MSG_EVT_TRX_SW_PAUSE:
606 ret = _dispr_trx_sw_pause_ctrl(phl_info, msg);
607 break;
608 case MSG_EVT_TRX_SW_RESUME:
609 ret = _dispr_trx_sw_resume_ctrl(phl_info, msg);
610 break;
611 case MSG_EVT_TRX_PAUSE_W_RST:
612 ret = _dispr_trx_pause_w_rst_ctrl(phl_info, msg);
613 break;
614 case MSG_EVT_TRX_RESUME_W_RST:
615 ret = _dispr_trx_resume_w_rst_ctrl(phl_info, msg);
616 break;
617 case MSG_EVT_MDL_CHECK_STOP:
618 ret = _dispr_mdl_stop_ctrl(phl_info, cmd_ctrl);
619 break;
620 default:
621 break;
622 }
623
624 return ret;
625 }
626 enum phl_mdl_ret_code
_dispr_ctrl_msg_hdlr(void * dispr,void * priv,struct phl_msg * msg)627 _dispr_ctrl_msg_hdlr(void *dispr,
628 void *priv,
629 struct phl_msg *msg)
630 {
631 enum phl_mdl_ret_code ret = MDL_RET_IGNORE;
632 struct cmd_controller *cmd_ctrl = (struct cmd_controller *)priv;
633
634 FUNCIN();
635 if (IS_MSG_FAIL(msg->msg_id)) {
636 PHL_TRACE(COMP_PHL_DBG, _PHL_WARNING_,
637 "%s: cmd dispatcher notify cmd failure: 0x%x.\n",
638 __FUNCTION__, msg->msg_id);
639 _fail_hdlr(dispr, cmd_ctrl->phl_info, msg);
640 FUNCOUT();
641 return MDL_RET_FAIL;
642 }
643
644 if (IS_DISPR_CTRL(MSG_MDL_ID_FIELD(msg->msg_id)))
645 ret = _internal_msg_hdlr(dispr, cmd_ctrl, msg);
646 else
647 ret = _external_msg_hdlr(dispr, cmd_ctrl, msg);
648 FUNCOUT();
649 return ret;
650 }
651
652 enum phl_mdl_ret_code
_dispr_ctrl_set_info(void * dispr,void * priv,struct phl_module_op_info * info)653 _dispr_ctrl_set_info(void *dispr,
654 void *priv,
655 struct phl_module_op_info *info)
656 {
657 PHL_INFO("%s(): \n", __func__);
658
659 return MDL_RET_IGNORE;
660 }
661
662 enum phl_mdl_ret_code
_dispr_ctrl_query_info(void * dispr,void * priv,struct phl_module_op_info * info)663 _dispr_ctrl_query_info(void *dispr, void *priv,
664 struct phl_module_op_info *info)
665 {
666 PHL_INFO("%s(): \n", __func__);
667
668 return MDL_RET_IGNORE;
669 }
670
dispr_ctrl_hook_ops(void * dispr,struct phl_bk_module_ops * ops)671 void dispr_ctrl_hook_ops(void *dispr, struct phl_bk_module_ops *ops)
672 {
673 if (ops == NULL)
674 return;
675 ops->init = _dispr_ctrl_init;
676 ops->deinit = _dispr_ctrl_deinit;
677 ops->start = _dispr_ctrl_start;
678 ops->stop = _dispr_ctrl_stop;
679 ops->msg_hdlr = _dispr_ctrl_msg_hdlr;
680 ops->set_info = _dispr_ctrl_set_info;
681 ops->query_info = _dispr_ctrl_query_info;
682 }
683 #endif
684
685