1 /****************************************************************************** 2 * 3 * Copyright(c) 2019 - 2020 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef _HAL_STRUCT_H_ 16 #define _HAL_STRUCT_H_ 17 18 19 struct hal_info_t; 20 21 #define hal_get_trx_ops(_halinfo) (_halinfo->trx_ops) 22 /** 23 * struct hal_trx_ops - hw ic specific operations 24 * 25 * @init: the function for initializing IC specific data and hw configuration 26 * @deinit: the function for deinitializing IC specific data and hw configuration 27 * @query_tx_res: the function for querying hw tx resource 28 * @query_rx_res: the function for querying hw rx resource 29 * @map_hw_tx_chnl: the function for getting mapping hw tx channel 30 * @qsel_to_tid: the function for converting hw qsel to tid value 31 * @query_txch_num: the function for querying total hw tx dma channels number 32 * @query_rxch_num: the function for querying total hw rx dma channels number 33 * @update_wd: the function for updating wd page for xmit packet 34 * @update_txbd: the function for updating tx bd for xmit packet 35 * @tx_start: the function to trigger hw to start tx 36 * @get_fwcmd_queue_idx: the function to get fwcmd queue idx 37 * @check_rxrdy: the function check if hw rx buffer is ready to access 38 * @handle_rxbd_info: the function handling hw rxbd information 39 * @handle_rx_buffer: the function handling hw rx buffer 40 * @update_rxbd: the function for updating rx bd for recv packet 41 * @notify_rxdone: the function to notify hw rx done 42 * @handle_wp_rpt: the function parsing wp report content 43 */ 44 struct hal_trx_ops { 45 u8 (*map_hw_tx_chnl)(u16 macid, enum rtw_phl_ring_cat cat, u8 band); 46 u8 (*query_txch_num)(void); 47 u8 (*query_rxch_num)(void); 48 49 #ifdef CONFIG_PCI_HCI 50 enum rtw_hal_status (*init)(struct hal_info_t *hal, u8 *txbd_buf, u8 *rxbd_buf); 51 void (*deinit)(struct hal_info_t *hal); 52 53 u16 (*query_tx_res)(struct rtw_hal_com_t *hal_com, u8 dma_ch, 54 u16 *host_idx, u16 *hw_idx); 55 u16 (*query_rx_res)(struct rtw_hal_com_t *hal_com, u8 dma_ch, 56 u16 *host_idx, u16 *hw_idx); 57 void (*cfg_dma_io)(struct hal_info_t *hal, u8 en); 58 void (*cfg_txdma)(struct hal_info_t *hal, u8 en, u8 dma_ch); 59 void (*cfg_wow_txdma)(struct hal_info_t *hal, u8 en); 60 void (*cfg_txhci)(struct hal_info_t *hal, u8 en); 61 void (*cfg_rxhci)(struct hal_info_t *hal, u8 en); 62 void (*clr_rwptr)(struct hal_info_t *hal); 63 void (*rst_bdram)(struct hal_info_t *hal); 64 u8 (*poll_txdma_idle)(struct hal_info_t *hal); 65 void (*cfg_rsvd_ctrl)(struct hal_info_t *hal); 66 u8 (*qsel_to_tid)(struct hal_info_t *hal, u8 qsel_id, u8 tid_indic); 67 68 enum rtw_hal_status 69 (*update_wd)(struct hal_info_t *hal, struct rtw_phl_pkt_req *req); 70 enum rtw_hal_status 71 (*update_txbd)(struct hal_info_t *hal, 72 struct tx_base_desc *txbd_ring, 73 struct rtw_wd_page *wd_page, 74 u8 ch_idx, u16 wd_num); 75 enum rtw_hal_status 76 (*tx_start)(struct hal_info_t *hal, 77 struct tx_base_desc *txbd, u8 dma_ch); 78 79 u8 (*get_fwcmd_queue_idx)(void); 80 81 u8 (*check_rxrdy)(struct rtw_phl_com_t *phl_com, u8 *rxbuf, u8 dma_ch); 82 enum rtw_hal_status 83 (*handle_rx_buffer)(struct rtw_phl_com_t *phl_com, 84 struct hal_info_t *hal, 85 u8 *buf, u32 buf_size, 86 struct rtw_phl_rx_pkt *rxpkt); 87 u8 (*handle_rxbd_info)(struct hal_info_t *hal, u8 *rxbuf, u16 *buf_size); 88 89 enum rtw_hal_status 90 (*update_rxbd)(struct hal_info_t *hal, 91 struct rx_base_desc *rxbd, 92 struct rtw_rx_buf *rx_buf); 93 94 enum rtw_hal_status 95 (*notify_rxdone)(struct hal_info_t *hal, 96 struct rx_base_desc *rxbd, u8 ch, u16 rxcnt); 97 98 u16 (*handle_wp_rpt)(struct hal_info_t *hal, u8 *rp, u16 len, 99 u8 *sw_retry, u8 *dma_ch, u16 *wp_seq, u8 *txsts); 100 #endif /*CONFIG_PCI_HCI*/ 101 102 #ifdef CONFIG_USB_HCI 103 enum rtw_hal_status (*init)(struct hal_info_t *hal); 104 void (*deinit)(struct hal_info_t *hal); 105 106 enum rtw_hal_status 107 (*hal_fill_wd)(struct hal_info_t *hal, struct rtw_xmit_req *tx_req, 108 u8 *wd_buf, u32 *wd_len); 109 u8 (*get_bulkout_id)(struct hal_info_t *hal, u8 ch_dma, u8 mode); 110 enum rtw_hal_status 111 (*handle_rx_buffer)(struct rtw_phl_com_t *phl_com, 112 struct hal_info_t *hal, 113 u8 *buf, u32 buf_size, 114 struct rtw_phl_rx_pkt *rxpkt); 115 enum rtw_hal_status 116 (*query_hal_info)(struct hal_info_t *hal, u8 info_id, void *value); 117 enum rtw_hal_status 118 (*usb_tx_agg_cfg)(struct hal_info_t *hal, u8* wd_buf, u8 agg_num); 119 enum rtw_hal_status 120 (*usb_rx_agg_cfg)(struct hal_info_t *hal, u8 mode, u8 agg_mode, 121 u8 drv_define, u8 timeout, u8 size, u8 pkt_num); 122 u8 (*get_fwcmd_queue_idx)(void); 123 u8 (*get_max_bulkout_wd_num)(struct hal_info_t *hal); 124 void (*cfg_dma_io)(struct hal_info_t *hal, u8 en); 125 void (*cfg_txdma)(struct hal_info_t *hal, u8 en, u8 dma_ch); 126 void (*cfg_txhci)(struct hal_info_t *hal, u8 en); 127 void (*cfg_rxhci)(struct hal_info_t *hal, u8 en); 128 void (*clr_rwptr)(struct hal_info_t *hal); 129 void (*rst_bdram)(struct hal_info_t *hal); 130 void (*cfg_rsvd_ctrl)(struct hal_info_t *hal); 131 u16 (*handle_wp_rpt)(struct hal_info_t *hal, u8 *rp, u16 len, 132 u8 *mac_id, u8 *ac_queue, u8 *txsts); 133 #endif /*CONFIG_USB_HCI*/ 134 135 #ifdef CONFIG_SDIO_HCI 136 enum rtw_hal_status (*init)(struct hal_info_t *hal); 137 void (*deinit)(struct hal_info_t *hal); 138 u16 (*query_tx_res)(struct rtw_hal_com_t *hal_com, u8 dma_ch, 139 u16 *host_idx, u16 *hw_idx); 140 u16 (*query_rx_res)(struct rtw_hal_com_t *hal_com, u8 dma_ch, 141 u16 *host_idx, u16 *hw_idx); 142 143 enum rtw_hal_status 144 (*hal_fill_wd)(struct hal_info_t *hal, struct rtw_xmit_req *tx_req, 145 u8 *wd_buf, u32 *wd_len); 146 u8 (*get_fwcmd_queue_idx)(void); 147 void (*cfg_dma_io)(struct hal_info_t *hal, u8 en); 148 void (*cfg_txdma)(struct hal_info_t *hal, u8 en, u8 dma_ch); 149 void (*cfg_txhci)(struct hal_info_t *hal, u8 en); 150 void (*cfg_rxhci)(struct hal_info_t *hal, u8 en); 151 void (*clr_rwptr)(struct hal_info_t *hal); 152 void (*rst_bdram)(struct hal_info_t *hal); 153 void (*cfg_rsvd_ctrl)(struct hal_info_t *hal); 154 155 enum rtw_hal_status(*handle_rx_buffer)(struct rtw_phl_com_t *phl_com, 156 struct hal_info_t *hal, 157 u8 *buf, u32 buf_size, 158 struct rtw_phl_rx_pkt *rxpkt); 159 #endif 160 161 }; 162 163 #define hal_get_ops(_halinfo) (&_halinfo->hal_ops) 164 165 struct hal_ops_t { 166 /*** initialize section ***/ 167 void (*read_chip_version)(struct rtw_phl_com_t *phl_com, 168 struct hal_info_t *hal); 169 void (*init_hal_spec)(struct rtw_phl_com_t *phl_com, 170 struct hal_info_t *hal); 171 void (*init_default_value)(struct hal_info_t *hal, struct hal_intr_mask_cfg *cfg); 172 u32 (*hal_hci_configure)(struct rtw_phl_com_t *phl_com, 173 struct hal_info_t *hal, 174 struct rtw_ic_info *ic_info); 175 176 enum rtw_hal_status (*hal_get_efuse)(struct rtw_phl_com_t *phl_com, 177 struct hal_info_t *hal); 178 enum rtw_hal_status (*hal_init)(struct rtw_phl_com_t *phl_com, 179 struct hal_info_t *hal); 180 void (*hal_deinit)(struct rtw_phl_com_t *phl_com, 181 struct hal_info_t *hal); 182 enum rtw_hal_status (*hal_start)(struct rtw_phl_com_t *phl_com, 183 struct hal_info_t *hal); 184 enum rtw_hal_status (*hal_stop)(struct rtw_phl_com_t *phl_com, 185 struct hal_info_t *hal); 186 enum rtw_hal_status (*hal_cfg_fw)(struct rtw_phl_com_t *phl_com, 187 struct hal_info_t *hal, 188 char *ic_name, 189 enum rtw_fw_type fw_type); 190 #ifdef CONFIG_WOWLAN 191 enum rtw_hal_status (*hal_wow_init)(struct rtw_phl_com_t *phl_com, 192 struct hal_info_t *hal, struct rtw_phl_stainfo_t *sta); 193 enum rtw_hal_status (*hal_wow_deinit)(struct rtw_phl_com_t *phl_com, 194 struct hal_info_t *hal, struct rtw_phl_stainfo_t *sta); 195 #endif /* CONFIG_WOWLAN */ 196 197 /* MP */ 198 enum rtw_hal_status (*hal_mp_init)(struct rtw_phl_com_t *phl_com, 199 struct hal_info_t *hal); 200 enum rtw_hal_status (*hal_mp_deinit)(struct rtw_phl_com_t *phl_com, 201 struct hal_info_t *hal); 202 /*IO ops*/ 203 u32 (*read_macreg)(struct hal_info_t *hal, 204 u32 offset, u32 bit_mask); 205 void (*write_macreg)(struct hal_info_t *hal, 206 u32 offset, u32 bit_mask, u32 data); 207 u32 (*read_bbreg)(struct hal_info_t *hal, 208 u32 offset, u32 bit_mask); 209 void (*write_bbreg)(struct hal_info_t *hal, 210 u32 offset, u32 bit_mask, u32 data); 211 u32 (*read_rfreg)(struct hal_info_t *hal, 212 enum rf_path path, u32 offset, u32 bit_mask); 213 void (*write_rfreg)(struct hal_info_t *hal, 214 enum rf_path path, u32 offset, u32 bit_mask, u32 data); 215 #ifdef RTW_WKARD_BUS_WRITE 216 enum rtw_hal_status (*write_reg_post_cfg)(struct hal_info_t *hal_info, 217 u32 offset, u32 value); 218 #endif 219 220 /*** interrupt hdl section ***/ 221 void (*enable_interrupt)(struct hal_info_t *hal); 222 void (*disable_interrupt)(struct hal_info_t *hal); 223 void (*config_interrupt)(struct hal_info_t *hal, enum rtw_phl_config_int int_mode); 224 bool (*recognize_interrupt)(struct hal_info_t *hal); 225 bool (*recognize_halt_c2h_interrupt)(struct hal_info_t *hal); 226 void (*clear_interrupt)(struct hal_info_t *hal); 227 u32 (*interrupt_handler)(struct hal_info_t *hal); 228 void (*restore_interrupt)(struct hal_info_t *hal); 229 void (*restore_rx_interrupt)(struct hal_info_t *hal); 230 231 #ifdef RTW_PHL_BCN //hal_ops_t 232 enum rtw_hal_status (*cfg_bcn)(struct rtw_phl_com_t *phl_com, 233 struct hal_info_t *hal, struct rtw_bcn_entry *bcn_entry); 234 enum rtw_hal_status (*upt_bcn)(struct rtw_phl_com_t *phl_com, 235 struct hal_info_t *hal, struct rtw_bcn_entry *bcn_entry); 236 #endif 237 238 enum rtw_hal_status (*pkt_ofld)(struct hal_info_t *hal, u8 *id, u8 op, 239 u8 *pkt, u16 *len); 240 enum rtw_hal_status (*pkt_update_ids)(struct hal_info_t *hal, 241 struct pkt_ofld_entry *entry); 242 }; 243 244 struct hal_info_t { 245 struct rtw_hal_com_t *hal_com; 246 _os_atomic hal_mac_mem; 247 248 struct hal_trx_ops *trx_ops; 249 struct hal_ops_t hal_ops; 250 #ifdef CONFIG_PCI_HCI 251 void *txch_map; 252 #endif 253 void *rpr_cfg; 254 255 void *mac; /*halmac*/ 256 void *bb; 257 void *rf; 258 void *btc; 259 void *efuse; 260 enum rtw_rx_fltr_mode rx_fltr_mode; 261 u8 monitor_mode; /* default: 0 */ 262 }; 263 264 struct hal_c2h_hdl { 265 u8 cat; 266 u8 cls_min; 267 u8 cls_max; 268 u32 (*c2h_hdl)(void *hal, struct rtw_c2h_info *c2h); 269 }; 270 271 272 #ifdef CONFIG_PHL_CHANNEL_INFO 273 274 struct chinfo_bbcr_cfg { 275 bool ch_i_phy0_en; 276 bool ch_i_phy1_en; 277 bool ch_i_data_src; 278 bool ch_i_cmprs; 279 u8 ch_i_grp_num_non_he; 280 u8 ch_i_grp_num_he; 281 u8 ch_i_blk_start_idx; 282 u8 ch_i_blk_end_idx; 283 u32 ch_i_ele_bitmap; 284 bool ch_i_type; 285 u8 ch_i_seg_len; 286 }; 287 288 struct ch_rpt_hdr_info { 289 u16 total_len_l; /*header(16byte) + Raw data length(Unit: byte)*/ 290 #if (PLATFOM_IS_LITTLE_ENDIAN) 291 u8 total_len_m:1; 292 u8 total_seg_num:7; 293 #else 294 u8 total_seg_num:7; 295 u8 total_len_m:1; 296 #endif 297 u8 avg_noise_pow; 298 #if (PLATFOM_IS_LITTLE_ENDIAN) 299 u8 is_pkt_end:1; 300 u8 set_valid:1; 301 u8 n_rx:3; 302 u8 n_sts:3; 303 #else 304 u8 n_sts:3; 305 u8 n_rx:3; 306 u8 set_valid:1; 307 u8 is_pkt_end:1; 308 #endif 309 u8 segment_size; /*unit (8Byte)*/ 310 u8 evm[2]; 311 }; 312 313 struct phy_info_rpt { 314 u8 rssi[2]; 315 u16 rsvd_0; 316 u8 rssi_avg; 317 #if (PLATFOM_IS_LITTLE_ENDIAN) 318 u8 rxsc:4; 319 u8 rsvd_1:4; 320 #else 321 u8 rsvd_1:4; 322 u8 rxsc:4; 323 #endif 324 u16 rsvd_2; 325 }; 326 327 328 struct ch_info_drv_rpt { 329 u32 raw_data_len; 330 u8 seg_idx_curr; 331 }; 332 333 #endif /* CONFIG_PHL_CHANNEL_INFO */ 334 #endif /*_HAL_STRUCT_H_*/ 335