1 /****************************************************************************** 2 * 3 * Copyright(c) 2019 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 16 #ifndef _HAL_LD_FILE_H_ 17 #define _HAL_LD_FILE_H_ 18 19 #define PHYPG_BAND2G 0 20 #define PHYPG_BAND5G 1 21 #define PHYPG_RF1Tx 0 22 #define PHYPG_RF2Tx 1 23 #define PHYPG_OFFSET 15 24 25 enum PHY_PG_RATE_def { 26 CCK_11M_1M = 0, 27 OFDM_18M_6M = 1, 28 OFDM_54M_24M = 2, 29 HE1SS_MCS3_0 = 3, 30 HE1SS_MCS7_4 = 4, 31 HE1SS_MCS11_8 = 5, 32 HE1SS_DCM4_0 = 6, 33 HE2SS_MCS3_0 = 3, 34 HE2SS_MCS7_4 = 4, 35 HE2SS_MCS11_8 = 5, 36 HE2SS_DCM4_0 = 6, 37 Legacy_AllRate = 7, 38 HE_AllRate = 8, 39 }; 40 41 struct _hal_file_regd_ext { 42 u16 domain; 43 char country[2]; 44 char reg_name[10]; 45 }; 46 47 typedef struct hal_txpwr_lmt_t { 48 u8 band; 49 u8 bw; 50 u8 ntx; 51 u8 rs; 52 u8 bf; 53 u8 reg; 54 u8 ch; 55 s8 val; 56 u8 tx_shap_idx; 57 } HAL_TXPWR_LMT_T , *PHAL_TXPWR_LMT_T; 58 59 typedef struct hal_txpwr_lmt_ru_t { 60 u8 band; 61 u8 rubw; 62 u8 ntx; 63 u8 rs; 64 u8 reg; 65 u8 ch; 66 s8 val; 67 u8 tx_shap_idx; 68 } Hal_Txpwr_lmt_Ru_t , *pHal_Txpwr_lmt_Ru_t; 69 70 enum _halrf_tx_pw_lmt_ru_bandwidth_type { 71 _PW_LMT_RU_BW_RU26, 72 _PW_LMT_RU_BW_RU52, 73 _PW_LMT_RU_BW_RU106, 74 _PW_LMT_RU_BW_NULL 75 }; 76 77 enum _halrf_pw_lmt_band_type { 78 _PW_LMT_BAND_2_4G = 0, 79 _PW_LMT_BAND_5G = 1 80 }; 81 82 enum _halrf_pw_lmt_bandwidth_type { 83 _PW_LMT_BW_20M = 0, 84 _PW_LMT_BW_40M = 1, 85 _PW_LMT_BW_80M = 2, 86 _PW_LMT_BW_160M = 3, 87 _PW_LMT_MAX_BANDWIDTH_NUM = 4 88 }; 89 90 enum _halrf_pw_lmt_ratesection_type { 91 _PW_LMT_RS_CCK = 0, 92 _PW_LMT_RS_OFDM = 1, 93 _PW_LMT_RS_HT = 2, 94 _PW_LMT_RS_VHT = 3, 95 _PW_LMT_RS_HE = 4, 96 _PW_LMT_MAX_RS_NUM = 5 97 }; 98 99 enum _halrf_pw_lmt_rfpath_type { 100 _PW_LMT_PH_1T = 0, 101 _PW_LMT_PH_2T = 1, 102 _PW_LMT_PH_3T = 2, 103 _PW_LMT_PH_4T = 3, 104 _PW_LMT_MAX_PH_NUM = 4 105 }; 106 107 enum _halrf_pw_lmt_beamforming_type { 108 _PW_LMT_NONBF = 0, 109 _PW_LMT_BF = 1, 110 _PW_LMT_MAX_BF_NUM = 2 111 }; 112 113 /*@--------------------------Define Parameters-------------------------------*/ 114 #define AVG_THERMAL_NUM 8 115 #define MAX_RF_PATH 4 116 #define DELTA_SWINGIDX_SIZE 30 117 #define BAND_NUM 4 118 #define DELTA_SWINTSSI_SIZE 61 119 120 /*@---------------------------End Define Parameters---------------------------*/ 121 122 struct hal_txpwr_track_t { 123 /* u8 is_txpowertracking; */ 124 u8 tx_powercount; 125 bool is_txpowertracking_init; 126 bool is_txpowertracking; 127 u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */ 128 u8 tm_trigger; 129 u8 internal_pa_5g[2]; /* pathA / pathB */ 130 131 u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */ 132 u8 thermal_value; 133 u8 thermal_value_path[MAX_RF_PATH]; 134 u8 thermal_value_lck; 135 u8 thermal_value_iqk; 136 s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */ 137 u8 thermal_value_avg[AVG_THERMAL_NUM]; 138 u8 thermal_value_avg_path[MAX_RF_PATH][AVG_THERMAL_NUM]; 139 u8 thermal_value_avg_index; 140 u8 thermal_value_avg_index_path[MAX_RF_PATH]; 141 s8 power_index_offset_path[MAX_RF_PATH]; 142 143 u8 thermal_value_rx_gain; 144 u8 thermal_value_crystal; 145 u8 thermal_value_dpk_store; 146 u8 thermal_value_dpk_track; 147 bool txpowertracking_in_progress; 148 149 bool is_reloadtxpowerindex; 150 u8 is_rf_pi_enable; 151 u32 txpowertracking_callback_cnt; /* cosa add for debug */ 152 153 u8 is_cck_in_ch14; 154 u8 CCK_index; 155 u8 OFDM_index[MAX_RF_PATH]; 156 s8 power_index_offset; 157 s8 delta_power_index; 158 s8 delta_power_index_path[MAX_RF_PATH]; 159 s8 delta_power_index_last; 160 s8 delta_power_index_last_path[MAX_RF_PATH]; 161 bool is_tx_power_changed; 162 163 /*struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];*/ 164 u8 delta_lck; 165 s8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE]; 166 s8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE]; 167 s8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE]; 168 s8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE]; 169 s8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE]; 170 s8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE]; 171 s8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE]; 172 s8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE]; 173 s8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE]; 174 s8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE]; 175 s8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE]; 176 s8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE]; 177 s8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE]; 178 s8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE]; 179 s8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE]; 180 s8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE]; 181 s8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; 182 s8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; 183 s8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; 184 s8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; 185 s8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; 186 s8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; 187 s8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; 188 s8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; 189 s8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE]; 190 s8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE]; 191 s8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE]; 192 s8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE]; 193 s8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE]; 194 s8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE]; 195 s8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE]; 196 s8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE]; 197 s8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE]; 198 s8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE]; 199 s8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE]; 200 s8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE]; 201 s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE]; 202 s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE]; 203 s8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE]; 204 s8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE]; 205 206 u8 bb_swing_idx_ofdm[MAX_RF_PATH]; 207 u8 bb_swing_idx_ofdm_current; 208 u8 bb_swing_idx_ofdm_base; 209 u8 bb_swing_idx_ofdm_base_path[MAX_RF_PATH]; 210 bool bb_swing_flag_ofdm; 211 u8 bb_swing_idx_cck; 212 u8 bb_swing_idx_cck_current; 213 u8 bb_swing_idx_cck_base; 214 u8 default_ofdm_index; 215 u8 default_cck_index; 216 bool bb_swing_flag_cck; 217 218 s8 absolute_ofdm_swing_idx[MAX_RF_PATH]; 219 s8 remnant_ofdm_swing_idx[MAX_RF_PATH]; 220 s8 absolute_cck_swing_idx[MAX_RF_PATH]; 221 s8 remnant_cck_swing_idx; 222 s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */ 223 bool modify_tx_agc_flag_path_a; 224 bool modify_tx_agc_flag_path_b; 225 bool modify_tx_agc_flag_path_c; 226 bool modify_tx_agc_flag_path_d; 227 bool modify_tx_agc_flag_path_a_cck; 228 bool modify_tx_agc_flag_path_b_cck; 229 230 s8 kfree_offset[MAX_RF_PATH]; 231 /*Add by Yuchen for Kfree Phydm*/ 232 u8 reg_rf_kfree_enable; /*for registry*/ 233 u8 rf_kfree_enable; /*for efuse enable check*/ 234 }; 235 236 void rtw_hal_dl_all_para_file(struct rtw_phl_com_t *phl_com, char *ic_name, void *hal); 237 u8 rtw_hal_efuse_shadow_file_load(void *hal, char *ic_name, bool is_limit); 238 u8 rtw_hal_ld_fw_symbol(struct rtw_phl_com_t *phl_com, 239 struct rtw_hal_com_t *hal_com, const char *name, u8 **buf, u32 *buf_size); 240 #endif /*_HAL_LD_FILE_H_*/