1 /******************************************************************************
2 *
3 * Copyright(c) 2019 - 2020 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #define _HAL_INIT_C_
16 #include "hal_headers.h"
17
18 #if defined(CONFIG_PCI_HCI)
19 #include "hal_pci.h"
20 #elif defined(CONFIG_USB_HCI)
21 #include "hal_usb.h"
22 #elif defined(CONFIG_SDIO_HCI)
23 #include "hal_sdio.h"
24 #endif
25
26
27 /******************* IO APIs *******************/
rtw_hal_read8(void * h,u32 addr)28 u8 rtw_hal_read8(void *h, u32 addr)
29 {
30 struct hal_info_t *hal_info = (struct hal_info_t *)h;
31 struct rtw_hal_com_t *hal_com = hal_info->hal_com;
32
33 return hal_read8(hal_com, addr);
34 }
rtw_hal_read16(void * h,u32 addr)35 u16 rtw_hal_read16(void *h, u32 addr)
36 {
37 struct hal_info_t *hal_info = (struct hal_info_t *)h;
38 struct rtw_hal_com_t *hal_com = hal_info->hal_com;
39
40 return hal_read16(hal_com, addr);
41 }
rtw_hal_read32(void * h,u32 addr)42 u32 rtw_hal_read32(void *h, u32 addr)
43 {
44 struct hal_info_t *hal_info = (struct hal_info_t *)h;
45 struct rtw_hal_com_t *hal_com = hal_info->hal_com;
46
47 return hal_read32(hal_com, addr);
48 }
rtw_hal_write8(void * h,u32 addr,u8 val)49 void rtw_hal_write8(void *h, u32 addr, u8 val)
50 {
51 struct hal_info_t *hal_info = (struct hal_info_t *)h;
52 struct rtw_hal_com_t *hal_com = hal_info->hal_com;
53
54 hal_write8(hal_com, addr, val);
55 }
rtw_hal_write16(void * h,u32 addr,u16 val)56 void rtw_hal_write16(void *h, u32 addr, u16 val)
57 {
58 struct hal_info_t *hal_info = (struct hal_info_t *)h;
59 struct rtw_hal_com_t *hal_com = hal_info->hal_com;
60
61 hal_write16(hal_com, addr, val);
62 }
rtw_hal_write32(void * h,u32 addr,u32 val)63 void rtw_hal_write32(void *h, u32 addr, u32 val)
64 {
65 struct hal_info_t *hal_info = (struct hal_info_t *)h;
66 struct rtw_hal_com_t *hal_com = hal_info->hal_com;
67
68 hal_write32(hal_com, addr, val);
69 }
70
rtw_hal_read_macreg(void * h,u32 offset,u32 bit_mask)71 u32 rtw_hal_read_macreg(void *h, u32 offset, u32 bit_mask)
72 {
73 struct hal_info_t *hal = (struct hal_info_t *)h;
74 struct hal_ops_t *hal_ops = hal_get_ops(hal);
75
76 return hal_ops->read_macreg(hal, offset, bit_mask);
77 }
rtw_hal_write_macreg(void * h,u32 offset,u32 bit_mask,u32 data)78 void rtw_hal_write_macreg(void *h,
79 u32 offset, u32 bit_mask, u32 data)
80 {
81 struct hal_info_t *hal = (struct hal_info_t *)h;
82 struct hal_ops_t *hal_ops = hal_get_ops(hal);
83
84 hal_ops->write_macreg(hal, offset, bit_mask, data);
85 }
rtw_hal_read_bbreg(void * h,u32 offset,u32 bit_mask)86 u32 rtw_hal_read_bbreg(void *h, u32 offset, u32 bit_mask)
87 {
88 struct hal_info_t *hal = (struct hal_info_t *)h;
89 struct hal_ops_t *hal_ops = hal_get_ops(hal);
90
91 return hal_ops->read_bbreg(hal, offset, bit_mask);
92 }
rtw_hal_write_bbreg(void * h,u32 offset,u32 bit_mask,u32 data)93 void rtw_hal_write_bbreg(void *h,
94 u32 offset, u32 bit_mask, u32 data)
95 {
96 struct hal_info_t *hal = (struct hal_info_t *)h;
97 struct hal_ops_t *hal_ops = hal_get_ops(hal);
98
99 hal_ops->write_bbreg(hal, offset, bit_mask, data);
100 }
101
rtw_hal_read_rfreg(void * h,enum rf_path path,u32 offset,u32 bit_mask)102 u32 rtw_hal_read_rfreg(void *h,
103 enum rf_path path, u32 offset, u32 bit_mask)
104 {
105 struct hal_info_t *hal = (struct hal_info_t *)h;
106 struct hal_ops_t *hal_ops = hal_get_ops(hal);
107
108 return hal_ops->read_rfreg(hal, path, offset, bit_mask);
109 }
110
rtw_hal_write_rfreg(void * h,enum rf_path path,u32 offset,u32 bit_mask,u32 data)111 void rtw_hal_write_rfreg(void *h,
112 enum rf_path path, u32 offset, u32 bit_mask, u32 data)
113 {
114 struct hal_info_t *hal = (struct hal_info_t *)h;
115 struct hal_ops_t *hal_ops = hal_get_ops(hal);
116
117 hal_ops->write_rfreg(hal, path, offset, bit_mask, data);
118 }
119
120
121 #ifdef PHL_PLATFORM_LINUX
rtw_hal_mac_reg_dump(void * sel,void * h)122 void rtw_hal_mac_reg_dump(void *sel, void *h)
123 {
124 struct hal_info_t *hal_info = (struct hal_info_t *)h;
125 struct rtw_hal_com_t *hal = hal_info->hal_com;
126 int i, j = 1;
127
128 RTW_PRINT_SEL(sel, "======= MAC REG =======\n");
129
130 for (i = 0x0; i < 0x800; i += 4) {
131 if (j % 4 == 1)
132 RTW_PRINT_SEL(sel, "0x%04x", i);
133 _RTW_PRINT_SEL(sel, " 0x%08x ", hal_read32(hal, i));
134 if ((j++) % 4 == 0)
135 _RTW_PRINT_SEL(sel, "\n");
136 }
137
138 #if 1
139 for (i = 0x1000; i < 0xF000; i += 4) {
140 if (j % 4 == 1)
141 RTW_PRINT_SEL(sel, "0x%04x", i);
142 _RTW_PRINT_SEL(sel, " 0x%08x ", hal_read32(hal, i));
143 if ((j++) % 4 == 0)
144 _RTW_PRINT_SEL(sel, "\n");
145 }
146 #endif
147 }
148
rtw_hal_bb_reg_dump(void * sel,void * h)149 void rtw_hal_bb_reg_dump(void *sel, void *h)
150 {
151 struct hal_info_t *hal_info = (struct hal_info_t *)h;
152 struct rtw_hal_com_t *hal = hal_info->hal_com;
153 int i, j = 1;
154
155 RTW_PRINT_SEL(sel, "======= BB REG =======\n");
156 for (i = 0x800; i < 0x1000; i += 4) {
157 if (j % 4 == 1)
158 RTW_PRINT_SEL(sel, "0x%04x", i);
159 _RTW_PRINT_SEL(sel, " 0x%08x ", hal_read32(hal, i));
160 if ((j++) % 4 == 0)
161 _RTW_PRINT_SEL(sel, "\n");
162 }
163
164 #if 0
165 for (i = 0x1800; i < 0x2000; i += 4) {
166 if (j % 4 == 1)
167 RTW_PRINT_SEL(sel, "0x%04x", i);
168 _RTW_PRINT_SEL(sel, " 0x%08x ", hal_read32(hal, i));
169 if ((j++) % 4 == 0)
170 _RTW_PRINT_SEL(sel, "\n");
171 }
172 #endif
173
174 #if 0
175 for (i = 0x2c00; i < 0x2c60; i += 4) {
176 if (j % 4 == 1)
177 RTW_PRINT_SEL(sel, "0x%04x", i);
178 _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
179 if ((j++) % 4 == 0)
180 _RTW_PRINT_SEL(sel, "\n");
181 }
182
183 for (i = 0x2d00; i < 0x2df0; i += 4) {
184 if (j % 4 == 1)
185 RTW_PRINT_SEL(sel, "0x%04x", i);
186 _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
187 if ((j++) % 4 == 0)
188 _RTW_PRINT_SEL(sel, "\n");
189 }
190
191 for (i = 0x4000; i < 0x4060; i += 4) {
192 if (j % 4 == 1)
193 RTW_PRINT_SEL(sel, "0x%04x", i);
194 _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
195 if ((j++) % 4 == 0)
196 _RTW_PRINT_SEL(sel, "\n");
197 }
198
199 for (i = 0x4100; i < 0x4200; i += 4) {
200 if (j % 4 == 1)
201 RTW_PRINT_SEL(sel, "0x%04x", i);
202 _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
203 if ((j++) % 4 == 0)
204 _RTW_PRINT_SEL(sel, "\n");
205 }
206
207 #endif
208
209 }
210
rtw_hal_bb_reg_dump_ex(void * sel,void * h)211 void rtw_hal_bb_reg_dump_ex(void *sel, void *h)
212 {
213 struct hal_info_t *hal_info = (struct hal_info_t *)h;
214 struct rtw_hal_com_t *hal = hal_info->hal_com;
215 int i;
216
217 RTW_PRINT_SEL(sel, "======= BB REG =======\n");
218 for (i = 0x800; i < 0x1000; i += 4) {
219 RTW_PRINT_SEL(sel, "0x%04x", i);
220 _RTW_PRINT_SEL(sel, " 0x%08x ", hal_read32(hal, i));
221 _RTW_PRINT_SEL(sel, "\n");
222 }
223
224 #if 0
225 for (i = 0x1800; i < 0x2000; i += 4) {
226 RTW_PRINT_SEL(sel, "0x%04x", i);
227 _RTW_PRINT_SEL(sel, " 0x%08x ", hal_read32(hal, i));
228 _RTW_PRINT_SEL(sel, "\n");
229 }
230 #endif
231 }
232
233
rtw_hal_rf_reg_dump(void * sel,void * h)234 void rtw_hal_rf_reg_dump(void *sel, void *h)
235 {
236 #ifdef RTW_WKARD_RF_CR_DUMP
237 int i, j = 1, path;
238 struct hal_info_t *hal_info = (struct hal_info_t *)h;
239 struct rtw_hal_com_t *hal = hal_info->hal_com;
240 u32 value;
241 u8 path_nums;
242
243 if (hal->rfpath_tx_num > hal->rfpath_rx_num)
244 path_nums = hal->rfpath_tx_num;
245 else
246 path_nums = hal->rfpath_rx_num;
247
248 RTW_PRINT_SEL(sel, "======= RF REG =======\n");
249 for (path = 0; path < path_nums; path++) {
250 RTW_PRINT_SEL(sel, "RF_Path(%x)\n", path);
251 for (i = 0; i < 0x100; i++) {
252 value = rtw_hal_read_rfreg(hal_info, path, i, 0xfffff);
253 if (j % 4 == 1)
254 RTW_PRINT_SEL(sel, "0x%02x ", i);
255 _RTW_PRINT_SEL(sel, " 0x%08x ", value);
256 if ((j++) % 4 == 0)
257 _RTW_PRINT_SEL(sel, "\n");
258 }
259 j = 1;
260 #ifdef CONFIG_RTL8852B
261 for (i = 0x10000; i < 0x10100; i++) {
262 value = rtw_hal_read_rfreg(hal_info, path, i, 0xfffff);
263 if (j % 4 == 1)
264 RTW_PRINT_SEL(sel, "0x%02x ", i);
265 _RTW_PRINT_SEL(sel, " 0x%08x ", value);
266 if ((j++) % 4 == 0)
267 _RTW_PRINT_SEL(sel, "\n");
268 }
269 _RTW_PRINT_SEL(sel, "\n");
270 #endif
271 }
272 #endif/*RTW_WKARD_RF_CR_DUMP*/
273
274 }
275 #endif
276
277 /**
278 * rtw_hal_get_sec_cam() - get the security cam raw data from HW
279 * @h: struct hal_info_t *
280 * @num: How many cam you wnat to dump from the first one.
281 * @buf: ptr to buffer which store the content from HW.
282 * If buf is NULL, use console as debug path.
283 * @size Size of allocated memroy for @buf.
284 * The size should be @num * size of security cam offset(0x20).
285 *
286 * Return rtw_hal_mac_get_addr_cam's return value in enum rtw_hal_status type.
287 */
288 enum rtw_hal_status
rtw_hal_get_sec_cam(void * h,u16 num,u8 * buf,u16 size)289 rtw_hal_get_sec_cam(void *h, u16 num, u8 *buf, u16 size)
290 {
291 struct hal_info_t *hal_info = (struct hal_info_t *)h;
292 enum rtw_hal_status ret = RTW_HAL_STATUS_SUCCESS;
293
294 ret = rtw_hal_mac_get_sec_cam(hal_info, num, buf, size);
295
296 return ret;
297 }
298
299 /**
300 * rtw_hal_get_addr_cam() - get the address cam raw data from HW
301 * @h: struct hal_info_t *
302 * @num: How many cam you wnat to dump from the first one.
303 * @buf: ptr to buffer which store the content from HW.
304 * If buf is NULL, use console as debug path.
305 * @size Size of allocated memroy for @buf.
306 * The size should be @num * size of Addr cam offset(0x40).
307 *
308 * Return rtw_hal_mac_get_addr_cam's return value in enum rtw_hal_status type.
309 */
310 enum rtw_hal_status
rtw_hal_get_addr_cam(void * h,u16 num,u8 * buf,u16 size)311 rtw_hal_get_addr_cam(void *h, u16 num, u8 *buf, u16 size)
312 {
313 struct hal_info_t *hal_info = (struct hal_info_t *)h;
314 enum rtw_hal_status ret = RTW_HAL_STATUS_SUCCESS;
315
316 ret = rtw_hal_mac_get_addr_cam(hal_info, num, buf, size);
317
318 return ret;
319 }
320
rtw_hal_enable_interrupt(struct rtw_phl_com_t * phl_com,void * h)321 void rtw_hal_enable_interrupt(struct rtw_phl_com_t *phl_com, void *h)
322 {
323 struct hal_info_t *hal = (struct hal_info_t *)h;
324 struct hal_ops_t *hal_ops = hal_get_ops(hal);
325
326 if (hal_ops->enable_interrupt)
327 hal_ops->enable_interrupt(hal);
328 }
329
rtw_hal_disable_interrupt(struct rtw_phl_com_t * phl_com,void * h)330 void rtw_hal_disable_interrupt(struct rtw_phl_com_t *phl_com, void *h)
331 {
332 struct hal_info_t *hal = (struct hal_info_t *)h;
333 struct hal_ops_t *hal_ops = hal_get_ops(hal);
334
335 if (hal_ops->disable_interrupt)
336 hal_ops->disable_interrupt(hal);
337 }
338
rtw_hal_config_interrupt(void * h,enum rtw_phl_config_int int_mode)339 void rtw_hal_config_interrupt(void *h, enum rtw_phl_config_int int_mode)
340 {
341 struct hal_info_t *hal = (struct hal_info_t *)h;
342 struct hal_ops_t *hal_ops = hal_get_ops(hal);
343
344 if (hal_ops->config_interrupt)
345 hal_ops->config_interrupt(hal, int_mode);
346 }
347
rtw_hal_recognize_interrupt(void * h)348 bool rtw_hal_recognize_interrupt(void *h)
349 {
350 struct hal_info_t *hal = (struct hal_info_t *)h;
351 struct hal_ops_t *hal_ops = hal_get_ops(hal);
352
353 if (hal_ops->recognize_interrupt)
354 return hal_ops->recognize_interrupt(hal);
355 else
356 return false;
357 }
358
rtw_hal_recognize_halt_c2h_interrupt(void * h)359 bool rtw_hal_recognize_halt_c2h_interrupt(void *h)
360 {
361 struct hal_info_t *hal = (struct hal_info_t *)h;
362 struct hal_ops_t *hal_ops = hal_get_ops(hal);
363
364 if (hal_ops->recognize_halt_c2h_interrupt)
365 return hal_ops->recognize_halt_c2h_interrupt(hal);
366 else
367 return false;
368 }
369
rtw_hal_clear_interrupt(void * h)370 void rtw_hal_clear_interrupt(void *h)
371 {
372 struct hal_info_t *hal = (struct hal_info_t *)h;
373 struct hal_ops_t *hal_ops = hal_get_ops(hal);
374
375 if (hal_ops->clear_interrupt)
376 hal_ops->clear_interrupt(hal);
377 }
378
rtw_hal_interrupt_handler(void * h)379 u32 rtw_hal_interrupt_handler(void *h)
380 {
381 struct hal_info_t *hal = (struct hal_info_t *)h;
382 struct hal_ops_t *hal_ops = hal_get_ops(hal);
383 u32 ret = 0;
384
385
386 if (hal_ops->interrupt_handler)
387 ret = hal_ops->interrupt_handler(hal);
388 else
389 PHL_DBG("hal_ops->interrupt_handler is NULL\n");
390
391 PHL_DBG("hal_ops->interrupt_handler ret=0x%x\n", ret);
392
393
394 return ret;
395 }
396
rtw_hal_restore_interrupt(struct rtw_phl_com_t * phl_com,void * h)397 void rtw_hal_restore_interrupt(struct rtw_phl_com_t *phl_com, void *h)
398 {
399 struct hal_info_t *hal = (struct hal_info_t *)h;
400 struct hal_ops_t *hal_ops = hal_get_ops(hal);
401
402 if (hal_ops->restore_interrupt)
403 hal_ops->restore_interrupt(hal);
404 }
405
rtw_hal_restore_rx_interrupt(void * h)406 void rtw_hal_restore_rx_interrupt(void *h)
407 {
408 struct hal_info_t *hal = (struct hal_info_t *)h;
409 struct hal_ops_t *hal_ops = hal_get_ops(hal);
410
411 if (hal_ops->restore_rx_interrupt)
412 hal_ops->restore_rx_interrupt(hal);
413 else
414 PHL_DBG("hal_ops->restore_rx_interrupt is NULL\n");
415 }
416
hal_ops_check(struct hal_info_t * hal)417 static enum rtw_hal_status hal_ops_check(struct hal_info_t *hal)
418 {
419 enum rtw_hal_status status = RTW_HAL_STATUS_SUCCESS;
420 struct hal_ops_t *ops = hal_get_ops(hal);
421 struct hal_trx_ops *trx_ops = hal_get_trx_ops(hal);
422
423 /***hal_ops initialize section ***/
424 if (!ops->init_hal_spec) {
425 hal_error_msg("init_hal_spec");
426 status = RTW_HAL_STATUS_FAILURE;
427 }
428
429 if (!ops->read_chip_version) {
430 hal_error_msg("read_chip_version");
431 status = RTW_HAL_STATUS_FAILURE;
432 }
433
434 if (!ops->hal_init) {
435 hal_error_msg("hal_init");
436 status = RTW_HAL_STATUS_FAILURE;
437 }
438 if (!ops->hal_deinit) {
439 hal_error_msg("hal_deinit");
440 status = RTW_HAL_STATUS_FAILURE;
441 }
442
443 if (!ops->hal_start) {
444 hal_error_msg("hal_start");
445 status = RTW_HAL_STATUS_FAILURE;
446 }
447 if (!ops->hal_stop) {
448 hal_error_msg("hal_stop");
449 status = RTW_HAL_STATUS_FAILURE;
450 }
451 #ifdef CONFIG_WOWLAN
452 if (!ops->hal_wow_init) {
453 hal_error_msg("hal_wow_init");
454 status = RTW_HAL_STATUS_FAILURE;
455 }
456 if (!ops->hal_wow_deinit) {
457 hal_error_msg("hal_wow_deinit");
458 status = RTW_HAL_STATUS_FAILURE;
459 }
460 #endif /* CONFIG_WOWLAN */
461 if (!ops->hal_mp_init) {
462 hal_error_msg("hal_mp_init");
463 status = RTW_HAL_STATUS_FAILURE;
464 }
465 if (!ops->hal_mp_deinit) {
466 hal_error_msg("hal_mp_deinit");
467 status = RTW_HAL_STATUS_FAILURE;
468 }
469
470 if (!ops->hal_cfg_fw) {
471 hal_error_msg("hal_cfg_fw");
472 status = RTW_HAL_STATUS_FAILURE;
473 }
474 if (!ops->init_default_value) {
475 hal_error_msg("init_default_value");
476 status = RTW_HAL_STATUS_FAILURE;
477 }
478 if (!ops->hal_hci_configure) {
479 hal_error_msg("hal_hci_configure");
480 status = RTW_HAL_STATUS_FAILURE;
481 }
482 if (!ops->read_macreg) {
483 hal_error_msg("read_macreg");
484 status = RTW_HAL_STATUS_FAILURE;
485 }
486 if (!ops->write_macreg) {
487 hal_error_msg("write_macreg");
488 status = RTW_HAL_STATUS_FAILURE;
489 }
490 if (!ops->read_bbreg) {
491 hal_error_msg("read_bbreg");
492 status = RTW_HAL_STATUS_FAILURE;
493 }
494 if (!ops->write_bbreg) {
495 hal_error_msg("write_bbreg");
496 status = RTW_HAL_STATUS_FAILURE;
497 }
498 if (!ops->read_rfreg) {
499 hal_error_msg("read_rfreg");
500 status = RTW_HAL_STATUS_FAILURE;
501 }
502 if (!ops->write_rfreg) {
503 hal_error_msg("write_rfreg");
504 status = RTW_HAL_STATUS_FAILURE;
505 }
506
507 #if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI)
508 if (!ops->enable_interrupt) {
509 hal_error_msg("enable_interrupt");
510 status = RTW_HAL_STATUS_FAILURE;
511 }
512 if (!ops->disable_interrupt) {
513 hal_error_msg("disable_interrupt");
514 status = RTW_HAL_STATUS_FAILURE;
515 }
516 #ifdef CONFIG_SDIO_HCI
517 if (!ops->config_interrupt) {
518 hal_error_msg("config_interrupt");
519 status = RTW_HAL_STATUS_FAILURE;
520 }
521 if (!ops->recognize_halt_c2h_interrupt) {
522 hal_error_msg("recognize_halt_c2h_interrupt");
523 status = RTW_HAL_STATUS_FAILURE;
524 }
525 #endif
526 if (!ops->recognize_interrupt) {
527 hal_error_msg("recognize_interrupt");
528 status = RTW_HAL_STATUS_FAILURE;
529 }
530 if (!ops->clear_interrupt) {
531 hal_error_msg("clear_interrupt");
532 status = RTW_HAL_STATUS_FAILURE;
533 }
534 if (!ops->interrupt_handler) {
535 hal_error_msg("interrupt_handler");
536 status = RTW_HAL_STATUS_FAILURE;
537 }
538 if (!ops->restore_interrupt) {
539 hal_error_msg("restore_interrupt");
540 status = RTW_HAL_STATUS_FAILURE;
541 }
542 #endif /*defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI)*/
543
544
545 /***hal_trx_ops section ***/
546 if (!trx_ops->init) {
547 hal_error_msg("trx init");
548 status = RTW_HAL_STATUS_FAILURE;
549 }
550 if (!trx_ops->deinit) {
551 hal_error_msg("trx deinit");
552 status = RTW_HAL_STATUS_FAILURE;
553 }
554 if (!trx_ops->map_hw_tx_chnl) {
555 hal_error_msg("trx map_hw_tx_chnl");
556 status = RTW_HAL_STATUS_FAILURE;
557 }
558 if (!trx_ops->get_fwcmd_queue_idx) {
559 hal_error_msg("trx get_fwcmd_queue_idx");
560 status = RTW_HAL_STATUS_FAILURE;
561 }
562 #ifdef CONFIG_PCI_HCI
563 if (!trx_ops->query_tx_res) {
564 hal_error_msg("trx query_tx_res");
565 status = RTW_HAL_STATUS_FAILURE;
566 }
567 if (!trx_ops->query_rx_res) {
568 hal_error_msg("trx query_rx_res");
569 status = RTW_HAL_STATUS_FAILURE;
570 }
571 if (!trx_ops->cfg_wow_txdma) {
572 hal_error_msg("trx cfg_wow_txdma");
573 status = RTW_HAL_STATUS_FAILURE;
574 }
575 if (!trx_ops->poll_txdma_idle) {
576 hal_error_msg("trx poll_txdma_idle");
577 status = RTW_HAL_STATUS_FAILURE;
578 }
579 if (!trx_ops->qsel_to_tid) {
580 hal_error_msg("trx qsel_to_tid");
581 status = RTW_HAL_STATUS_FAILURE;
582 }
583
584 if (!trx_ops->query_txch_num) {
585 hal_error_msg("trx query_txch_num");
586 status = RTW_HAL_STATUS_FAILURE;
587 }
588
589 if (!trx_ops->query_rxch_num) {
590 hal_error_msg("trx query_rxch_num");
591 status = RTW_HAL_STATUS_FAILURE;
592 }
593 if (!trx_ops->update_wd) {
594 hal_error_msg("trx update_wd");
595 status = RTW_HAL_STATUS_FAILURE;
596 }
597 if (!trx_ops->update_txbd) {
598 hal_error_msg("trx update_txbd");
599 status = RTW_HAL_STATUS_FAILURE;
600 }
601 if (!trx_ops->tx_start) {
602 hal_error_msg("trx tx_start");
603 status = RTW_HAL_STATUS_FAILURE;
604 }
605 if (!trx_ops->check_rxrdy) {
606 hal_error_msg("trx check_rxrdy");
607 status = RTW_HAL_STATUS_FAILURE;
608 }
609 if (!trx_ops->handle_rxbd_info) {
610 hal_error_msg("trx handle_rxbd_info");
611 status = RTW_HAL_STATUS_FAILURE;
612 }
613 if (!trx_ops->handle_rx_buffer) {
614 hal_error_msg("trx handle_rx_buffer");
615 status = RTW_HAL_STATUS_FAILURE;
616 }
617 if (!trx_ops->update_rxbd) {
618 hal_error_msg("trx update_rxbd");
619 status = RTW_HAL_STATUS_FAILURE;
620 }
621 if (!trx_ops->notify_rxdone) {
622 hal_error_msg("trx notify_rxdone");
623 status = RTW_HAL_STATUS_FAILURE;
624 }
625 if (!trx_ops->handle_wp_rpt) {
626 hal_error_msg("trx handle_wp_rpt");
627 status = RTW_HAL_STATUS_FAILURE;
628 }
629 #endif /*CONFIG_PCIE_HCI*/
630
631 #ifdef CONFIG_USB_HCI
632 if (!trx_ops->hal_fill_wd) {
633 hal_error_msg("trx hal_fill_wd");
634 status = RTW_HAL_STATUS_FAILURE;
635 }
636 if (!trx_ops->get_bulkout_id) {
637 hal_error_msg("trx get_bulkout_id");
638 status = RTW_HAL_STATUS_FAILURE;
639 }
640 if (!trx_ops->handle_rx_buffer) {
641 hal_error_msg("trx handle_rx_buffer");
642 status = RTW_HAL_STATUS_FAILURE;
643 }
644 if (!trx_ops->usb_tx_agg_cfg) {
645 hal_error_msg("trx usb_tx_agg_cfg");
646 status = RTW_HAL_STATUS_FAILURE;
647 }
648 if (!trx_ops->usb_rx_agg_cfg) {
649 hal_error_msg("trx usb_rx_agg_cfg");
650 status = RTW_HAL_STATUS_FAILURE;
651 }
652 if (!trx_ops->handle_wp_rpt) {
653 hal_error_msg("trx handle_wp_rpt");
654 status = RTW_HAL_STATUS_FAILURE;
655 }
656 #endif
657
658 #ifdef CONFIG_SDIO_HCI
659
660 #endif
661 return status;
662 }
hal_set_ops(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal_info)663 static enum rtw_hal_status hal_set_ops(struct rtw_phl_com_t *phl_com,
664 struct hal_info_t *hal_info)
665 {
666 #ifdef CONFIG_PCI_HCI
667 if (phl_get_hci_type(phl_com) == RTW_HCI_PCIE)
668 hal_set_ops_pci(phl_com, hal_info);
669 #endif
670
671 #ifdef CONFIG_USB_HCI
672 if (phl_get_hci_type(phl_com) == RTW_HCI_USB)
673 hal_set_ops_usb(phl_com, hal_info);
674 #endif
675
676 #ifdef CONFIG_SDIO_HCI
677 if (phl_get_hci_type(phl_com) == RTW_HCI_SDIO)
678 hal_set_ops_sdio(phl_com, hal_info);
679 #endif
680
681 return hal_ops_check(hal_info);
682 }
683
684 #ifdef RTW_PHL_BCN
hal_bcn_init(struct hal_info_t * hal_info)685 enum rtw_hal_status hal_bcn_init(struct hal_info_t *hal_info)
686 {
687 struct bcn_entry_pool *bcn_pool = &hal_info->hal_com->bcn_pool;
688
689 hal_info->hal_com->bcn_pool.bcn_num = 0;
690 INIT_LIST_HEAD(&bcn_pool->bcn_list);
691 _os_spinlock_init(hal_to_drvpriv(hal_info), &hal_info->hal_com->bcn_pool.bcn_lock);
692
693 return RTW_HAL_STATUS_SUCCESS;
694 }
695
hal_bcn_deinit(struct hal_info_t * hal_info)696 enum rtw_hal_status hal_bcn_deinit(struct hal_info_t *hal_info)
697 {
698 void *drv_priv = hal_to_drvpriv(hal_info);
699 struct bcn_entry_pool *bcn_pool = &hal_info->hal_com->bcn_pool;
700 struct rtw_bcn_entry *tmp_entry, *type = NULL;
701
702 _os_spinlock(drv_priv, &bcn_pool->bcn_lock, _ps, NULL);
703
704 phl_list_for_loop_safe(tmp_entry, type,
705 struct rtw_bcn_entry, &bcn_pool->bcn_list, list)
706 {
707 list_del(&tmp_entry->list);
708 _os_mem_free(drv_priv, tmp_entry, sizeof(struct rtw_bcn_entry));
709 }
710
711 _os_spinunlock(drv_priv, &bcn_pool->bcn_lock, _ps, NULL);
712
713 return RTW_HAL_STATUS_SUCCESS;
714 }
715
hal_alloc_bcn_entry(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal_info,struct rtw_bcn_entry ** bcn_entry,struct rtw_bcn_info_cmn * bcn_cmn)716 enum rtw_hal_status hal_alloc_bcn_entry(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info,
717 struct rtw_bcn_entry **bcn_entry, struct rtw_bcn_info_cmn *bcn_cmn)
718 {
719 void *drv_priv = hal_to_drvpriv(hal_info);
720 struct bcn_entry_pool *bcn_pool = &hal_info->hal_com->bcn_pool;
721 struct rtw_bcn_entry *new_entry = _os_mem_alloc(drv_priv, sizeof(struct rtw_bcn_entry));
722
723 if(new_entry == NULL)
724 return RTW_HAL_STATUS_FAILURE;
725
726 _os_spinlock(drv_priv, &bcn_pool->bcn_lock, _ps, NULL);
727
728 list_add_tail(&new_entry->list, &bcn_pool->bcn_list);
729 bcn_pool->bcn_num ++;
730
731 _os_spinunlock(drv_priv, &bcn_pool->bcn_lock, _ps, NULL);
732
733 *bcn_entry = new_entry;
734
735 return RTW_HAL_STATUS_SUCCESS;
736 }
737
hal_free_bcn_entry(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal_info,u8 bcn_id)738 enum rtw_hal_status hal_free_bcn_entry(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info,
739 u8 bcn_id)
740 {
741 void *drv_priv = hal_to_drvpriv(hal_info);
742 struct bcn_entry_pool *bcn_pool = &hal_info->hal_com->bcn_pool;
743 struct rtw_bcn_entry *tmp_entry, *type = NULL;
744 u8 is_found = 0;
745
746 _os_spinlock(drv_priv, &bcn_pool->bcn_lock, _ps, NULL);
747
748 phl_list_for_loop_safe(tmp_entry, type,
749 struct rtw_bcn_entry, &bcn_pool->bcn_list, list)
750 {
751 if(tmp_entry->bcn_cmn->bcn_id == bcn_id){
752 is_found = 1;
753 break;
754 }
755 }
756
757 _os_spinunlock(drv_priv, &bcn_pool->bcn_lock, _ps, NULL);
758
759 if(is_found){
760 list_del(&tmp_entry->list);
761 _os_mem_free(drv_priv, tmp_entry, sizeof(struct rtw_bcn_entry));
762 bcn_pool->bcn_num --;
763 return RTW_HAL_STATUS_SUCCESS;
764 }
765 else
766 return RTW_HAL_STATUS_FAILURE;
767 }
768
hal_get_bcn_entry(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal_info,struct rtw_bcn_entry ** bcn_entry,u8 bcn_id)769 enum rtw_hal_status hal_get_bcn_entry(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info,
770 struct rtw_bcn_entry **bcn_entry, u8 bcn_id)
771 {
772 void *drv_priv = hal_to_drvpriv(hal_info);
773 struct bcn_entry_pool *bcn_pool = &hal_info->hal_com->bcn_pool;
774 struct rtw_bcn_entry *tmp_entry, *type = NULL;
775 u8 is_found = 0;
776
777 _os_spinlock(drv_priv, &bcn_pool->bcn_lock, _ps, NULL);
778
779 phl_list_for_loop_safe(tmp_entry, type,
780 struct rtw_bcn_entry, &bcn_pool->bcn_list, list)
781 {
782 if(tmp_entry->bcn_cmn->bcn_id == bcn_id){
783 is_found = 1;
784 break;
785 }
786 }
787
788 _os_spinunlock(drv_priv, &bcn_pool->bcn_lock, _ps, NULL);
789
790 if(is_found){
791 *bcn_entry = tmp_entry;
792 return RTW_HAL_STATUS_SUCCESS;
793 }
794 else
795 return RTW_HAL_STATUS_FAILURE;
796 }
797
hal_update_bcn_entry(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal_info,struct rtw_bcn_entry * bcn_entry,struct rtw_bcn_info_cmn * bcn_cmn)798 enum rtw_hal_status hal_update_bcn_entry(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info,
799 struct rtw_bcn_entry *bcn_entry, struct rtw_bcn_info_cmn *bcn_cmn)
800 {
801 struct rtw_wifi_role_t *wrole = &phl_com->wifi_roles[bcn_cmn->role_idx];
802 struct rtw_phl_stainfo_t *phl_sta = rtw_phl_get_stainfo_self(phl_com->phl_priv, wrole);
803
804 bcn_entry->bcn_cmn = bcn_cmn;
805
806 bcn_entry->bcn_hw.band = wrole->hw_band;
807 bcn_entry->bcn_hw.port = wrole->hw_port;
808 bcn_entry->bcn_hw.mbssid = wrole->hw_mbssid;
809 bcn_entry->bcn_hw.mac_id = (u8)phl_sta->macid;
810
811 return RTW_HAL_STATUS_SUCCESS;
812 }
813
rtw_hal_add_beacon(struct rtw_phl_com_t * phl_com,void * hal,void * bcn_cmn)814 enum rtw_hal_status rtw_hal_add_beacon(struct rtw_phl_com_t *phl_com, void *hal,
815 void *bcn_cmn)
816 {
817 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
818 struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
819 struct rtw_bcn_entry *bcn_entry = NULL;
820
821 if(hal_alloc_bcn_entry(phl_com, hal_info, &bcn_entry, (struct rtw_bcn_info_cmn *)bcn_cmn) == RTW_HAL_STATUS_FAILURE)
822 return RTW_HAL_STATUS_FAILURE;
823
824 if(hal_update_bcn_entry(phl_com, hal_info, bcn_entry, (struct rtw_bcn_info_cmn *)bcn_cmn) == RTW_HAL_STATUS_FAILURE)
825 return RTW_HAL_STATUS_FAILURE;
826
827 if(hal_ops->cfg_bcn(phl_com, hal_info, bcn_entry) == RTW_HAL_STATUS_FAILURE)
828 return RTW_HAL_STATUS_FAILURE;
829
830 if(hal_ops->upt_bcn(phl_com, hal_info, bcn_entry) == RTW_HAL_STATUS_FAILURE)
831 return RTW_HAL_STATUS_FAILURE;
832
833 return RTW_HAL_STATUS_SUCCESS;
834 }
835
rtw_hal_update_beacon(struct rtw_phl_com_t * phl_com,void * hal,u8 bcn_id)836 enum rtw_hal_status rtw_hal_update_beacon(struct rtw_phl_com_t *phl_com, void *hal,
837 u8 bcn_id)
838 {
839 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
840 struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
841 struct rtw_bcn_entry *bcn_entry = NULL;
842
843 if(hal_get_bcn_entry(phl_com, hal_info, &bcn_entry, bcn_id) == RTW_HAL_STATUS_FAILURE)
844 return RTW_HAL_STATUS_FAILURE;
845
846 if(hal_ops->upt_bcn(phl_com, hal_info, bcn_entry) == RTW_HAL_STATUS_FAILURE)
847 return RTW_HAL_STATUS_FAILURE;
848
849 return RTW_HAL_STATUS_SUCCESS;
850 }
851
rtw_hal_free_beacon(struct rtw_phl_com_t * phl_com,void * hal,u8 bcn_id)852 enum rtw_hal_status rtw_hal_free_beacon(struct rtw_phl_com_t *phl_com, void *hal,
853 u8 bcn_id)
854 {
855 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
856
857 if(hal_free_bcn_entry(phl_com, hal_info, bcn_id) == RTW_HAL_STATUS_FAILURE)
858 return RTW_HAL_STATUS_FAILURE;
859
860 return RTW_HAL_STATUS_SUCCESS;
861 }
862 #endif
863
rtw_hal_pkt_ofld(void * hal,u8 * id,u8 op,u8 * pkt_buf,u16 * pkt_len)864 enum rtw_hal_status rtw_hal_pkt_ofld(void *hal, u8 *id, u8 op,
865 u8 *pkt_buf, u16 *pkt_len)
866 {
867 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
868 struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
869
870 return hal_ops->pkt_ofld(hal, id, op, pkt_buf, pkt_len);
871 }
872
rtw_hal_pkt_update_ids(void * hal,struct pkt_ofld_entry * entry)873 enum rtw_hal_status rtw_hal_pkt_update_ids(void *hal,
874 struct pkt_ofld_entry *entry)
875 {
876 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
877 struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
878
879 return hal_ops->pkt_update_ids(hal, entry);
880 }
881
rtw_hal_get_pwr_state(void * hal,enum rtw_mac_pwr_st * pwr_state)882 enum rtw_hal_status rtw_hal_get_pwr_state(void *hal, enum rtw_mac_pwr_st *pwr_state)
883 {
884 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
885
886 return rtw_hal_mac_get_pwr_state(hal_info, pwr_state);
887 }
888
rtw_hal_init(void * drv_priv,struct rtw_phl_com_t * phl_com,void ** hal,enum rtl_ic_id ic_id)889 enum rtw_hal_status rtw_hal_init(void *drv_priv,
890 struct rtw_phl_com_t *phl_com, void **hal, enum rtl_ic_id ic_id)
891 {
892 struct hal_info_t *hal_info = NULL;
893 struct rtw_hal_com_t *hal_com = NULL;
894 enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
895 void (*set_intf_ops)(struct rtw_hal_com_t *hal, struct hal_io_ops *ops) = NULL;
896 enum rtw_chip_id chip_id = CHIP_WIFI6_MAX;
897
898 if (ic_id == RTL8852A)
899 chip_id = CHIP_WIFI6_8852A;
900 else if(ic_id == RTL8834A)
901 chip_id = CHIP_WIFI6_8834A;
902 else if(ic_id == RTL8852B)
903 chip_id = CHIP_WIFI6_8852B;
904 else if(ic_id == RTL8852C)
905 chip_id = CHIP_WIFI6_8852C;
906 else
907 return RTW_HAL_STATUS_FAILURE;
908
909 hal_info = _os_mem_alloc(drv_priv, sizeof(struct hal_info_t));
910 if (hal_info == NULL) {
911 hal_status = RTW_HAL_STATUS_RESOURCE;
912 PHL_ERR("alloc hal_info failed\n");
913 goto error_hal_mem;
914 }
915 *hal = hal_info;
916
917 hal_com = _os_mem_alloc(drv_priv, sizeof(struct rtw_hal_com_t));
918 if (hal_com == NULL) {
919 hal_status = RTW_HAL_STATUS_RESOURCE;
920 PHL_ERR("alloc hal_com failed\n");
921 goto error_hal_com_mem;
922 }
923
924 hal_info->hal_com = hal_com;
925 hal_com->drv_priv = drv_priv;
926 hal_com->hal_priv = hal_info;
927 hal_com->chip_id = chip_id;
928 hal_com->dbcc_en = false;
929 #ifdef DBG_HAL_MEM_MOINTOR
930 _os_atomic_set(drv_priv, &(hal_com->hal_mem), 0);
931 #endif
932
933 /*set io_ops*/
934 #ifdef CONFIG_PCI_HCI
935 if (phl_com->hci_type == RTW_HCI_PCIE)
936 set_intf_ops = hal_pci_set_io_ops;
937 #endif
938
939 #ifdef CONFIG_USB_HCI
940 if (phl_com->hci_type == RTW_HCI_USB)
941 set_intf_ops = hal_usb_set_io_ops;
942 #endif
943
944 #ifdef CONFIG_SDIO_HCI
945 if (phl_com->hci_type == RTW_HCI_SDIO)
946 set_intf_ops = hal_sdio_set_io_ops;
947 #endif
948
949 hal_status = hal_init_io_priv(hal_info->hal_com, set_intf_ops);
950 if (hal_status != RTW_HAL_STATUS_SUCCESS) {
951 PHL_ERR("hal_init_io_priv failed\n");
952 goto error_io_priv;
953 }
954
955 /*set hal_ops and hal_hook_trx_ops*/
956 hal_status = hal_set_ops(phl_com, hal_info);
957 if (hal_status != RTW_HAL_STATUS_SUCCESS) {
958 PHL_ERR("hal_set_ops failed\n");
959 goto error_hal_ops;
960 }
961
962 hal_status = hal_info->hal_ops.hal_init(phl_com, hal_info);
963 if (hal_status != RTW_HAL_STATUS_SUCCESS) {
964 PHL_ERR("hal_ops.hal_init failed\n");
965 goto error_hal_init;
966 }
967
968 hal_status = rtw_hal_mac_init(phl_com, hal_info);
969 if ((hal_status != RTW_HAL_STATUS_SUCCESS) || (hal_info->mac == NULL)) {
970 PHL_ERR("rtw_hal_mac_init failed\n");
971 goto error_mac_init;
972 }
973
974 hal_status = rtw_hal_efuse_init(phl_com, hal_info);
975 if (hal_status != RTW_HAL_STATUS_SUCCESS) {
976 PHL_ERR("rtw_hal_efuse_init failed\n");
977 goto error_efuse_init;
978 }
979
980 hal_status = rtw_hal_bb_init(phl_com, hal_info);
981 if (hal_status != RTW_HAL_STATUS_SUCCESS) {
982 PHL_ERR("rtw_hal_bb_init failed\n");
983 goto error_bb_init;
984 }
985
986 hal_status = rtw_hal_rf_init(phl_com, hal_info);
987 if (hal_status != RTW_HAL_STATUS_SUCCESS) {
988 PHL_ERR("rtw_hal_rf_init failed\n");
989 goto error_rf_init;
990 }
991
992 hal_status = rtw_hal_btc_init(phl_com, hal_info);
993 if (hal_status != RTW_HAL_STATUS_SUCCESS){
994 PHL_ERR("rtw_hal_btc_init failed\n");
995 goto error_btc_init;
996 }
997
998 #ifdef RTW_PHL_BCN
999 hal_status = hal_bcn_init(hal_info);
1000 if (hal_status != RTW_HAL_STATUS_SUCCESS){
1001 PHL_ERR("hal_bcn_init failed\n");
1002 goto error_bcn_init;
1003 }
1004 #endif
1005
1006 return RTW_HAL_STATUS_SUCCESS;
1007
1008 #ifdef RTW_PHL_BCN
1009 error_bcn_init:
1010 rtw_hal_btc_deinit(phl_com, hal_info);
1011 #endif
1012
1013 error_btc_init:
1014 rtw_hal_rf_deinit(phl_com, hal_info);
1015
1016 error_rf_init:
1017 rtw_hal_bb_deinit(phl_com, hal_info);
1018
1019 error_bb_init:
1020 rtw_hal_efuse_deinit(phl_com, hal_info);
1021
1022 error_efuse_init:
1023 rtw_hal_mac_deinit(phl_com, hal_info);
1024
1025 error_mac_init:
1026 hal_info->hal_ops.hal_deinit(phl_com, hal_info);
1027
1028 error_hal_init:
1029 error_hal_ops:
1030 hal_deinit_io_priv(hal_com);
1031
1032 error_io_priv:
1033 if (hal_com) {
1034 _os_mem_free(drv_priv, hal_com, sizeof(struct rtw_hal_com_t));
1035 hal_com = NULL;
1036 }
1037
1038 error_hal_com_mem:
1039 if (hal_info) {
1040 _os_mem_free(drv_priv, hal_info, sizeof(struct hal_info_t));
1041 *hal = hal_info = NULL;
1042 }
1043
1044 error_hal_mem:
1045 return hal_status;
1046 }
rtw_hal_get_halcom(void * hal)1047 struct rtw_hal_com_t *rtw_hal_get_halcom(void *hal)
1048 {
1049 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
1050
1051 return hal_info->hal_com;
1052 }
1053
rtw_hal_deinit(struct rtw_phl_com_t * phl_com,void * hal)1054 void rtw_hal_deinit(struct rtw_phl_com_t *phl_com, void *hal)
1055 {
1056 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
1057 void *drv_priv = hal_to_drvpriv(hal_info);
1058
1059 if(hal_info == NULL)
1060 return;
1061
1062 /* stop mechanism / disassociate hal ops */
1063 #ifdef RTW_PHL_BCN
1064 hal_bcn_deinit(hal_info);
1065 #endif
1066 rtw_hal_btc_deinit(phl_com, hal_info);
1067 rtw_hal_rf_deinit(phl_com, hal_info);
1068 rtw_hal_bb_deinit(phl_com, hal_info);
1069 rtw_hal_efuse_deinit(phl_com, hal_info);
1070 rtw_hal_mac_deinit(phl_com, hal_info);
1071 hal_info->hal_ops.hal_deinit(phl_com, hal_info);
1072 hal_deinit_io_priv(hal_info->hal_com);
1073
1074 #ifdef DBG_HAL_MEM_MOINTOR
1075 PHL_INFO("[PHL-MEM] %s HAL memory :%d\n", __func__,
1076 _os_atomic_read(hal_to_drvpriv(hal_info), &(hal_info->hal_com->hal_mem)));
1077 #endif
1078
1079 if (hal_info->hal_com) {
1080 if(hal_info->hal_com->bf_obj)
1081 hal_bf_deinit(hal_info);
1082 if(hal_info->hal_com->csi_obj)
1083 hal_csi_deinit(hal_info);
1084 if(hal_info->hal_com->snd_obj)
1085 hal_snd_obj_deinit(hal_info);
1086 _os_mem_free(drv_priv,
1087 hal_info->hal_com, sizeof(struct rtw_hal_com_t));
1088 hal_info->hal_com = NULL;
1089 }
1090 if (hal_info) {
1091 _os_mem_free(drv_priv,
1092 hal_info, sizeof(struct hal_info_t));
1093 hal_info = NULL;
1094 }
1095 }
1096
rtw_hal_is_inited(struct rtw_phl_com_t * phl_com,void * hal)1097 bool rtw_hal_is_inited(struct rtw_phl_com_t *phl_com, void *hal)
1098 {
1099 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
1100
1101 return hal_info->hal_com->is_hal_init;
1102 }
1103
rtw_hal_hci_cfg(struct rtw_phl_com_t * phl_com,void * hal,struct rtw_ic_info * ic_info)1104 u32 rtw_hal_hci_cfg(struct rtw_phl_com_t *phl_com, void *hal,
1105 struct rtw_ic_info *ic_info)
1106 {
1107 enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
1108 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
1109 struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
1110
1111 #ifdef CONFIG_SDIO_HCI
1112 hal_info->hal_com->block_sz = ic_info->sdio_info.block_sz;
1113 #endif
1114 hal_ops->hal_hci_configure(phl_com, hal_info, ic_info);
1115
1116 return hal_status;
1117 }
1118
rtw_hal_read_chip_info(struct rtw_phl_com_t * phl_com,void * hal)1119 u32 rtw_hal_read_chip_info(struct rtw_phl_com_t *phl_com, void *hal)
1120 {
1121 enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
1122 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
1123 struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
1124
1125 hal_ops->read_chip_version(phl_com, hal_info);
1126
1127 /*get mac,bb,rf capability*/
1128 hal_ops->init_hal_spec(phl_com, hal_info);
1129
1130 return hal_status;
1131 }
1132
_hal_reset_chandef(struct rtw_hal_com_t * hal_com)1133 static void _hal_reset_chandef(struct rtw_hal_com_t *hal_com)
1134 {
1135 struct rtw_chan_def *chandef = NULL;
1136 u8 bid = 0;
1137
1138 for (bid = 0; bid < HW_BAND_MAX; bid++) {
1139 chandef = &(hal_com->band[bid].cur_chandef);
1140 chandef->bw = CHANNEL_WIDTH_MAX;
1141 chandef->chan = 0;
1142 chandef->offset = CHAN_OFFSET_NO_EXT;
1143 }
1144 }
1145
rtw_hal_set_default_var(void * hal,enum rtw_hal_set_def_var_rsn rsn)1146 void rtw_hal_set_default_var(void *hal, enum rtw_hal_set_def_var_rsn rsn)
1147 {
1148 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
1149 struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
1150 struct hal_intr_mask_cfg intr_cfg = {0};
1151
1152 switch (rsn) {
1153 case SET_DEF_RSN_HAL_INIT:
1154 intr_cfg.halt_c2h_en = 1;
1155 intr_cfg.wdt_en = 1;
1156 hal_info->hal_com->assoc_sta_cnt = 0;
1157 _hal_reset_chandef(hal_info->hal_com);
1158 break;
1159 case SET_DEF_RSN_WOW_RESUME_HNDL_RX:
1160 intr_cfg.halt_c2h_en = 0;
1161 intr_cfg.wdt_en = 1;
1162 break;
1163 case SET_DEF_RSN_WOW_RESUME_DONE:
1164 intr_cfg.halt_c2h_en = 1;
1165 intr_cfg.wdt_en = 1;
1166 break;
1167 default:
1168 intr_cfg.halt_c2h_en = 1;
1169 intr_cfg.wdt_en = 1;
1170 hal_info->hal_com->assoc_sta_cnt = 0;
1171 _hal_reset_chandef(hal_info->hal_com);
1172 break;
1173 }
1174
1175 PHL_INFO("%s : rsn %d.\n", __func__, rsn);
1176 hal_ops->init_default_value(hal_info, &intr_cfg);
1177 }
1178
rtw_hal_var_init(struct rtw_phl_com_t * phl_com,void * hal)1179 u32 rtw_hal_var_init(struct rtw_phl_com_t *phl_com, void *hal)
1180 {
1181 enum rtw_hal_status hal_status = RTW_HAL_STATUS_SUCCESS;
1182 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
1183 struct rtw_hal_com_t *hal_com = hal_info->hal_com;
1184
1185 hal_com->is_hal_init = false;
1186 rtw_hal_set_default_var(hal_info, SET_DEF_RSN_HAL_INIT);
1187
1188 /*csi init shall after read hw chip info*/
1189 hal_status = hal_csi_init(
1190 hal_info,
1191 phl_com->hal_spec.max_csi_buf_su_nr,
1192 phl_com->hal_spec.max_csi_buf_mu_nr);
1193 if (hal_status != RTW_HAL_STATUS_SUCCESS){
1194 PHL_ERR("rtw_hal_csi_init failed\n");
1195 }
1196
1197 /*bf init shall after read hw chip info*/
1198 hal_status = hal_bf_init(
1199 hal_info,
1200 phl_com->hal_spec.max_bf_ent_nr,
1201 phl_com->hal_spec.max_su_sta_nr,
1202 phl_com->hal_spec.max_mu_sta_nr);
1203 if (hal_status != RTW_HAL_STATUS_SUCCESS){
1204 PHL_ERR("rtw_hal_bf_init failed\n");
1205 }
1206
1207 hal_status = hal_snd_obj_init(hal_info);
1208 if (hal_status != RTW_HAL_STATUS_SUCCESS){
1209 PHL_ERR("hal_snd_obj_init failed\n");
1210 }
1211 return hal_status;
1212 }
1213
1214 static int
_hal_parse_macreg(void * drv_priv,u32 * pdest_buf,u8 * psrc_buf,u32 buflen)1215 _hal_parse_macreg(void *drv_priv, u32 *pdest_buf, u8 *psrc_buf, u32 buflen)
1216 {
1217 return 0;
1218 }
1219
_get_path_from_ant_num(u8 antnum)1220 enum rf_path _get_path_from_ant_num(u8 antnum)
1221 {
1222 enum rf_path ret = RF_PATH_B;
1223
1224 switch (antnum) {
1225 default:
1226 break;
1227 case 1:
1228 ret = RF_PATH_B;
1229 break;
1230 case 2:
1231 ret = RF_PATH_AB;
1232 break;
1233 case 3:
1234 ret = RF_PATH_ABC;
1235 break;
1236 }
1237 return ret;
1238 }
1239
_hal_send_hal_init_hub_msg(struct rtw_phl_com_t * phl_com,u8 init_ok)1240 static void _hal_send_hal_init_hub_msg(struct rtw_phl_com_t *phl_com, u8 init_ok)
1241 {
1242 struct phl_msg msg = {0};
1243 u16 evt_id = (init_ok) ? MSG_EVT_HAL_INIT_OK : MSG_EVT_HAL_INIT_FAIL;
1244
1245 msg.inbuf = NULL;
1246 msg.inlen = 0;
1247 SET_MSG_MDL_ID_FIELD(msg.msg_id, PHL_MDL_PHY_MGNT);
1248 SET_MSG_EVT_ID_FIELD(msg.msg_id, evt_id);
1249 msg.band_idx = HW_BAND_0;
1250 rtw_phl_msg_hub_hal_send(phl_com, NULL, &msg);
1251 }
1252
rtw_hal_preload(struct rtw_phl_com_t * phl_com,void * hal)1253 enum rtw_hal_status rtw_hal_preload(struct rtw_phl_com_t *phl_com, void *hal)
1254 {
1255 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
1256 enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
1257 struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
1258
1259 FUNCIN();
1260
1261 hal_status = hal_ops->hal_get_efuse(phl_com, hal_info);
1262 if (hal_status != RTW_HAL_STATUS_SUCCESS)
1263 return hal_status;
1264
1265 return hal_status;
1266 }
1267
hal_rfe_type_chk(struct rtw_phl_com_t * phl_com,struct hal_info_t * hal_info)1268 enum rtw_hal_status hal_rfe_type_chk(struct rtw_phl_com_t *phl_com,
1269 struct hal_info_t *hal_info)
1270 {
1271 enum rtw_hal_status hal_status = RTW_HAL_STATUS_UNKNOWN_RFE_TYPE;
1272
1273 if(phl_com->dev_cap.rfe_type != 0xff){
1274 hal_status = RTW_HAL_STATUS_SUCCESS;
1275 }
1276 else {
1277 if(phl_com->dev_cap.bypass_rfe_chk == true){
1278 rtw_hal_rf_get_default_rfe_type(hal_info->hal_com);
1279 rtw_hal_rf_get_default_xtal(hal_info->hal_com);
1280 PHL_WARN("%s: Use default RFE type(0x%x) / XTAL(0x%x) configuration for empty EFUSE\n",
1281 __FUNCTION__,
1282 hal_info->hal_com->dev_hw_cap.rfe_type,
1283 hal_info->hal_com->dev_hw_cap.xcap);
1284 hal_status = RTW_HAL_STATUS_SUCCESS;
1285 }
1286 }
1287
1288 return hal_status;
1289 }
1290
rtw_hal_start(struct rtw_phl_com_t * phl_com,void * hal)1291 enum rtw_hal_status rtw_hal_start(struct rtw_phl_com_t *phl_com, void *hal)
1292 {
1293 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
1294 enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
1295 struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
1296 #ifdef RTW_WKARD_DEF_CMACTBL_CFG
1297 enum rf_path tx, rx;
1298 #endif
1299 hal_status = hal_rfe_type_chk(phl_com, hal_info);
1300 if(hal_status != RTW_HAL_STATUS_SUCCESS){
1301 PHL_ERR("%s: Unknown RFE type!!!\n", __FUNCTION__);
1302 return hal_status;
1303 }
1304
1305 hal_status = hal_ops->hal_start(phl_com, hal_info);
1306 if (hal_status != RTW_HAL_STATUS_SUCCESS)
1307 return hal_status;
1308
1309 hal_status = RTW_HAL_STATUS_SUCCESS;
1310 hal_info->hal_com->is_hal_init = true;
1311 rtw_hal_set_default_var(hal_info, SET_DEF_RSN_HAL_INIT);
1312
1313 rtw_hal_rf_set_power(hal_info, HW_PHY_0, PWR_BY_RATE);
1314 #ifdef RTW_WKARD_DEF_CMACTBL_CFG
1315 if (phl_com->phy_cap[0].txss < hal_info->hal_com->rfpath_tx_num)
1316 hal_info->hal_com->rfpath_tx_num = phl_com->phy_cap[0].txss;
1317 if (phl_com->phy_cap[0].rxss < hal_info->hal_com->rfpath_rx_num)
1318 hal_info->hal_com->rfpath_rx_num = phl_com->phy_cap[0].rxss;
1319 tx = _get_path_from_ant_num(hal_info->hal_com->rfpath_tx_num);
1320 rx = _get_path_from_ant_num(hal_info->hal_com->rfpath_rx_num);
1321 rtw_hal_bb_trx_path_cfg(hal_info, tx, phl_com->phy_cap[0].txss,
1322 rx, phl_com->phy_cap[0].rxss);
1323 #endif
1324 #ifdef RTW_WKARD_SINGLE_PATH_RSSI
1325 hal_info->hal_com->cur_rx_rfpath =
1326 _get_path_from_ant_num(hal_info->hal_com->rfpath_rx_num);
1327 #endif
1328 #ifdef CONFIG_BTCOEX
1329 rtw_hal_btc_radio_state_ntfy(hal_info, true);
1330 #endif
1331
1332 return hal_status;
1333 }
1334
rtw_hal_stop(struct rtw_phl_com_t * phl_com,void * hal)1335 void rtw_hal_stop(struct rtw_phl_com_t *phl_com, void *hal)
1336 {
1337 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
1338 enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
1339 struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
1340
1341 do {
1342 if (true == TEST_STATUS_FLAG(phl_com->dev_state,
1343 RTW_DEV_SURPRISE_REMOVAL)) {
1344 PHL_WARN("%s(): Device has removed, skip HW stop functions!\n", __func__);
1345 break;
1346 }
1347
1348 #ifdef CONFIG_BTCOEX
1349 rtw_hal_btc_radio_state_ntfy(hal_info, false);
1350 #endif
1351 hal_status = hal_ops->hal_stop(phl_com, hal_info);
1352 hal_info->hal_com->is_hal_init = false;
1353 } while (false);
1354 }
1355
rtw_hal_restart(struct rtw_phl_com_t * phl_com,void * hal)1356 enum rtw_hal_status rtw_hal_restart(struct rtw_phl_com_t *phl_com, void *hal)
1357 {
1358 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
1359 enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
1360 struct hal_ops_t *hal_ops = hal_get_ops(hal_info);
1361
1362 #ifdef CONFIG_BTCOEX
1363 rtw_hal_btc_radio_state_ntfy(hal_info, false);
1364 #endif
1365
1366 hal_status = hal_ops->hal_stop(phl_com, hal_info);
1367 if (hal_status != RTW_HAL_STATUS_SUCCESS)
1368 return hal_status;
1369
1370 hal_status = hal_ops->hal_start(phl_com, hal_info);
1371 if (hal_status != RTW_HAL_STATUS_SUCCESS)
1372 return hal_status;
1373
1374 #ifdef CONFIG_BTCOEX
1375 rtw_hal_btc_radio_state_ntfy(hal_info, true);
1376 #endif
1377
1378 hal_info->hal_com->is_hal_init = true;
1379
1380 return hal_status;
1381 }
1382
rtw_hal_hal_deinit(struct rtw_phl_com_t * phl_com,void * hal)1383 enum rtw_hal_status rtw_hal_hal_deinit(struct rtw_phl_com_t *phl_com, void *hal)
1384 {
1385 enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
1386 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
1387
1388 hstatus = rtw_hal_mac_hal_deinit(phl_com, hal_info);
1389
1390 return hstatus;
1391 }
1392
1393 enum rtw_hal_status
rtw_hal_role_cfg(void * hal,struct rtw_wifi_role_t * wrole)1394 rtw_hal_role_cfg(void *hal, struct rtw_wifi_role_t *wrole)
1395 {
1396 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
1397 enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
1398
1399 /*enable & configure mac hw-port*/
1400 hal_status = rtw_hal_mac_port_init(hal_info, wrole);
1401
1402 /* init hal mac bfer function if wrole cap if any of bfer cap is true*/
1403 if (wrole->proto_role_cap.he_su_bfmr ||
1404 wrole->proto_role_cap.he_mu_bfmr ||
1405 wrole->proto_role_cap.vht_su_bfmr ||
1406 wrole->proto_role_cap.vht_mu_bfmr ||
1407 wrole->proto_role_cap.ht_su_bfmr) {
1408 if ((PHL_RTYPE_AP == wrole->type) ||
1409 ((PHL_RTYPE_STATION == wrole->type) &&
1410 (MLME_LINKED == wrole->mstate))) {
1411 hal_status = hal_bf_hw_mac_init_bfer(hal_info,
1412 wrole->hw_band);
1413 }
1414 }
1415
1416 return hal_status;
1417 }
1418
1419 enum rtw_hal_status
rtw_hal_role_cfg_ex(void * hal,struct rtw_wifi_role_t * wrole,enum pcfg_type type,void * param)1420 rtw_hal_role_cfg_ex(void *hal, struct rtw_wifi_role_t *wrole,
1421 enum pcfg_type type, void *param)
1422 {
1423 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
1424 enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
1425
1426 hal_status = rtw_hal_mac_port_cfg(hal_info, wrole, type, param);
1427
1428 return hal_status;
1429 }
1430
1431 enum rtw_hal_status
rtw_hal_beacon_stop(void * hal,struct rtw_wifi_role_t * wrole,bool stop)1432 rtw_hal_beacon_stop(void *hal, struct rtw_wifi_role_t *wrole, bool stop)
1433 {
1434 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
1435 enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE;
1436 u32 bcn_en = (stop) ? 0 : 1;
1437
1438 PHL_INFO("%s wr-%d, bcn_en:%s\n", __func__, wrole->id, (bcn_en) ? "E" : "D");
1439 hsts = rtw_hal_mac_port_cfg(hal_info, wrole, PCFG_BCN_EN, &bcn_en);
1440
1441 return hsts;
1442 }
1443
1444 enum rtw_hal_status
hal_ver_check(struct rtw_hal_com_t * hal_com)1445 hal_ver_check(struct rtw_hal_com_t *hal_com)
1446 {
1447 if ((hal_com->mac_vc.mac_ver < hal_com->bb_vc.mac_ver) ||
1448 (hal_com->mac_vc.mac_ver < hal_com->rf_vc.mac_ver) ||
1449 (hal_com->mac_vc.mac_ver < hal_com->btc_vc.mac_ver) ||
1450 (hal_com->mac_vc.mac_ver < hal_com->fw_vc.mac_ver))
1451 return RTW_HAL_STATUS_FAILURE;
1452 return RTW_HAL_STATUS_SUCCESS;
1453 }
1454
1455
1456 enum rtw_hal_status
rtw_hal_watchdog(void * hal)1457 rtw_hal_watchdog(void *hal)
1458 {
1459 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
1460 enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
1461
1462 hal_status = rtw_hal_bb_watchdog(hal_info, false);
1463 if (hal_status != RTW_HAL_STATUS_SUCCESS) {
1464 PHL_ERR("%s rtw_hal_bb_watchdog fail (%x)\n", __FUNCTION__, hal_status);
1465 goto exit;
1466 }
1467
1468 hal_status = rtw_hal_rf_watchdog(hal_info);
1469 if (hal_status != RTW_HAL_STATUS_SUCCESS) {
1470 PHL_ERR("%s rtw_hal_rf_watchdog fail (%x)\n", __FUNCTION__, hal_status);
1471 goto exit;
1472 }
1473
1474 hal_status = rtw_hal_mac_watchdog(hal_info);
1475 if (hal_status != RTW_HAL_STATUS_SUCCESS) {
1476 PHL_ERR("%s rtw_hal_mac_watchdog fail (%x)\n", __FUNCTION__, hal_status);
1477 goto exit;
1478 }
1479
1480 exit:
1481 return hal_status;
1482 }
1483
1484 enum rtw_hal_status
rtw_hal_simple_watchdog(void * hal,u8 io_en)1485 rtw_hal_simple_watchdog(void *hal, u8 io_en)
1486 {
1487 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
1488 enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
1489
1490 hal_status = rtw_hal_bb_simple_watchdog(hal_info, io_en);
1491 if(hal_status != RTW_HAL_STATUS_SUCCESS){
1492 PHL_INFO("%s fail (%x)\n",
1493 __FUNCTION__, hal_status);
1494 goto exit;
1495 }
1496
1497 exit:
1498 return hal_status;
1499 }
1500
1501
1502 enum rtw_hal_status
rtw_hal_cfg_trx_path(void * hal,enum rf_path tx,u8 tx_nss,enum rf_path rx,u8 rx_nss)1503 rtw_hal_cfg_trx_path(void *hal, enum rf_path tx, u8 tx_nss,
1504 enum rf_path rx, u8 rx_nss)
1505 {
1506 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
1507 enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
1508
1509 if (tx < RF_PATH_AB) {
1510 /* forced tx nss = 1*/
1511 tx_nss = 1;
1512 }
1513 if (rx < RF_PATH_AB) {
1514 /* forced rx nss = 1*/
1515 rx_nss = 1;
1516 }
1517
1518 hal_status = rtw_hal_bb_trx_path_cfg(
1519 hal_info,
1520 tx,
1521 ((tx_nss > hal_info->hal_com->rfpath_tx_num) ?
1522 hal_info->hal_com->rfpath_tx_num : tx_nss),
1523 rx,
1524 ((rx_nss > hal_info->hal_com->rfpath_rx_num) ?
1525 hal_info->hal_com->rfpath_rx_num : rx_nss));
1526 #ifdef RTW_WKARD_SINGLE_PATH_RSSI
1527 hal_info->hal_com->cur_rx_rfpath = rx;
1528 #endif
1529
1530 return hal_status;
1531 }
1532
rtw_hal_set_sw_gpio_mode(struct rtw_phl_com_t * phl_com,void * hal,enum rtw_gpio_mode mode,u8 gpio)1533 enum rtw_hal_status rtw_hal_set_sw_gpio_mode(struct rtw_phl_com_t *phl_com, void *hal, enum rtw_gpio_mode mode, u8 gpio)
1534 {
1535 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
1536 enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
1537
1538 hal_status = rtw_hal_mac_set_sw_gpio_mode(hal_info, mode, gpio);
1539 PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s : status(%u).\n", __func__, hal_status);
1540
1541 return hal_status;
1542 }
1543
rtw_hal_sw_gpio_ctrl(struct rtw_phl_com_t * phl_com,void * hal,u8 high,u8 gpio)1544 enum rtw_hal_status rtw_hal_sw_gpio_ctrl(struct rtw_phl_com_t *phl_com, void *hal, u8 high, u8 gpio)
1545 {
1546 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
1547 enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
1548
1549 hal_status = rtw_hal_mac_sw_gpio_ctrl(hal_info, high, gpio);
1550 PHL_TRACE(COMP_PHL_WOW, _PHL_INFO_, "%s : status(%u).\n", __func__, hal_status);
1551
1552 return hal_status;
1553 }
1554
rtw_hal_dbg_status_dump(void * hal,struct hal_mac_dbg_dump_cfg * cfg)1555 void rtw_hal_dbg_status_dump(void *hal, struct hal_mac_dbg_dump_cfg *cfg)
1556 {
1557 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
1558
1559 rtw_hal_mac_dbg_status_dump(hal_info, cfg);
1560 }
1561
1562