1 /****************************************************************************** 2 * 3 * Copyright(c) 2019 - 2021 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef _HAL_DEF_H_ 16 #define _HAL_DEF_H_ 17 18 #define halcom_to_drvpriv(_hcom) (_hcom->drv_priv) 19 20 #define MAX_WD_LEN (48) 21 #define MAX_WD_BODY_LEN (24) 22 #define MAX_BAENTRY 2 23 24 enum HAL_CMD_ID { 25 HAL_HELP, 26 MAC_DD_DBG, 27 MAC_DUMP_SEC_CAM_TBL 28 }; 29 30 struct hal_cmd_info { 31 char name[16]; 32 u8 id; 33 }; 34 35 static const struct hal_cmd_info hal_cmd_i[] = { 36 {"-h", HAL_HELP}, 37 {"dd_dbg", MAC_DD_DBG},/*@do not move this element to other position*/ 38 {"sec_cam_tbl", MAC_DUMP_SEC_CAM_TBL} 39 }; 40 41 42 enum rtw_hal_status { 43 RTW_HAL_STATUS_SUCCESS, /* 0 */ 44 RTW_HAL_STATUS_FAILURE, /* 1 */ 45 RTW_HAL_STATUS_RESOURCE, /* 2 */ 46 RTW_HAL_STATUS_IO_INIT_FAILURE, /* 3 */ 47 RTW_HAL_STATUS_MAC_INIT_FAILURE, /* 4 */ 48 RTW_HAL_STATUS_BB_INIT_FAILURE, /* 5 */ 49 RTW_HAL_STATUS_RF_INIT_FAILURE, /* 6 */ 50 RTW_HAL_STATUS_BTC_INIT_FAILURE, /* 7 */ 51 RTW_HAL_STATUS_HAL_INIT_FAILURE, /* 8 */ 52 RTW_HAL_STATUS_EFUSE_UNINIT, /* 9 */ 53 RTW_HAL_STATUS_EFUSE_IVALID_OFFSET, /* 10 */ 54 RTW_HAL_STATUS_EFUSE_PG_FAIL, /* 11 */ 55 RTW_HAL_STATUS_MAC_API_FAILURE, /* 12 */ 56 RTW_HAL_STATUS_BB_CH_INFO_LAST_SEG, /*13*/ 57 RTW_HAL_STATUS_UNKNOWN_RFE_TYPE, /* 14 */ 58 RTW_HAL_STATUS_TIMEOUT, /* 15 */ 59 }; 60 61 #define FW_FILE_NIC_POSTFIX "" 62 #define FW_FILE_WOWLAN_POSTFIX "_wowlan" 63 #define FW_FILE_SPIC_POSTFIX "_spic" 64 #define FW_FILE_AP_POSTFIX "_ap" 65 66 enum rtw_fw_type { 67 RTW_FW_NIC, /* 1 */ 68 RTW_FW_WOWLAN, /* 2 */ 69 RTW_FW_AP, /* 3 */ 70 RTW_FW_ROM, /* 4 */ 71 RTW_FW_SPIC, /* 5 */ 72 RTW_FW_NIC_MP, /* 6 */ 73 RTW_FW_AP_MP, /* 7 */ 74 RTW_FW_VRAP, /* 8 */ 75 RTW_FW_MAX 76 }; 77 78 enum _rtw_hal_query_info { 79 RTW_HAL_RXDESC_SIZE, 80 }; 81 82 enum rtw_h2c_pkt_type { 83 H2CB_TYPE_CMD = 0, 84 H2CB_TYPE_DATA = 1, 85 H2CB_TYPE_LONG_DATA = 2, 86 H2CB_TYPE_MAX = 0x3 87 }; 88 89 enum tx_pause_rson { 90 PAUSE_RSON_NOR_SCAN, /*normal scan*/ 91 PAUSE_RSON_UNSPEC_BY_MACID, /*P2P_SCAN*/ 92 PAUSE_RSON_RFK, 93 PAUSE_RSON_PSD, 94 PAUSE_RSON_DFS, 95 PAUSE_RSON_DBCC, 96 PAUSE_RSON_RESET, 97 PAUSE_RSON_MAX 98 }; 99 100 enum rtw_hal_config_int { 101 RTW_HAL_EN_DEFAULT_INT, 102 RTW_HAL_DIS_DEFAULT_INT, 103 RTW_HAL_STOP_RX_INT, 104 RTW_HAL_RESUME_RX_INT, 105 RTW_HAL_SER_HANDSHAKE_MODE, 106 RTW_HAL_EN_HCI_INT, 107 RTW_HAL_DIS_HCI_INT, 108 RTW_HAL_CONFIG_INT_MAX 109 }; 110 111 enum hal_mp_efuse_type { 112 HAL_MP_EFUSE_WIFI = 0, 113 HAL_MP_EFUSE_BT, 114 HAL_MP_EFUSE_NONE, 115 }; 116 117 struct rtw_g6_h2c_hdr { 118 u8 h2c_class; //0x0~0x7: Phydm; 0x8~0xF: RF; 0x10~0x17: BTC 119 u8 h2c_func; 120 u8 seq_valid:1; 121 u8 seq:3; 122 u8 seq_stop:1; 123 enum rtw_h2c_pkt_type type; //0:cmd ; 1:cmd+data ; 2:cmd+long data 124 u16 content_len:12; 125 u16 rec_ack:1; //Ack when receive H2C 126 u16 done_ack:1; //Ack when FW execute H2C cmd done 127 u16 rsvd2:2; 128 }; 129 130 /** 131 * @c2h_cat: target category of this c2h / c2h ack 132 * @c2h_class: target class of this c2h / c2h ack 133 * @c2h_func: target function of this c2h / c2h ack 134 * @type_rec_ack: set 1 as a receive ack to this c2h 135 * @type_done_ack: set 1 as a done ack to this c2h 136 * @h2c_return: status code of done ack responding to h2c 137 * 138 */ 139 struct rtw_c2h_info { 140 u8 c2h_cat; 141 u8 c2h_class; 142 u8 c2h_func; 143 u8 type_rec_ack:1; 144 u8 type_done_ack:1; 145 u8 rsvd:6; 146 u8 h2c_return;/*H2C return value, 0 = success*/ 147 u8 h2c_seq; 148 u16 content_len; 149 u8 *content; 150 }; 151 152 153 #define RTW_BTC_OVERWRITE_BUF_LEN 10 154 struct hal_bt_msg { 155 _os_lock lock; 156 u16 len; 157 u16 cnt; /* update cnt */ 158 u8 latest[RTW_BTC_OVERWRITE_BUF_LEN]; 159 u8 working[RTW_BTC_OVERWRITE_BUF_LEN]; 160 }; 161 162 struct btc_fw_msg { 163 _os_lock lock; 164 u32 fev_cnt; /* fw event cnt, need to be protected by lock */ 165 166 struct hal_bt_msg btinfo; 167 struct hal_bt_msg scbd; 168 169 /* common fwinfo queue */ 170 struct phl_queue idleq; 171 struct phl_queue waitq; 172 }; 173 174 struct btc_ctrl_t { 175 u8 lps; 176 u8 tx_time; 177 u8 tx_retry; 178 }; 179 180 /*except version*/ 181 struct ver_ctrl_t { 182 u64 mac_ver; 183 u64 bb_ver; 184 u64 rf_ver; 185 u64 btc_ver; 186 u64 fw_ver; 187 }; 188 189 190 struct hal_mu_score_tbl_ctrl { 191 u32 mu_sc_thr:2; 192 u32 mu_opt:1; 193 u32 rsvd:29; 194 }; 195 196 #define HAL_MAX_MU_SCORE_SIZE 8 /* Unit: Byte */ 197 struct hal_mu_score_tbl_score { 198 u8 valid; 199 u16 macid; 200 u8 score[HAL_MAX_MU_SCORE_SIZE]; /*by case: [1:0], [3:2], ..... */ 201 }; 202 203 #define HAL_MAX_MU_STA_NUM 6 204 struct hal_mu_score_tbl { 205 struct hal_mu_score_tbl_ctrl mu_ctrl; 206 _os_lock lock; 207 u8 num_mu_sta; /*By IC, shall alway <= than HAL_MAX_MU_STA_NUM , 0 = tbl invalid */ 208 u8 sz_mu_score; /*By IC, shall alway <= than HAL_MAX_MU_SCORE_SIZE , 0 = score invalid */ 209 struct hal_mu_score_tbl_score mu_score[HAL_MAX_MU_STA_NUM]; /* mu_score[num_mu_sta] */ 210 }; 211 212 213 #define HAL_MAX_VHT_BFRP_NUM 3 214 #define HAL_MAX_HE_BFRP_NUM 2 215 #define HLA_MAX_BFRP_NUM ((HAL_MAX_VHT_BFRP_NUM > HAL_MAX_HE_BFRP_NUM) ?\ 216 HAL_MAX_VHT_BFRP_NUM : HAL_MAX_HE_BFRP_NUM) 217 #define HAL_MAX_VHT_SND_STA_NUM HAL_MAX_VHT_BFRP_NUM + 1 218 #define HAL_MAX_HE_BFRP_STA_NUM 4 219 #define HAL_MAX_HE_SND_STA_NUM HAL_MAX_HE_BFRP_NUM * HAL_MAX_HE_BFRP_STA_NUM 220 221 struct hal_frame_hdr { 222 u16 frame_ctl; 223 u16 duration; 224 u8 addr1[MAC_ALEN]; 225 u8 addr2[MAC_ALEN]; 226 }; 227 struct hal_npda_dialog_token { 228 u8 rsvd:1; 229 u8 he:1; 230 u8 token:6; 231 }; 232 233 #define HAL_NPDA_AC_SU 0 234 #define HAL_NPDA_AC_MU 1 235 #define HAL_NDPA_AX_FB_SU_NG_4 0 236 #define HAL_NDPA_AX_FB_SU_NG_16 2 237 #define HAL_NDPA_AX_FB_MU_NG_4 1 238 #define HAL_NDPA_AX_FB_MU_NG_16 3 239 #define HAL_NDPA_AX_FB_CQI 3 240 #define HAL_NPDA_AX_CB_SU42_MU75 0 241 #define HAL_NPDA_AX_CB_SU64_MU97 1 242 243 struct hal_he_snd_f2p { 244 u16 csi_len_bfrp:12; 245 u16 tb_t_pe_bfrp:2; 246 u16 tri_pad_bfrp:2; 247 248 u16 ul_cqi_rpt_tri_bfrp:1; 249 u16 rf_gain_idx_bfrp:10; 250 u16 fix_gain_en_bfrp:1; 251 u16 rsvd:4; 252 }; 253 254 struct hal_vht_ndpa_sta_info { 255 u32 aid12:12; 256 u32 feedback_type:1; 257 u32 nc:3; 258 u32 rsvd:16; 259 }; 260 261 struct hal_he_ndpa_sta_info { 262 u32 aid:11; 263 u32 bw:14; 264 u32 fb_ng:2; 265 u32 disambiguation:1; 266 u32 cb:1; 267 u32 nc:3; 268 }; 269 270 struct hal_ndpa_para { 271 struct hal_frame_hdr common; 272 struct hal_npda_dialog_token snd_dialog; 273 u32 ndpa_sta_info[HAL_MAX_HE_SND_STA_NUM]; 274 }; 275 276 struct hal_he_trg_frm_cmn { 277 u32 tgr_info: 4; 278 u32 ul_len: 12; 279 u32 more_tf: 1; 280 u32 cs_rqd: 1; 281 u32 ul_bw: 2; 282 u32 gi_ltf: 2; 283 u32 mimo_ltfmode: 1; 284 u32 num_heltf: 3; 285 u32 ul_pktext: 3; 286 u32 ul_stbc: 1; 287 u32 ldpc_extra_sym: 1; 288 u32 dplr: 1; 289 u32 ap_tx_pwr: 6; 290 u32 ul_sr: 16; 291 u32 ul_siga2_rsvd: 9; 292 u32 rsvd: 1; 293 }; 294 295 struct hal_he_trg_fm_user { 296 u16 aid12; 297 u8 ru_pos; 298 u8 ul_fec_code; 299 u8 ul_mcs; 300 u8 ul_dcm; 301 u8 ss_alloc; 302 u8 ul_tgt_rssi; 303 }; 304 305 struct hal_bfrp_he { 306 struct hal_he_trg_frm_cmn common; 307 struct hal_he_trg_fm_user user[HAL_MAX_HE_BFRP_STA_NUM]; 308 u8 fbseg_rexmit_bmp[HAL_MAX_HE_BFRP_STA_NUM];/*BFRP only*/ 309 struct hal_he_snd_f2p f2p_info; 310 }; 311 312 313 struct hal_bfrp_vht { 314 u8 rexmit_bmp; 315 }; 316 317 struct hal_bfrp_para { 318 struct hal_frame_hdr hdr[HLA_MAX_BFRP_NUM]; 319 struct hal_bfrp_he he_para[HAL_MAX_HE_BFRP_NUM]; 320 struct hal_bfrp_vht vht_para[HAL_MAX_VHT_BFRP_NUM]; 321 }; 322 323 struct hal_snd_wd_para { 324 u16 txpktsize; 325 u16 ndpa_duration; 326 u16 datarate:9; 327 u16 macid:7; 328 u8 force_txop:1; 329 u8 data_bw:2; 330 u8 gi_ltf:3; 331 u8 data_er:1; 332 u8 data_dcm:1; 333 u8 data_stbc:1; 334 u8 data_ldpc:1; 335 u8 data_bw_er:1; 336 u8 multiport_id:1; 337 u8 mbssid:4; 338 u8 signaling_ta_pkt_sc:4; 339 u8 sw_define:4; 340 u8 txpwr_ofset_type:3; 341 u8 lifetime_sel:3; 342 u8 stf_mode:1; 343 u8 disdatafb:1; 344 u8 data_txcnt_lmt_sel:1; 345 u8 data_txcnt_lmt:6; 346 u8 sifs_tx:1; 347 u8 snd_pkt_sel:3; 348 u8 ndpa:2; 349 u8 rsvd:3; 350 }; 351 352 #define HAL_FEXG_TYPE_AC_SU 31 353 #define HAL_FEXG_TYPE_AC_MU_1 32 354 #define HAL_FEXG_TYPE_AC_MU_2 33 355 #define HAL_FEXG_TYPE_AC_MU_3 34 356 #define HAL_FEXG_TYPE_AX_SU 35 357 #define HAL_FEXG_TYPE_AX_MU_1 36 358 #define HAL_FEXG_TYPE_AX_MU_2 37 359 360 struct hal_ax_fwcmd_snd { 361 u8 frame_ex_type; 362 u8 bfrp0_sta_nr; 363 u8 bfrp1_sta_nr; 364 u16 macid[8]; 365 struct hal_ndpa_para ndpa; 366 struct hal_bfrp_para bfrp; 367 /** 368 * HE: NDPA NDP HE_Trigger_BFRP (CSI) BFRP (CSI) 369 * VHT: NDPA NDP (CSI) VHT_BFRP (CSI) BFRP (CSI) BFRP (CSI) 370 **/ 371 struct hal_snd_wd_para wd[HLA_MAX_BFRP_NUM + 2]; 372 }; 373 374 375 struct rtw_hal_com_t; 376 struct hal_io_ops { 377 u8(*_read8)(struct rtw_hal_com_t *hal, u32 addr); 378 u16(*_read16)(struct rtw_hal_com_t *hal, u32 addr); 379 u32(*_read32)(struct rtw_hal_com_t *hal, u32 addr); 380 void (*_read_mem)(struct rtw_hal_com_t *hal, u32 addr, u32 cnt, u8 *pmem); 381 382 int (*_write8)(struct rtw_hal_com_t *hal, u32 addr, u8 val); 383 int (*_write16)(struct rtw_hal_com_t *hal, u32 addr, u16 val); 384 int (*_write32)(struct rtw_hal_com_t *hal, u32 addr, u32 val); 385 int (*_write_mem)(struct rtw_hal_com_t *hal, u32 addr, u32 length, u8 *pdata); 386 387 #ifdef RTW_WKARD_BUS_WRITE 388 int (*_write_post_cfg)(struct rtw_hal_com_t *hal, u32 addr, u32 val); 389 #endif 390 391 #ifdef CONFIG_SDIO_HCI 392 u8(*_sd_f0_read8)(struct rtw_hal_com_t *hal, u32 addr); 393 #ifdef CONFIG_SDIO_INDIRECT_ACCESS 394 u8(*_sd_iread8)(struct rtw_hal_com_t *hal, u32 addr); 395 u16(*_sd_iread16)(struct rtw_hal_com_t *hal, u32 addr); 396 u32(*_sd_iread32)(struct rtw_hal_com_t *hal, u32 addr); 397 int (*_sd_iwrite8)(struct rtw_hal_com_t *hal, u32 addr, u8 val); 398 int (*_sd_iwrite16)(struct rtw_hal_com_t *hal, u32 addr, u16 val); 399 int (*_sd_iwrite32)(struct rtw_hal_com_t *hal, u32 addr, u32 val); 400 #endif /* CONFIG_SDIO_INDIRECT_ACCESS */ 401 #endif 402 }; 403 404 struct hal_io_priv { 405 #ifdef CONFIG_SDIO_INDIRECT_ACCESS 406 _os_mutex sd_indirect_access_mutex; 407 #endif 408 struct hal_io_ops io_ops; 409 }; 410 411 #define halcom_to_drvpriv(_hcom) (_hcom->drv_priv) 412 #define hal_get_chip_id(_halcom) (_halcom->chip_id) 413 414 enum pcfg_type { 415 PCFG_FUNC_SW, 416 PCFG_TBTT_AGG, 417 PCFG_TBTT_SHIFT, 418 PCFG_HIQ_WIN, 419 PCFG_HIQ_DTIM, 420 PCFG_HIQ_MAX, 421 PCFG_BCN_INTERVAL, /* Beacon Interval */ 422 PCFG_BSS_CLR, 423 PCFG_BCN_EN 424 }; 425 426 /* 427 * refers to _usb.h 428 * #define USB11 0x1 429 * #define USB2 0x2 430 * #define USB3 0x3 431 * */ 432 enum usb_type { 433 USB_1_1 = 1, 434 USB_2_0, 435 USB_3_0, 436 }; 437 #ifdef RTW_PHL_BCN 438 struct bcn_entry_pool { 439 u8 bcn_num; 440 _os_list bcn_list; 441 _os_lock bcn_lock; 442 }; 443 #endif 444 445 enum rtw_hal_set_def_var_rsn { 446 SET_DEF_RSN_HAL_INIT, 447 SET_DEF_RSN_WOW_RESUME_HNDL_RX, 448 SET_DEF_RSN_WOW_RESUME_DONE 449 }; 450 451 struct hal_intr_mask_cfg { 452 u8 halt_c2h_en; 453 u8 wdt_en; 454 }; 455 456 struct hal_halt_c2h_int { 457 /* halt c2h */ 458 u32 intr; 459 u32 val_mask; 460 u32 val_default; 461 }; 462 463 struct hal_watchdog_timer_int { 464 /* watchdog timer */ 465 u32 intr; 466 u32 val_mask; 467 u32 val_default; 468 }; 469 470 struct hal_int_array { 471 struct hal_halt_c2h_int halt_c2h_int; 472 struct hal_watchdog_timer_int watchdog_timer_int; 473 }; 474 475 /* c2h event id for hal/phl layer */ 476 enum rtw_hal_c2h_ev { 477 HAL_C2H_EV_DO_NOTHING = 0, 478 HAL_C2H_EV_BB_MUGRP_DOWN = 1,/* BB Process C2H mu-score-tbl done */ 479 HAL_C2H_EV_BTC_INFO = 2, /* BTC event */ 480 HAL_C2H_EV_BTC_SCBD = 3, /* BTC event */ 481 HAL_C2H_EV_MAC_TSF32_TOG = 4, /* MAC event */ 482 HAL_C2H_EV_MAX 483 }; 484 485 /* ppdu status : per user info */ 486 struct hal_ppdu_sts_usr { 487 /* MAC */ 488 u8 vld:1; 489 u8 has_data:1; 490 u8 has_ctrl:1; 491 u8 has_mgnt:1; 492 u8 has_bcn:1; 493 u16 macid; 494 }; 495 496 enum hal_rxcnt_sel { 497 HAL_RXCNT_OFDM_OK = 0, 498 HAL_RXCNT_OFDM_FAIL = 1, 499 HAL_RXCNT_OFDM_FAM = 2, 500 HAL_RXCNT_CCK_OK = 3, 501 HAL_RXCNT_CCK_FAIL = 4, 502 HAL_RXCNT_CCK_FAM = 5, 503 HAL_RXCNT_HT_OK = 6, 504 HAL_RXCNT_HT_FAIL = 7, 505 HAL_RXCNT_HT_PPDU = 8, 506 HAL_RXCNT_HT_FAM = 9, 507 HAL_RXCNT_VHTSU_OK = 0xA, 508 HAL_RXCNT_VHTSU_FAIL = 0xB, 509 HAL_RXCNT_VHTSU_PPDU = 0xC, 510 HAL_RXCNT_VHTSU_FAM = 0xD, 511 HAL_RXCNT_VHTMU_OK = 0xE, 512 HAL_RXCNT_VHTMU_FAIL = 0xF, 513 HAL_RXCNT_VHTMU_PPDU = 0x10, 514 HAL_RXCNT_VHTMU_FAM = 0x11, 515 HAL_RXCNT_HESU_OK = 0x12, 516 HAL_RXCNT_HESU_FAIL = 0x13, 517 HAL_RXCNT_HESU_PPDU = 0x14, 518 HAL_RXCNT_HESU_FAM = 0x15, 519 HAL_RXCNT_HEMU_OK = 0x16, 520 HAL_RXCNT_HEMU_FAIL = 0x17, 521 HAL_RXCNT_HEMU_PPDU = 0x18, 522 HAL_RXCNT_HEMU_FAM = 0x19, 523 HAL_RXCNT_HETB_OK = 0x1A, 524 HAL_RXCNT_HETB_FAIL = 0x1B, 525 HAL_RXCNT_HETB_PPDU = 0x1C, 526 HAL_RXCNT_HETB_FAM = 0x1D, 527 HAL_RXCNT_INVD = 0x1E, 528 HAL_RXCNT_RECCA = 0x1F, 529 HAL_RXCNT_FULLDRP = 0x20, 530 HAL_RXCNT_FULLDRP_PKT = 0x21, 531 HAL_RXCNT_RXDMA = 0x22, 532 HAL_RXCNT_USER0 = 0x23, 533 HAL_RXCNT_USER1 = 0x24, 534 HAL_RXCNT_USER2 = 0x25, 535 HAL_RXCNT_USER3 = 0x26, 536 HAL_RXCNT_CONT_FCS = 0x27, 537 HAL_RXCNT_PKTFLTR_DRP = 0x28, 538 HAL_RXCNT_CSIPKT_DMA_OK = 0x29, 539 HAL_RXCNT_CSIPKT_DMA_DROP = 0x2A, 540 HAL_RXCNT_MAX 541 }; 542 543 enum hal_rate_mode { 544 HAL_LEGACY_MODE = 0, 545 HAL_HT_MODE = 1, 546 HAL_VHT_MODE = 2, 547 HAL_HE_MODE = 3 548 }; 549 550 enum hal_rate_bw { 551 HAL_RATE_BW_20 = 0, 552 HAL_RATE_BW_40 = 1, 553 HAL_RATE_BW_80 = 2, 554 HAL_RATE_BW_160 = 3, 555 }; 556 557 struct hal_ppdu_rx_cnt { 558 u16 ppdu_cnt[HAL_RXCNT_MAX]; 559 }; 560 561 /* ppdu sts mac bmp_append_info */ 562 #define HAL_PPDU_MAC_INFO BIT(1) 563 #define HAL_PPDU_PLCP BIT(3) 564 #define HAL_PPDU_RX_CNT BIT(2) 565 /* ppdu sts mac bmp_filter */ 566 #define HAL_PPDU_HAS_A1M BIT(4) 567 #define HAL_PPDU_HAS_CRC_OK BIT(5) 568 569 /* ppdu status (mac info + phy info) */ 570 struct hal_ppdu_sts { 571 #define RTW_HAL_PPDU_STS_MAX_USR 4 572 /* MAC */ 573 /* NOTE: (rx_cnt, plcp, phy_st)_ptr are only available before phl_recycle_rx_buf() */ 574 u8 *rx_cnt_ptr; 575 u8 *plcp_ptr; 576 u8 *phy_st_ptr; /* for bb phy status */ 577 u8 plcp_size; 578 u32 phy_st_size;/* for bb phy status */ 579 u32 rx_cnt_size; 580 u8 usr_num; 581 struct hal_ppdu_sts_usr usr[RTW_HAL_PPDU_STS_MAX_USR]; 582 struct hal_ppdu_rx_cnt rx_cnt; 583 }; 584 585 #define HAL_RSSI_MAVG_NUM 16 586 #define STA_UPDATE_MA_RSSI_FAST(_RSSI, _VAL) _RSSI = ((_RSSI * \ 587 (HAL_RSSI_MAVG_NUM - 1)) + _VAL) \ 588 / HAL_RSSI_MAVG_NUM 589 590 struct rtw_cfo_info { 591 s32 cfo_tail; 592 s32 pre_cfo_avg; 593 s32 cfo_avg; 594 u16 cfo_cnt; 595 u32 tp; 596 }; 597 598 struct rtw_rssi_info { 599 u8 rssi; /* u(8,1), hal-bb provide, read only : 0~110 (dBm = rssi -110) */ 600 u16 rssi_ma; /* u(16,5), hal-bb provide, read only : u16 U(12,4)*/ 601 u16 rssi_ma_path[4]; 602 u16 pkt_cnt_data; 603 u8 rssi_bcn; /* u(8,1), beacon RSSI, hal-bb provide, read only : 0~110 (dBm = rssi -110) */ 604 u16 rssi_bcn_ma; /* u(16,5), beacon RSSI, hal-bb provide, read only*/ 605 u16 rssi_bcn_ma_path[4]; 606 u16 pkt_cnt_bcn; 607 u8 ma_factor:4; 608 u8 ma_factor_bcn:4; 609 u8 rssi_ofdm; /* u(8,1), hal-bb provide, read only : packet, for debug */ 610 u8 rssi_cck; /* u(8,1), hal-bb provide, read only : packet, for debug */ 611 u8 assoc_rssi; /* phl_rx provide, read only */ 612 /* phl_rx provide, read only : Moving Average RSSI information for the STA */ 613 u8 ma_rssi; /* moving average : 0 ~ PHL_MAX_RSSI (dBm = rssi - PHL_MAX_RSSI) */ 614 u8 ma_rssi_mgnt; /* moving average rssi for beacon/probe : 0 ~ PHL_MAX_RSSI (dBm = rssi - PHL_MAX_RSSI) */ 615 u16 snr_ma; /* u(16,4), hal-bb provide, read only, SNR= snr_ma dBm*/ 616 }; 617 618 struct rtw_rate_info { 619 enum rtw_gi_ltf gi_ltf; /* 3bit GILTF */ 620 enum hal_rate_mode mode; /* 2bit 0:legacy, 1:HT, 2:VHT, 3:HE*/ 621 enum hal_rate_bw bw; /*2bit 0:5M/10M/20M, 1:40M, 2:80M, 3:160M or 80+80*/ 622 u8 mcs_ss_idx; /*HE: 3bit SS + 4bit MCS; non-HE: 5bit MCS/rate idx */ 623 }; 624 625 /* from cmn_sta_info */ 626 struct rtw_ra_sta_info { 627 /*u8 rate_id; remove !!! use wmode in phl, [PHYDM] ratr_idx*/ 628 /*u8 rssi_level; [PHYDM]*/ 629 /*u8 is_first_connect:1; change connect flow, [PHYDM] CE: ra_rpt_linked, AP: H2C_rssi_rpt*/ 630 /*u8 is_support_sgi:1; mov to phl [driver]*/ 631 /*u8 is_vht_enable:2; mov to phl [driver]*/ 632 /*u8 disable_ra:1; mov to hal [driver]*/ 633 /*u8 disable_pt:1; remove for no PT, [driver] remove is_disable_power_training*/ 634 /*u8 txrx_state:2; ///////////////need to check if needed, [PHYDM] 0: Tx, 1:Rx, 2:bi-direction*/ 635 /*u8 is_noisy:1; ///////////////need to check if needed, [PHYDM]*/ 636 u16 curr_tx_rate; /*use struct bb_rate_info, [PHYDM] FW->Driver*/ 637 enum channel_width ra_bw_mode; /*remove to phl, [Driver] max bandwidth, for RA only*/ 638 enum channel_width curr_tx_bw; /*bb_rate_info, [PHYDM] FW->Driver*/ 639 /* u8 drv_ractrl; */ 640 641 /* Ctrl */ 642 u8 ra_nss_limit; /* 0: no limitation, otherwise, limit to tx nss pkt*/ 643 bool dis_ra; /*move from rtw_hal_stainfo_t*/ 644 bool ra_registered;/*move from rtw_hal_stainfo_t*/ 645 u64 ra_mask;/*move from rtw_hal_stainfo_t*/ /*drv decide by specific req*/ 646 u64 cur_ra_mask;/*move from rtw_hal_stainfo_t*/ 647 /*halbb create, mod by driver and decide by rssi or other*/ 648 u8 cal_giltf; /* 3bit gi_ltf ctrl by driver*/ 649 bool fix_giltf_en; /*giltf from cal_giltf or halbb*/ 650 bool fixed_rt_en; 651 struct rtw_rate_info fixed_rt_i; 652 u8 rainfo_cfg1; /* prepare for other control*/ 653 u8 rainfo_cfg2; /* prepare for other control*/ 654 655 /* Report */ 656 struct rtw_rate_info rpt_rt_i; 657 u8 curr_retry_ratio; /*[HALBB] FW->Driver*/ 658 659 bool ra_csi_rate_en; 660 bool fixed_csi_rate_en; 661 u8 band_num; 662 struct rtw_rate_info csi_rate; 663 664 u8 avg_agg; 665 u32 tx_ok_cnt[4]; 666 u32 tx_retry_cnt[4]; 667 u32 tx_total_cnt; 668 /*u64 ramask;*/ 669 }; 670 671 struct rtw_mura_info { 672 /* Ctrl */ 673 bool fixed_rt_en; 674 struct rtw_rate_info fixed_rt_i; 675 /* Report */ 676 struct rtw_rate_info rpt_rt_i; 677 u8 curr_retry_ratio; /*[PHYDM] FW->Driver*/ 678 }; 679 680 /* from cmn_sta_info */ 681 struct rtw_dtp_info { 682 u8 dyn_tx_power; /*Dynamic Tx power offset*/ 683 u8 last_tx_power; 684 u8 sta_tx_high_power_lvl:4; 685 u8 sta_last_dtp_lvl:4; 686 }; 687 688 struct rtw_hal_muba_info { 689 u32 fix_ba:1; 690 u32 ru_psd:9; 691 u32 tf_rate:9; 692 u32 rf_gain_fix:1; 693 u32 rf_gain_idx:10; 694 u32 tb_ppdu_bw:2; 695 u8 dcm:1; 696 u8 ss:3; 697 u8 mcs:4; 698 u8 gi_ltf:3; 699 u8 doppler:1; 700 u8 stbc:1; 701 u8 sta_coding:1; 702 u8 tb_t_pe_nom:2; 703 u8 pr20_bw_en:1; 704 u8 ma_type: 1; 705 u8 rsvd1: 6; 706 }; 707 708 enum rtw_hal_protection_type { 709 HAL_PROT_NO_PROETCT = 0, 710 HAL_PROT_PRIUSER_HW_RTS = 1, 711 HAL_PROT_RTS = 2, 712 HAL_PROT_CTS2SELF = 3, 713 HAL_PROT_MU_RTS = 4, 714 HAL_PROT_HW_DEFAULT_ = 5 715 }; 716 717 enum rtw_hal_ack_resp_type { 718 HAL_ACK_N_MINUS_1USER_BA = 0, 719 HAL_ACK_N_USER_BA = 1, 720 HAL_ACK_MU_BAR = 2, 721 HAL_ACK_HTP_ACK = 3, 722 HAL_ACK_HW_DEFAULT = 4 723 }; 724 725 struct rtw_wp_rpt_stats { 726 u32 busy_cnt; 727 u32 tx_ok_cnt; 728 u32 rty_fail_cnt; 729 u32 lifetime_drop_cnt; 730 u32 macid_drop_cnt; 731 u32 sw_drop_cnt; 732 u32 recycle_fail_cnt; 733 u32 delay_tx_ok_cnt; 734 u32 delay_rty_fail_cnt; 735 u32 delay_lifetime_drop_cnt; 736 u32 delay_macid_drop_cnt; 737 }; 738 739 struct rtw_trx_stat { 740 u32 rx_ok_cnt; 741 u32 rx_err_cnt; 742 u16 rx_rate_plurality; 743 /* add lock for tx statistics */ 744 _os_lock tx_sts_lock; 745 /* Below info is for release report*/ 746 u32 tx_fail_cnt; 747 u32 tx_ok_cnt; 748 #ifdef CONFIG_USB_HCI 749 struct rtw_wp_rpt_stats wp_rpt_stats[PHL_AC_QUEUE_TOTAL]; 750 #endif 751 #ifdef CONFIG_PCI_HCI 752 u8 *wp_rpt_stats; 753 u32 ltr_tx_dly_count; 754 u32 ltr_last_tx_dly_time; 755 #endif 756 }; 757 758 struct bacam_ctrl_t { 759 u8 used_map[MAX_BAENTRY]; 760 u8 tid[MAX_BAENTRY]; 761 u8 count; 762 }; 763 764 struct rtw_hal_stainfo_t { 765 /* from cmn_sta_info */ 766 u16 dm_ctrl; 767 /* struct su_ra_info */ 768 struct rtw_rssi_info rssi_stat; 769 struct rtw_cfo_info cfo_stat; 770 771 /* Beamform Related */ 772 u8 bf_cap;/* sta's beamform capability : ht/vht/he + bfee/bfer */ 773 void *bf_entry; 774 u16 bf_csi_buf; 775 u16 bf_csi_buf_swap;/*used in mu swap mode*/ 776 /* BFee capability */ 777 u8 max_nc; 778 u8 nr; 779 u8 ng16;/* 0:non-support ; BIT0:support SU ; BIT1:support MU */ 780 u8 cb_sz;/* 0:non-support ; BIT0:support (4,2) SU ; BIT1:support (7,5) MU */ 781 u8 support_cqi_fb; 782 /*mu group*/ 783 u8 mugrp_bmp; 784 u32 mu_score; 785 /*FW Frame Exchange : when STA is primary STA, prefer protect type and ack resp type in MU*/ 786 enum rtw_hal_protection_type prot_type; 787 enum rtw_hal_ack_resp_type resp_type; 788 struct bacam_ctrl_t ba_ctl; 789 790 /* from cmn_sta_info */ 791 struct rtw_ra_sta_info ra_info; 792 /* from cmn_sta_info */ 793 struct rtw_dtp_info dtp_stat; 794 struct rtw_trx_stat trx_stat; 795 void *hw_cfg_tab; 796 void *bb_sta; 797 }; 798 799 800 801 struct bus_hw_cap_t { 802 #ifdef CONFIG_PCI_HCI 803 enum rtw_pcie_bus_func_cap_t l0s_ctrl; 804 enum rtw_pcie_bus_func_cap_t l1_ctrl; 805 enum rtw_pcie_bus_func_cap_t l1ss_ctrl; 806 enum rtw_pcie_bus_func_cap_t wake_ctrl; 807 enum rtw_pcie_bus_func_cap_t crq_ctrl; 808 u8 clkdly_ctrl; 809 u8 l0sdly_ctrl; 810 u8 l1dly_ctrl; 811 u8 ltr_sw_ctrl; /* whether ltr can be controlled by sw */ 812 u8 ltr_hw_ctrl; 813 u32 max_txbd_num; 814 u32 max_rxbd_num; 815 u32 max_rpbd_num; 816 u8 max_phyaddr_num; 817 u8 max_wd_page_size; 818 u8 txbd_len; 819 u8 rxbd_len; 820 u8 wdb_size; 821 u8 wdi_size; 822 u8 addr_info_size; 823 u8 seq_info_size; 824 #elif defined (CONFIG_USB_HCI) 825 u32 tx_buf_size; 826 u32 tx_buf_num; 827 u32 tx_mgnt_buf_size; 828 u32 tx_mgnt_buf_num; 829 u32 tx_h2c_buf_num; 830 u32 rx_buf_size; 831 u32 rx_buf_num; 832 u32 in_token_num; 833 #elif defined (CONFIG_SDIO_HCI) 834 u32 tx_buf_size; 835 u32 tx_buf_num; 836 u32 tx_mgnt_buf_size; 837 u32 tx_mgnt_buf_num; 838 u32 rx_buf_size; 839 u32 rx_buf_num; 840 #else 841 u8 temp_for_struct_empty; /* for undefined interface */ 842 #endif 843 }; 844 845 /* phy capability of phy */ 846 struct phy_hw_cap_t { 847 #ifdef RTW_WKARD_BTC_RFETYPE 848 u8 rfe_type; 849 #endif 850 u8 tx_num; 851 u8 rx_num; 852 u16 hw_rts_time_th; 853 u16 hw_rts_len_th; 854 }; 855 856 857 /*PHYx + Sx*/ 858 enum phl_phy_idx { 859 HW_PHY_0, 860 HW_PHY_1, 861 HW_PHY_MAX 862 }; 863 864 enum phl_pwr_table { 865 PWR_BY_RATE = BIT0, 866 PWR_LIMIT = BIT1, 867 PWR_LIMIT_RU = BIT2 868 }; 869 870 enum phl_rf_mode { 871 RF_MODE_NORMAL = 0, 872 RF_MODE_SHUTDOWN = 1, 873 RF_MODE_STANDBY = 2, 874 RF_MODE_RX = 3, 875 RF_MODE_TX = 4, 876 RF_MODE_MAX 877 }; 878 879 880 /*--------------------------------------------------------------------------*/ 881 /*[TX Power Unit(TPU) array size]*/ 882 #define TPU_SIZE_PWR_TAB 16 /*MCS0~MCS11(12) + {dcm_0,1,3,4}4 = 16*/ 883 #define TPU_SIZE_PWR_TAB_lGCY 12 /*cck(4) + ofdm(8) = 12*/ 884 #define TPU_SIZE_MODE 5 /*0~4: HE, VHT, HT, Legacy, CCK, */ 885 #define TPU_SIZE_BW 5 /*0~4: 80_80, 160, 80, 40, 20*/ 886 #define TPU_SIZE_RUA 3 /*{26, 52, 106}*/ 887 #define TPU_SIZE_BW20_SC 8 /*8 * 20M = 160M*/ 888 #define TPU_SIZE_BW40_SC 4 /*4 * 40M = 160M*/ 889 #define TPU_SIZE_BW80_SC 2 /*2 * 80M = 160M*/ 890 #define TPU_SIZE_BF 2 /*{NON_BF, BF}*/ 891 892 #if defined(CONFIG_RTL8851A) 893 #define HAL_COMPILE_IC_1SS 894 #endif 895 896 #if (defined(CONFIG_RTL8852A) || defined(CONFIG_RTL8852B) || defined(CONFIG_RTL8852C)) 897 #define HAL_COMPILE_IC_2SS 898 #endif 899 900 #if defined(CONFIG_RTL8853A) 901 #define HAL_COMPILE_IC_3SS 902 #endif 903 904 #if defined(CONFIG_RTL8834A) 905 #define HAL_COMPILE_IC_4SS 906 #endif 907 908 /*@==========================================================================*/ 909 #if (defined(HAL_COMPILE_IC_4SS)) 910 #define HAL_COMPILE_ABOVE_4SS 911 #endif 912 913 #if (defined(HAL_COMPILE_IC_3SS) || defined(HAL_COMPILE_ABOVE_4SS)) 914 #define HAL_COMPILE_ABOVE_3SS 915 #endif 916 917 #if (defined(HAL_COMPILE_IC_2SS) || defined(HAL_COMPILE_ABOVE_3SS)) 918 #define HAL_COMPILE_ABOVE_2SS 919 #endif 920 921 #if (defined(HAL_COMPILE_IC_1SS) || defined(HAL_COMPILE_ABOVE_2SS)) 922 #define HAL_COMPILE_ABOVE_1SS 923 #endif 924 925 #if (defined(HAL_COMPILE_ABOVE_4SS)) 926 #define HAL_MAX_PATH 4 927 #elif (defined(HAL_COMPILE_ABOVE_3SS)) 928 #define HAL_MAX_PATH 3 929 #elif (defined(HAL_COMPILE_ABOVE_2SS)) 930 #define HAL_MAX_PATH 2 931 #else 932 #define HAL_MAX_PATH 1 933 #endif 934 935 /*--------------------------[Structure]-------------------------------------*/ 936 enum rtw_tpu_op_mode { 937 TPU_NORMAL_MODE = 0, 938 TPU_DBG_MODE = 1 939 }; 940 941 struct rtw_tpu_pwr_by_rate_info { /*TX Power Unit (TPU)*/ 942 s8 pwr_by_rate_lgcy[TPU_SIZE_PWR_TAB_lGCY]; 943 s8 pwr_by_rate[HAL_MAX_PATH][TPU_SIZE_PWR_TAB]; 944 }; 945 946 struct rtw_tpu_ext_pwr_lmt_info { /*TX Power Unit (TPU)*/ 947 s8 ext_pwr_lmt_2_4g[HAL_MAX_PATH]; 948 s8 ext_pwr_lmt_5g_band1[HAL_MAX_PATH]; /*CH36 ~ CH48*/ 949 s8 ext_pwr_lmt_5g_band2[HAL_MAX_PATH]; /*CH52 ~ CH64*/ 950 s8 ext_pwr_lmt_5g_band3[HAL_MAX_PATH]; /*CH100 ~ CH144*/ 951 s8 ext_pwr_lmt_5g_band4[HAL_MAX_PATH]; /*CH149 ~ CH165*/ 952 }; 953 954 struct rtw_tpu_pwr_imt_info { /*TX Power Unit (TPU)*/ 955 s8 pwr_lmt_cck_20m[HAL_MAX_PATH][TPU_SIZE_BF]; 956 s8 pwr_lmt_cck_40m[HAL_MAX_PATH][TPU_SIZE_BF]; 957 s8 pwr_lmt_lgcy_20m[HAL_MAX_PATH][TPU_SIZE_BF]; /*ofdm*/ 958 s8 pwr_lmt_20m[HAL_MAX_PATH][TPU_SIZE_BW20_SC][TPU_SIZE_BF]; 959 s8 pwr_lmt_40m[HAL_MAX_PATH][TPU_SIZE_BW40_SC][TPU_SIZE_BF]; 960 s8 pwr_lmt_80m[HAL_MAX_PATH][TPU_SIZE_BW80_SC][TPU_SIZE_BF]; 961 s8 pwr_lmt_160m[HAL_MAX_PATH][TPU_SIZE_BF]; 962 s8 pwr_lmt_40m_0p5[HAL_MAX_PATH][TPU_SIZE_BF]; 963 s8 pwr_lmt_40m_2p5[HAL_MAX_PATH][TPU_SIZE_BF]; 964 }; 965 966 struct rtw_tpu_info { /*TX Power Unit (TPU)*/ 967 enum rtw_tpu_op_mode op_mode; /*In debug mode, only debug tool control TPU APIs*/ 968 bool normal_mode_lock_en; 969 s8 ofst_int; /*SW: S(8,3) -16 ~ +15.875 (dB)*/ 970 u8 ofst_fraction; /*[0:3] * 0.125(dBm)*/ 971 u8 base_cw_0db; /*[63~39~15]: [+24~0~-24 dBm]*/ 972 u16 tssi_16dBm_cw; 973 /*[Ref Pwr]*/ 974 s16 ref_pow_ofdm; /*-> HW: s(9,2)*/ 975 s16 ref_pow_cck; /*-> HW: s(9,2)*/ 976 u16 ref_pow_ofdm_cw; /*BBCR 0x58E0[9:0]*/ 977 u16 ref_pow_cck_cw; /*BBCR 0x58E0[21:12]*/ 978 /*[Pwr Ofsset]*/ /*-> HW: s(7,1)*/ 979 s8 pwr_ofst_mode[TPU_SIZE_MODE]; /*0~4: HE, VHT, HT, Legacy, CCK, */ 980 s8 pwr_ofst_bw[TPU_SIZE_BW]; /*0~4: 80_80, 160, 80, 40, 20*/ 981 /*[Pwr By rate]*/ /*-> HW: s(7,1)*/ 982 struct rtw_tpu_pwr_by_rate_info rtw_tpu_pwr_by_rate_i; 983 /*[Pwr Limit]*/ /*-> HW: s(7,1)*/ 984 struct rtw_tpu_pwr_imt_info rtw_tpu_pwr_imt_i; 985 /*[Pwr Limit RUA]*/ /*-> HW: s(7,1)*/ 986 s8 pwr_lmt_ru[HAL_MAX_PATH][TPU_SIZE_RUA][TPU_SIZE_BW20_SC]; 987 u16 pwr_lmt_ru_mem_size; 988 bool pwr_lmt_en; 989 u8 tx_ptrn_shap_idx; 990 u8 tx_ptrn_shap_idx_cck; 991 }; 992 993 struct rtw_hal_stat_info { 994 u32 cnt_fail_all; 995 u32 cnt_cck_fail; 996 u32 cnt_ofdm_fail; 997 u32 cnt_cca_all; 998 u32 cnt_ofdm_cca; 999 u32 cnt_cck_cca; 1000 u32 cnt_crc32_error_all; 1001 u32 cnt_he_crc32_error; 1002 u32 cnt_vht_crc32_error; 1003 u32 cnt_ht_crc32_error ; 1004 u32 cnt_ofdm_crc32_error; 1005 u32 cnt_cck_crc32_error; 1006 u32 cnt_crc32_ok_all; 1007 u32 cnt_he_crc32_ok; 1008 u32 cnt_vht_crc32_ok; 1009 u32 cnt_ht_crc32_ok; 1010 u32 cnt_ofdm_crc32_ok; 1011 u32 cnt_cck_crc32_ok; 1012 u32 igi_fa_rssi; 1013 }; 1014 1015 struct rtw_hw_band { 1016 struct rtw_chan_def cur_chandef; 1017 u8 ppdu_sts_appen_info; 1018 u8 ppdu_sts_filter; 1019 struct rtw_tpu_info rtw_tpu_i; /*TX Power Unit (TPU)*/ 1020 u16 tx_pause[PAUSE_RSON_MAX]; /* ref: enum rtw_sch_txen_cfg */ 1021 struct rtw_hal_stat_info stat_info; 1022 }; 1023 1024 struct rtw_hal_com_t { 1025 enum rtw_chip_id chip_id; 1026 enum rtw_cv cv; 1027 1028 struct ver_ctrl_t mac_vc; 1029 struct ver_ctrl_t bb_vc; 1030 struct ver_ctrl_t rf_vc; 1031 struct ver_ctrl_t btc_vc; 1032 struct ver_ctrl_t fw_vc; 1033 1034 struct protocol_cap_t proto_hw_cap[MAX_BAND_NUM]; /* wifi protocol capability from EFUSE/halmac/halbb/halrf/... */ 1035 struct phy_hw_cap_t phy_hw_cap[MAX_BAND_NUM]; /* phy capability from EFUSE/halmac/halbb/halrf/... */ 1036 struct dev_cap_t dev_hw_cap; 1037 1038 struct bus_hw_cap_t bus_hw_cap; /* Bus HW capability */ 1039 struct bus_cap_t bus_cap; /* Final bus capability */ 1040 struct hal_io_priv iopriv; 1041 #ifdef DBG_HAL_MAC_MEM_MOINTOR 1042 _os_atomic hal_mac_mem; 1043 #endif 1044 #ifdef DBG_HAL_MEM_MOINTOR 1045 _os_atomic hal_mem; 1046 #endif 1047 bool is_hal_init; 1048 struct rtw_hw_band band[MAX_BAND_NUM];/*band0/band1 for DBCC*/ 1049 1050 bool dbcc_en; 1051 u8 assoc_sta_cnt; /*number of associated nodes (sta or ap)*/ 1052 1053 u8 rfpath_tx_num; /* rf path - instead of rf_type -1T1R.... */ 1054 u8 rfpath_rx_num; 1055 #ifdef RTW_WKARD_SINGLE_PATH_RSSI 1056 enum rf_path cur_rx_rfpath; 1057 #endif 1058 1059 bool ext_pwr_lmt_en; 1060 struct rtw_tpu_ext_pwr_lmt_info rtw_tpu_ext_pwr_lmt_i[MAX_BAND_NUM];/*for phy0 & phy1 exetend power limit*/ 1061 1062 1063 #ifdef CONFIG_PCI_HCI /*TODO move to hal_info_t*/ 1064 /*interrupt*/ 1065 u32 int_array[4]; 1066 u32 int_mask[4]; 1067 u32 int_mask_default[4]; 1068 #endif /* CONFIG_PCI_HCI */ 1069 #ifdef CONFIG_SDIO_HCI /*TODO move to hal_info_t*/ 1070 u32 block_sz; 1071 1072 /*interrupt*/ 1073 /* 1074 * Change type of int_mask from u32 to unsigned long for bit operation 1075 * API, ex: _os_test_and_clear_bit() and _os_test_and_set_bit() . 1076 */ 1077 unsigned long int_mask; 1078 u32 int_mask_default; 1079 #endif /* CONFIG_SDIO_HCI */ 1080 1081 struct hal_int_array intr; 1082 1083 #ifdef RTW_PHL_BCN 1084 struct bcn_entry_pool bcn_pool; 1085 #endif 1086 struct rtw_trx_stat trx_stat; 1087 void *hal_priv;/*pointer to hal_info*/ 1088 void *drv_priv; /*drv priv*/ 1089 1090 void *csi_obj; 1091 void *bf_obj; 1092 void *snd_obj; 1093 1094 struct hal_mu_score_tbl bb_mu_score_tbl; 1095 bool csi_para_ctrl_sel; 1096 1097 struct btc_ctrl_t btc_ctrl; 1098 struct btc_fw_msg btc_msg; 1099 #ifdef RTW_WKARD_CCX_RPT_LIMIT_CTRL 1100 u8 spe_pkt_cnt_lmt; 1101 #endif 1102 }; 1103 1104 #define FL_CFG_OP_SET 0 1105 #define FL_CFG_OP_CLR 1 1106 #define FL_CFG_OP_INFO 2 1107 1108 #define FL_CFG_TYPE_LEVEL 0 1109 #define FL_CFG_TYPE_OUTPUT 1 1110 #define FL_CFG_TYPE_COMP 2 1111 #define FL_CFG_TYPE_COMP_EXT 3 1112 1113 #define FL_LV_OFF 0 1114 #define FL_LV_CRT 1 1115 #define FL_LV_SER 2 1116 #define FL_LV_WARN 3 1117 #define FL_LV_LOUD 4 1118 #define FL_LV_TR 5 1119 1120 #define FL_OP_UART BIT0 1121 #define FL_OP_C2H BIT1 1122 #define FL_OP_SNI BIT2 1123 1124 #define FL_COMP_VER BIT0 1125 #define FL_COMP_INIT BIT1 1126 #define FL_COMP_TASK BIT2 1127 #define FL_COMP_CNS BIT3 1128 #define FL_COMP_H2C BIT4 1129 #define FL_COMP_C2H BIT5 1130 #define FL_COMP_TX BIT6 1131 #define FL_COMP_RX BIT7 1132 #define FL_COMP_IPSEC BIT8 1133 #define FL_COMP_TIMER BIT9 1134 #define FL_COMP_DBGPKT BIT10 1135 #define FL_COMP_PS BIT11 1136 #define FL_COMP_BB BIT16 1137 1138 struct rtw_hal_fw_log_cfg { 1139 u32 level; 1140 u32 output; 1141 u32 comp; 1142 u32 comp_ext; 1143 }; 1144 1145 enum pkt_ofld_op_type { 1146 PKT_OFLD_ADD = 0, 1147 PKT_OFLD_DEL = 1, 1148 PKT_OFLD_READ = 2, 1149 PKT_OFLD_MAX 1150 }; 1151 1152 struct pkt_ofld_info { 1153 struct list_head req_q; 1154 u32 req_cnt; 1155 u8 id; 1156 }; 1157 1158 struct pkt_ofld_entry { 1159 struct list_head list; 1160 u16 macid; 1161 struct pkt_ofld_info pkt_info[PKT_OFLD_TYPE_MAX]; 1162 }; 1163 1164 enum rtw_c2h_cat { 1165 C2H_CAT_TEST = 0, 1166 C2H_CAT_MAC = 1, 1167 C2H_CAT_OUTSRC = 2, 1168 C2H_CAT_MAX = 3 1169 }; 1170 1171 enum rtw_c2h_clas { 1172 C2H_CLS_PHYDM_MIN = 0, 1173 C2H_CLS_PHYDM_MAX = 7, 1174 C2H_CLS_RF_MIN = 8, 1175 C2H_CLS_RF_MAX = 0xf, 1176 C2H_CLS_BTC_MIN = 0x10, 1177 C2H_CLS_BTC_MAX = 0x17, 1178 C2H_CLS_MAX = 0x18 1179 }; 1180 1181 #define C2H_CLS_MAC_MIN 0x00 1182 #define C2H_CLS_MAC_MAX 0xFF 1183 1184 enum rtw_hal_ps_pwr_req_src { 1185 HAL_BB_PWR_REQ = 0, 1186 HAL_RF_PWR_REQ = 1, 1187 HAL_MAC_PWR_REQ = 2, 1188 HAL_BTC_PWR_REQ = 3 1189 }; 1190 1191 struct rtw_hal_lps_info { 1192 u8 en; 1193 u16 macid; 1194 enum rtw_lps_listen_bcn_mode listen_bcn_mode; 1195 u8 awake_interval; 1196 enum rtw_lps_smart_ps_mode smart_ps_mode; 1197 }; 1198 1199 struct rtw_hal_ips_info { 1200 u8 en; 1201 u16 macid; 1202 }; 1203 1204 enum ps_pwr_state { 1205 PS_PWR_STATE_ACTIVE = 0, 1206 PS_PWR_STATE_BAND0_RFON = 1, 1207 PS_PWR_STATE_BAND1_RFON = 2, 1208 PS_PWR_STATE_BAND0_RFOFF = 3, 1209 PS_PWR_STATE_BAND1_RFOFF = 4, 1210 PS_PWR_STATE_CLK_GATED = 5, 1211 PS_PWR_STATE_PWR_GATED = 6, 1212 PS_PWR_STATE_MAX, 1213 }; 1214 1215 #ifdef CONFIG_PHL_DFS 1216 struct hal_dfs_rpt { 1217 u8 *dfs_ptr; 1218 u16 dfs_num; 1219 u8 phy_idx; /*phy0,phy1*/ 1220 }; 1221 #endif 1222 1223 #ifdef CONFIG_WOWLAN 1224 struct rtw_hal_wow_cfg { 1225 struct rtw_keep_alive_info *keep_alive_cfg; 1226 struct rtw_disc_det_info *disc_det_cfg; 1227 struct rtw_nlo_info *nlo_cfg; 1228 struct rtw_arp_ofld_info *arp_ofld_cfg; 1229 struct rtw_ndp_ofld_info *ndp_ofld_cfg; 1230 struct rtw_gtk_ofld_info *gtk_ofld_cfg; 1231 struct rtw_realwow_info *realwow_cfg; 1232 struct rtw_wow_wake_info *wow_wake_cfg; 1233 struct rtw_pattern_match_info *pattern_match_info; 1234 struct rtw_wow_gpio_info *wow_gpio; 1235 }; 1236 #endif /* CONFIG_WOWLAN */ 1237 1238 1239 enum hal_tsf_sync_act { 1240 HAL_TSF_SYNC_NOW_ONCE = 0, 1241 HAL_TSF_EN_SYNC_AUTO = 1, 1242 HAL_TSF_DIS_SYNC_AUTO = 2, 1243 }; 1244 1245 #ifdef CONFIG_RTW_ACS 1246 struct auto_chan_sel_report { 1247 u8 clm_ratio; 1248 u8 nhm_pwr; 1249 }; 1250 #endif 1251 1252 struct watchdog_nhm_report { 1253 u8 ccx_rpt_stamp; 1254 u8 ccx_rpt_result; 1255 s8 nhm_pwr_dbm; 1256 u8 nhm_ratio; 1257 }; 1258 1259 struct hal_mac_dbg_dump_cfg { 1260 u32 ss_dbg_0; 1261 u32 ss_dbg_1; 1262 u8 ss_dbg; 1263 u8 dle_dbg; 1264 u8 dmac_dbg; 1265 u8 cmac_dbg; 1266 u8 mac_dbg_port; 1267 u8 plersvd_dbg; 1268 u8 tx_flow_dbg; 1269 }; 1270 1271 #endif /*_HAL_DEF_H_*/ 1272