1 /****************************************************************************** 2 * 3 * Copyright(c) 2019 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef _HAL_API_DRV_H_ 16 #define _HAL_API_DRV_H_ 17 18 u32 rtw_hal_mac_coex_init(struct rtw_hal_com_t *hal_com, u8 pta_mode, u8 direction); 19 u32 rtw_hal_mac_coex_reg_read(struct rtw_hal_com_t *hal_com, u32 offset, u32 *value); 20 u32 rtw_hal_mac_coex_reg_write(struct rtw_hal_com_t *hal_com, u32 offset, u32 value); 21 u32 rtw_hal_mac_set_scoreboard(struct rtw_hal_com_t *hal_com, u32 *value); 22 u32 rtw_hal_mac_get_scoreboard(struct rtw_hal_com_t *hal_com, u32 *value); 23 u32 rtw_hal_mac_set_grant(struct rtw_hal_com_t *hal_com, u8 *value); 24 u32 rtw_hal_mac_get_grant(struct rtw_hal_com_t *hal_com, u8 *value); 25 u32 rtw_hal_mac_set_polluted(struct rtw_hal_com_t *hal_com, u8 band, u8 tx_val, u8 rx_val); 26 u32 rtw_hal_mac_set_tx_time(struct rtw_hal_com_t *hal_com, u8 is_btc, 27 u8 is_resume, u8 macid, u32 tx_time); 28 u32 rtw_hal_mac_get_tx_time(struct rtw_hal_com_t *hal_com, u8 macid, u32 *tx_time); 29 u32 rtw_hal_mac_set_tx_retry_limit(struct rtw_hal_com_t *hal_com, u8 is_btc, 30 u8 is_resume, u8 macid, u8 tx_retry); 31 u32 rtw_hal_mac_get_tx_retry_limit(struct rtw_hal_com_t *hal_com, u8 macid, 32 u8 *tx_retry); 33 u32 rtw_hal_mac_get_bt_polt_cnt(struct rtw_hal_com_t *hal_com, u8 band, 34 u16 *cnt); 35 u32 rtw_hal_mac_set_coex_ctrl(struct rtw_hal_com_t *hal_com, u32 val); 36 u32 rtw_hal_mac_get_coex_ctrl(struct rtw_hal_com_t *hal_com, u32 *val); 37 38 u32 rtw_hal_mac_send_h2c(struct rtw_hal_com_t *hal_com, 39 struct rtw_g6_h2c_hdr *hdr, u32 *pvalue); 40 41 u32 rtw_hal_read_rf_reg(struct rtw_hal_com_t *hal_com, 42 enum rf_path path, u32 addr, u32 mask); 43 44 bool rtw_hal_write_rf_reg(struct rtw_hal_com_t *hal_com, 45 enum rf_path path, u32 addr, u32 mask, u32 data); 46 47 u32 rtw_hal_bb_read_cr(struct rtw_hal_com_t *hal_com, u32 addr, u32 mask); 48 49 bool rtw_hal_bb_write_cr(struct rtw_hal_com_t *hal_com, u32 addr, u32 mask, 50 u32 data); 51 52 u32 rtw_hal_mac_write_msk_pwr_reg( 53 struct rtw_hal_com_t *hal_com, u8 band, u32 offset, u32 mask, u32 val); 54 55 u32 rtw_hal_mac_set_pwr_reg(struct rtw_hal_com_t *hal_com, u8 band, u32 offset, u32 val); 56 57 u32 rtw_hal_mac_get_pwr_reg(struct rtw_hal_com_t *hal_com, u8 band, u32 offset, u32 *val); 58 59 enum rtw_hal_status 60 rtw_hal_mac_get_log_efuse_size(struct rtw_hal_com_t *hal_com, u32 *val, 61 bool is_limited); 62 63 enum rtw_hal_status 64 rtw_hal_mac_read_log_efuse_map(struct rtw_hal_com_t *hal_com, u8 *map, 65 bool is_limited); 66 67 enum rtw_hal_status 68 rtw_hal_mac_write_log_efuse_map(struct rtw_hal_com_t *hal_com, 69 u8 *map, 70 u32 map_size, 71 u8 *mask, 72 u32 mask_size, 73 u8 *map_version, 74 u8 *mask_version, 75 u8 version_length, 76 u8 part, 77 bool is_limited); 78 79 enum rtw_hal_status 80 rtw_hal_mac_read_hidden_rpt(struct rtw_hal_com_t *hal_com); 81 82 enum rtw_hal_status 83 rtw_hal_mac_check_efuse_autoload(struct rtw_hal_com_t *hal_com, u8 *autoload); 84 85 enum rtw_hal_status 86 rtw_hal_mac_get_efuse_avl(struct rtw_hal_com_t *hal_com, u32 *val); 87 88 enum rtw_hal_status 89 rtw_hal_mac_get_efuse_size(struct rtw_hal_com_t *hal_com, u32 *val); 90 91 enum rtw_hal_status 92 rtw_hal_mac_get_efuse_mask_size(struct rtw_hal_com_t *hal_com, u32 *val, 93 bool is_limited); 94 95 enum rtw_hal_status 96 rtw_hal_mac_get_efuse_info(struct rtw_hal_com_t *hal_com, 97 u8 *efuse_map, enum rtw_efuse_info info_type, void *value, 98 u8 size, u8 map_valid); 99 100 enum rtw_hal_status 101 rtw_hal_mac_read_phy_efuse(struct rtw_hal_com_t *hal_com, 102 u32 addr, u32 size, u8 *value); 103 104 enum rtw_hal_status 105 rtw_hal_mac_read_bt_phy_efuse(struct rtw_hal_com_t *hal_com, 106 u32 addr, u32 size, u8 *value); 107 108 enum rtw_hal_status 109 rtw_hal_mac_get_xcap(struct rtw_hal_com_t *hal_com, u8 sc_xo, u32 *value); 110 111 enum rtw_hal_status 112 rtw_hal_mac_set_xcap(struct rtw_hal_com_t *hal_com, u8 sc_xo, u32 value); 113 114 enum rtw_hal_status 115 rtw_hal_mac_get_xsi(struct rtw_hal_com_t *hal_com, u8 offset, u8 *val); 116 117 enum rtw_hal_status 118 rtw_hal_mac_set_xsi(struct rtw_hal_com_t *hal_com, u8 offset, u8 val); 119 120 enum rtw_hal_status 121 rtw_hal_bb_get_efuse_info(struct rtw_hal_com_t *hal_com, 122 u8 *efuse_map, enum rtw_efuse_info info_type, void *value, 123 u8 size, u8 map_valid); 124 125 enum rtw_hal_status 126 rtw_hal_rf_get_efuse_info(struct rtw_hal_com_t *hal_com, 127 u8 *efuse_map, enum rtw_efuse_info info_type, void *value, 128 u8 size, u8 map_valid); 129 130 void 131 rtw_hal_rf_set_power_table_switch(struct rtw_hal_com_t *hal_com, 132 enum phl_phy_idx phy_idx, 133 u8 pwrbyrate_type, u8 pwrlmt_type); 134 135 void 136 rtw_hal_bb_set_tx_pow_ref(struct rtw_hal_com_t *hal_com, 137 enum phl_phy_idx phy_idx); 138 139 enum rtw_hal_status rtw_hal_rf_read_pwr_table( 140 struct rtw_hal_com_t *hal_com, u8 rf_path, u16 rate, 141 u8 bandwidth, u8 channel, u8 offset, u8 dcm, 142 u8 beamforming, s16 *get_item); 143 144 enum rtw_hal_status rtw_hal_rf_wl_tx_power_control( 145 struct rtw_hal_com_t *hal_com, 146 u32 tx_power_val); 147 148 enum rtw_hal_status rtw_hal_rf_ctrl_dbcc(struct rtw_hal_com_t *hal_com, 149 bool dbcc_en); 150 151 void rtw_hal_rf_tssi_scan_ch(struct rtw_hal_com_t *hal_com, 152 enum phl_phy_idx phy_idx, enum rf_path path); 153 154 enum rtw_hal_status 155 rtw_hal_btc_get_efuse_info(struct rtw_hal_com_t *hal_com, 156 u8 *efuse_map, enum rtw_efuse_info info_type, void *value, 157 u8 size, u8 map_valid); 158 159 enum rtw_hal_status rtw_hal_efuse_get_info(struct rtw_hal_com_t *hal_com, 160 enum rtw_efuse_info info_type, void *value, u8 size); 161 enum rtw_hal_status rtw_hal_notify_switch_band(void *hinfo, 162 enum band_type band, enum phl_phy_idx phy_idx); 163 164 enum rtw_hal_status rtw_hal_reset(struct rtw_hal_com_t *hal_com, 165 enum phl_phy_idx phy_idx, u8 band_idx, bool reset); 166 167 #ifndef CONFIG_BTCOEX 168 #define rtw_hal_btc_wl_rfk_ntfy(hal_com, phy_idx, rfk_type, rfk_process) 0 169 #else 170 u8 rtw_hal_btc_wl_rfk_ntfy(struct rtw_hal_com_t *hal_com, u8 phy_idx, u8 rfk_type, u8 rfk_process); 171 172 enum rtw_hal_status rtw_hal_btc_cfg_tx_1ss(struct rtw_hal_com_t *hal_com, 173 struct rtw_phl_com_t *phl_com, u8 rid, bool enable); 174 #endif 175 void rtw_hal_btc_power_on_ntfy(void *hinfo); 176 void rtw_hal_btc_power_off_ntfy(void *hinfo); 177 178 enum rtw_hal_status 179 rtw_hal_tx_pause(struct rtw_hal_com_t *hal_com, 180 u8 band_idx, bool tx_pause, enum tx_pause_rson rson); 181 182 enum rtw_hal_status 183 rtw_hal_mac_set_macid_pause(struct rtw_hal_com_t *hal_com, 184 u16 macid, bool pause); 185 186 enum rtw_hal_status 187 rtw_hal_mac_set_macid_grp_pause(struct rtw_hal_com_t *hal_com, 188 u32 *macid_arr, u8 macid_arr_sz, bool pause); 189 190 u32 191 rtw_hal_mac_lamode_trig(struct rtw_hal_com_t *hal_com, u8 trig); 192 193 enum rtw_hal_status 194 rtw_hal_mac_lamode_cfg_buf(struct rtw_hal_com_t *hal_com, u8 buf_sel, 195 u32 *addr_start, u32 *addr_end); 196 197 enum rtw_hal_status 198 rtw_hal_mac_lamode_cfg(struct rtw_hal_com_t *hal_com, u8 func_en, 199 u8 restart_en, u8 timeout_en, u8 timeout_val, 200 u8 data_loss_imr, u8 la_tgr_tu_sel, u8 tgr_time_val); 201 202 enum rtw_hal_status 203 rtw_hal_mac_get_lamode_st(struct rtw_hal_com_t *hal_com, u8 *la_state, 204 u16 *la_finish_addr, bool *la_round_up, 205 bool *la_loss_data); 206 207 void 208 rtw_hal_mac_get_buffer_data(struct rtw_hal_com_t *hal_com, u32 strt_addr, 209 u8 *buf, u32 len, u32 dbg_path); 210 211 enum rtw_hal_status 212 rtw_hal_fw_log_cfg(void *hal, u8 op, u8 type, u32 value); 213 214 215 /* HALBB APIs for HW TX */ 216 217 enum rtw_hal_status 218 rtw_hal_bb_set_plcp_tx(struct rtw_hal_com_t *hal_com, 219 struct mp_plcp_param_t *plcp_tx_struct, 220 struct mp_usr_plcp_gen_in *plcp_usr_info, 221 enum phl_phy_idx plcp_phy_idx, 222 u8 *plcp_sts); 223 224 enum rtw_hal_status 225 rtw_hal_bb_set_pmac_cont_tx(struct rtw_hal_com_t *hal_com, u8 enable, u8 is_cck, 226 enum phl_phy_idx phy_idx); 227 228 enum rtw_hal_status 229 rtw_hal_bb_set_pmac_packet_tx(struct rtw_hal_com_t *hal_com, u8 enable, 230 u8 is_cck, u16 tx_cnt ,u16 period, u16 tx_time, 231 enum phl_phy_idx phy_idx); 232 233 enum rtw_hal_status 234 rtw_hal_bb_set_pmac_fw_trigger_tx(struct rtw_hal_com_t *hal_com, u8 enable, 235 u8 is_cck, u16 tx_cnt, u8 tx_duty, 236 enum phl_phy_idx phy_idx); 237 238 enum rtw_hal_status 239 rtw_hal_bb_set_dpd_bypass(struct rtw_hal_com_t *hal_com, bool pdp_bypass, 240 enum phl_phy_idx phy_idx); 241 242 enum rtw_hal_status 243 rtw_hal_bb_set_power(struct rtw_hal_com_t *hal_com, s16 power_dbm, 244 enum phl_phy_idx phy_idx); 245 246 enum rtw_hal_status 247 rtw_hal_bb_get_power(struct rtw_hal_com_t *hal_com, s16 *power_dbm, 248 enum phl_phy_idx phy_idx); 249 250 enum rtw_hal_status 251 rtw_hal_bb_ctrl_btg(struct rtw_hal_com_t *hal_com, bool btg); 252 253 enum rtw_hal_status 254 rtw_hal_bb_ctrl_btc_preagc(struct rtw_hal_com_t *hal_com, bool bt_en); 255 256 enum rtw_hal_status 257 rtw_hal_bb_cfg_rx_path(struct rtw_hal_com_t *hal_com, u8 rx_path); 258 259 enum rtw_hal_status 260 rtw_hal_bb_cfg_tx_path(struct rtw_hal_com_t *hal_com, u8 tx_path); 261 262 /* mode: 0 = tmac, 1 = pmac */ 263 enum rtw_hal_status 264 rtw_hal_bb_tx_mode_switch(struct rtw_hal_com_t *hal_com, 265 enum phl_phy_idx phy_idx, 266 u8 mode); 267 /* HALBB APIs for HW TX END*/ 268 /*@--------------------------[Prptotype]-------------------------------------*/ 269 /** 270 * rtw_hal_bb_get_txsc input arguments: 271 * @hal_com: hal com info 272 * @pri_ch: Spec-defined primary channel index 273 * @central_ch: Spec-defined central channel index 274 * @cbw: Channel BW 275 * @dbw: Data BW 276 */ 277 u8 rtw_hal_bb_get_txsc(struct rtw_hal_com_t *hal_com, u8 pri_ch, 278 u8 central_ch, enum channel_width cbw, enum channel_width dbw); 279 280 void rtw_hal_bb_nhm_mntr_result(struct rtw_hal_com_t *hal_com, void *rpt, enum phl_phy_idx phy_idx); 281 282 bool rtw_hal_query_regulation(void *phl, struct rtw_regulation_info *info); 283 284 enum rtw_hal_status 285 rtw_hal_mac_set_tpu_mode(struct rtw_hal_com_t *hal_com, 286 enum rtw_tpu_op_mode op_mode_new, u8 band); 287 enum rtw_hal_status 288 rtw_hal_mac_write_pwr_limit_rua_reg(struct rtw_hal_com_t *hal_com, u8 band); 289 enum rtw_hal_status 290 rtw_hal_mac_write_pwr_limit_reg(struct rtw_hal_com_t *hal_com, u8 band); 291 enum rtw_hal_status 292 rtw_hal_mac_write_pwr_by_rate_reg(struct rtw_hal_com_t *hal_com, u8 band); 293 294 enum rtw_hal_status 295 rtw_hal_mac_get_efuse_bt_avl(struct rtw_hal_com_t *hal_com, u32 *val); 296 297 enum rtw_hal_status 298 rtw_hal_mac_get_efuse_bt_size(struct rtw_hal_com_t *hal_com, u32 *val); 299 300 enum rtw_hal_status 301 rtw_hal_mac_get_efuse_bt_mask_size(struct rtw_hal_com_t *hal_com, u32 *val); 302 303 enum rtw_hal_status 304 rtw_hal_mac_get_log_efuse_bt_size(struct rtw_hal_com_t *hal_com, u32 *val); 305 306 enum rtw_hal_status 307 rtw_hal_mac_read_log_efuse_bt_map(struct rtw_hal_com_t *hal_com, u8 *map); 308 309 enum rtw_hal_status 310 rtw_hal_mac_write_log_efuse_bt_map(struct rtw_hal_com_t *hal_com, 311 u8 *map, 312 u32 map_size, 313 u8 *mask, 314 u32 mask_size); 315 316 317 enum rtw_hal_status 318 rtw_hal_bb_backup_info(struct rtw_hal_com_t *hal_com, u8 cur_phy_idx); 319 320 enum rtw_hal_status 321 rtw_hal_bb_restore_info(struct rtw_hal_com_t *hal_com, u8 cur_phy_idx); 322 323 enum rtw_hal_status 324 rtw_hal_bb_tssi_bb_reset(struct rtw_hal_com_t *hal_com); 325 326 enum rtw_hal_status 327 rtw_hal_bb_query_rainfo(void *hal, struct rtw_hal_stainfo_t *hal_sta, 328 struct rtw_phl_rainfo *phl_rainfo); 329 enum rtw_hal_status rtw_hal_bb_ctrl_rx_cca(struct rtw_hal_com_t *hal_com, 330 bool cca_en, enum phl_phy_idx phy_idx); 331 332 enum rtw_hal_status 333 rtw_hal_mac_write_pwr_ofst_mode(struct rtw_hal_com_t *hal_com, u8 band); 334 enum rtw_hal_status 335 rtw_hal_mac_write_pwr_ofst_bw(struct rtw_hal_com_t *hal_com, u8 band); 336 enum rtw_hal_status 337 rtw_hal_mac_write_pwr_ref_reg(struct rtw_hal_com_t *hal_com, u8 band); 338 enum rtw_hal_status 339 rtw_hal_mac_write_pwr_limit_en(struct rtw_hal_com_t *hal_com, u8 band); 340 enum rtw_hal_status 341 rtw_hal_mac_set_pwr_lmt_en_val(struct rtw_hal_com_t *hal_com, u8 band, bool en_val); 342 bool 343 rtw_hal_mac_get_pwr_lmt_en_val(struct rtw_hal_com_t *hal_com, u8 band); 344 enum rtw_hal_status 345 rtw_hal_mac_write_pwr_limit_rua_reg(struct rtw_hal_com_t *hal_com, u8 band); 346 enum rtw_hal_status 347 rtw_hal_mac_write_pwr_limit_reg(struct rtw_hal_com_t *hal_com, u8 band); 348 enum rtw_hal_status 349 rtw_hal_mac_write_pwr_by_rate_reg(struct rtw_hal_com_t *hal_com, u8 band); 350 enum rtw_hal_status 351 rtw_hal_mac_read_efuse_bt_hidden(struct rtw_hal_com_t *hal_com, u32 addr, u32 size, u8 *val); 352 353 enum rtw_hal_status 354 rtw_hal_mac_write_efuse_bt_hidden(struct rtw_hal_com_t *hal_com, u32 addr, u8 val); 355 356 enum rtw_hal_status 357 rtw_hal_mac_ax_init_bf_role(struct rtw_hal_com_t *hal_com, u8 bf_role, u8 band); 358 359 enum rtw_hal_status 360 rtw_hal_mac_ax_deinit_bfee(struct rtw_hal_com_t *hal_com, u8 band); 361 362 void rtw_hal_bb_gpio_setting_all(struct rtw_hal_com_t *hal_com, u8 rfe_idx); 363 364 void rtw_hal_bb_gpio_setting(struct rtw_hal_com_t *hal_com, u8 gpio_idx, u8 path, 365 bool inv, u8 src); 366 367 enum rtw_hal_status 368 rtw_hal_mac_set_gpio_func(struct rtw_hal_com_t *hal_com, u8 func, s8 gpio_cfg); 369 370 enum rtw_phl_status 371 rtw_hal_cmd_notify(struct rtw_phl_com_t *phl_com, 372 enum phl_msg_evt_id event, 373 void *hal_cmd, 374 u8 hw_idx); 375 #ifdef CONFIG_FW_IO_OFLD_SUPPORT 376 enum rtw_hal_status rtw_hal_mac_add_cmd_ofld(struct rtw_hal_com_t *hal_com, struct rtw_mac_cmd *cmd); 377 #endif 378 379 void rtw_hal_bb_env_rpt(struct rtw_hal_com_t *hal_com, struct rtw_env_report *env_rpt, 380 enum phl_phy_idx phy_indx); 381 382 void rtw_hal_bb_set_pow_patten_sharp(struct rtw_hal_com_t *hal_com, u8 channel, u8 is_cck, u8 sharp_id, enum phl_phy_idx phy_idx); 383 384 #endif /*_HAL_API_DRV_H_*/ 385