1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2019 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef _RTW_XMIT_H_ 16 #define _RTW_XMIT_H_ 17 18 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) 19 #ifdef CONFIG_TX_AGGREGATION 20 /* #define SDIO_TX_AGG_MAX 5 */ 21 #else 22 #define SDIO_TX_AGG_MAX 1 23 #endif 24 25 #if defined CONFIG_SDIO_HCI 26 #define SDIO_TX_DIV_NUM (2) 27 #endif 28 #endif 29 30 #if 0 /*CONFIG_CORE_XMITBUF*/ 31 #ifdef CONFIG_PCI_HCI 32 #define XMITBUF_ALIGN_SZ 4 33 #else 34 #ifdef USB_XMITBUF_ALIGN_SZ 35 #define XMITBUF_ALIGN_SZ (USB_XMITBUF_ALIGN_SZ) 36 #else 37 #define XMITBUF_ALIGN_SZ 512 38 #endif 39 #endif 40 41 #define MAX_CMDBUF_SZ (5120) /* (4096) */ 42 #endif 43 44 #define MAX_BEACON_LEN 512 45 46 #define MAX_NUMBLKS (1) 47 48 #define XMIT_VO_QUEUE (0) 49 #define XMIT_VI_QUEUE (1) 50 #define XMIT_BE_QUEUE (2) 51 #define XMIT_BK_QUEUE (3) 52 53 #define VO_QUEUE_INX 0 54 #define VI_QUEUE_INX 1 55 #define BE_QUEUE_INX 2 56 #define BK_QUEUE_INX 3 57 #define BCN_QUEUE_INX 4 58 #define MGT_QUEUE_INX 5 59 #define HIGH_QUEUE_INX 6 60 #define TXCMD_QUEUE_INX 7 61 62 #define HW_QUEUE_ENTRY 8 63 64 65 #ifdef RTW_PHL_TX 66 #define RTW_MAX_FRAG_NUM 10 //max scatter number of a packet to xmit 67 #define RTW_MAX_WL_HEAD 100 68 #define RTW_MAX_WL_TAIL 100 69 #define RTW_SZ_LLC (SNAP_SIZE + sizeof(u16)) 70 #define RTW_SZ_FCS 4 71 #endif 72 73 #define WEP_IV(pattrib_iv, dot11txpn, keyidx)\ 74 do {\ 75 dot11txpn.val = (dot11txpn.val == 0xffffff) ? 0 : (dot11txpn.val + 1);\ 76 pattrib_iv[0] = dot11txpn._byte_.TSC0;\ 77 pattrib_iv[1] = dot11txpn._byte_.TSC1;\ 78 pattrib_iv[2] = dot11txpn._byte_.TSC2;\ 79 pattrib_iv[3] = ((keyidx & 0x3)<<6);\ 80 } while (0) 81 82 83 #define TKIP_IV(pattrib_iv, dot11txpn, keyidx)\ 84 do {\ 85 dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val + 1);\ 86 pattrib_iv[0] = dot11txpn._byte_.TSC1;\ 87 pattrib_iv[1] = (dot11txpn._byte_.TSC1 | 0x20) & 0x7f;\ 88 pattrib_iv[2] = dot11txpn._byte_.TSC0;\ 89 pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\ 90 pattrib_iv[4] = dot11txpn._byte_.TSC2;\ 91 pattrib_iv[5] = dot11txpn._byte_.TSC3;\ 92 pattrib_iv[6] = dot11txpn._byte_.TSC4;\ 93 pattrib_iv[7] = dot11txpn._byte_.TSC5;\ 94 } while (0) 95 96 #define AES_IV(pattrib_iv, dot11txpn, keyidx)\ 97 do {\ 98 dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val + 1);\ 99 pattrib_iv[0] = dot11txpn._byte_.TSC0;\ 100 pattrib_iv[1] = dot11txpn._byte_.TSC1;\ 101 pattrib_iv[2] = 0;\ 102 pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\ 103 pattrib_iv[4] = dot11txpn._byte_.TSC2;\ 104 pattrib_iv[5] = dot11txpn._byte_.TSC3;\ 105 pattrib_iv[6] = dot11txpn._byte_.TSC4;\ 106 pattrib_iv[7] = dot11txpn._byte_.TSC5;\ 107 } while (0) 108 109 #define GCMP_IV(a, b, c) AES_IV(a, b, c) 110 111 /* Check if AMPDU Tx is supported or not. If it is supported, 112 * it need to check "amsdu in ampdu" is supported or not. 113 * (ampdu_en, amsdu_ampdu_en) = 114 * (0, x) : AMPDU is not enable, but AMSDU is valid to send. 115 * (1, 0) : AMPDU is enable, AMSDU in AMPDU is not enable. So, AMSDU is not valid to send. 116 * (1, 1) : AMPDU and AMSDU in AMPDU are enable. So, AMSDU is valid to send. 117 */ 118 #define IS_AMSDU_AMPDU_NOT_VALID(pattrib)\ 119 ((pattrib->ampdu_en == _TRUE) && (pattrib->amsdu_ampdu_en == _FALSE)) 120 121 #define IS_AMSDU_AMPDU_VALID(pattrib)\ 122 !((pattrib->ampdu_en == _TRUE) && (pattrib->amsdu_ampdu_en == _FALSE)) 123 124 #define HWXMIT_ENTRY 4 125 126 /* For Buffer Descriptor ring architecture */ 127 #if defined(BUF_DESC_ARCH) || defined(CONFIG_TRX_BD_ARCH) 128 #define TX_BUFFER_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */ 129 #endif 130 131 /*GEORGIA_TODO_FIXIT_MOVE_TO_HAL*/ 132 #if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C) 133 #define TXDESC_SIZE 48 /* HALMAC_TX_DESC_SIZE_8822B */ 134 #elif defined(CONFIG_RTL8821C) 135 #define TXDESC_SIZE 48 /* HALMAC_TX_DESC_SIZE_8821C */ 136 #elif defined(CONFIG_RTL8814B) 137 #define TXDESC_SIZE (16 + 32) 138 #else 139 #define TXDESC_SIZE 32 /* old IC (ex: 8188E) */ 140 #endif 141 142 #ifdef CONFIG_TX_EARLY_MODE 143 #define EARLY_MODE_INFO_SIZE 8 144 #endif 145 146 147 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) 148 #define TXDESC_OFFSET TXDESC_SIZE 149 #endif 150 151 #ifdef CONFIG_USB_HCI 152 #ifdef USB_PACKET_OFFSET_SZ 153 #define PACKET_OFFSET_SZ (USB_PACKET_OFFSET_SZ) 154 #else 155 #define PACKET_OFFSET_SZ (8) 156 #endif 157 #define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ) 158 #endif 159 160 #ifdef CONFIG_PCI_HCI 161 #if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_TRX_BD_ARCH) 162 /* this section is defined for buffer descriptor ring architecture */ 163 #define TX_WIFI_INFO_SIZE (TXDESC_SIZE) /* it may add 802.11 hdr or others... */ 164 /* tx desc and payload are in the same buf */ 165 #define TXDESC_OFFSET (TX_WIFI_INFO_SIZE) 166 #else 167 /* tx desc and payload are NOT in the same buf */ 168 #define TXDESC_OFFSET (0) 169 /* 8188ee/8723be/8812ae/8821ae has extra PCI DMA info in tx desc */ 170 #endif 171 #endif /* CONFIG_PCI_HCI */ 172 173 #ifdef RTW_PHL_TX 174 #ifdef TXDESC_OFFSET 175 #undef TXDESC_OFFSET 176 #endif 177 #define TXDESC_OFFSET (0) 178 #endif 179 180 #ifdef RTW_PHL_TX 181 enum CORE_TX_TYPE { 182 RTW_TX_OS = 0, 183 RTW_TX_OS_MAC80211, 184 RTW_TX_DRV_MGMT, 185 }; 186 #endif 187 188 enum TXDESC_SC { 189 SC_DONT_CARE = 0x00, 190 SC_UPPER = 0x01, 191 SC_LOWER = 0x02, 192 SC_DUPLICATE = 0x03 193 }; 194 195 #ifdef CONFIG_PCI_HCI 196 #ifndef CONFIG_TRX_BD_ARCH /* CONFIG_TRX_BD_ARCH doesn't need this */ 197 #define TXDESC_64_BYTES 198 #endif 199 #endif 200 201 /*GEORGIA_TODO_FIXIT_IC_DEPENDENCE*/ 202 #ifdef CONFIG_TRX_BD_ARCH 203 struct tx_buf_desc { 204 #ifdef CONFIG_64BIT_DMA 205 #define TX_BUFFER_SEG_SIZE 4 /* in unit of DWORD */ 206 #else 207 #define TX_BUFFER_SEG_SIZE 2 /* in unit of DWORD */ 208 #endif 209 unsigned int dword[TX_BUFFER_SEG_SIZE * (2 << TX_BUFFER_SEG_NUM)]; 210 } __packed; 211 #elif (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C)) && defined(CONFIG_PCI_HCI) /* 8192ee or 8814ae */ 212 /* 8192EE_TODO */ 213 struct tx_desc { 214 unsigned int txdw0; 215 unsigned int txdw1; 216 unsigned int txdw2; 217 unsigned int txdw3; 218 unsigned int txdw4; 219 unsigned int txdw5; 220 unsigned int txdw6; 221 unsigned int txdw7; 222 }; 223 #else 224 struct tx_desc { 225 unsigned int txdw0; 226 unsigned int txdw1; 227 unsigned int txdw2; 228 unsigned int txdw3; 229 unsigned int txdw4; 230 unsigned int txdw5; 231 unsigned int txdw6; 232 unsigned int txdw7; 233 234 #if defined(TXDESC_40_BYTES) || defined(TXDESC_64_BYTES) 235 unsigned int txdw8; 236 unsigned int txdw9; 237 #endif /* TXDESC_40_BYTES */ 238 239 #ifdef TXDESC_64_BYTES 240 unsigned int txdw10; 241 unsigned int txdw11; 242 243 /* 2008/05/15 MH Because PCIE HW memory R/W 4K limit. And now, our descriptor */ 244 /* size is 40 bytes. If you use more than 102 descriptor( 103*40>4096), HW will execute */ 245 /* memoryR/W CRC error. And then all DMA fetch will fail. We must decrease descriptor */ 246 /* number or enlarge descriptor size as 64 bytes. */ 247 unsigned int txdw12; 248 unsigned int txdw13; 249 unsigned int txdw14; 250 unsigned int txdw15; 251 #endif 252 }; 253 #endif 254 255 #ifndef CONFIG_TRX_BD_ARCH 256 union txdesc { 257 struct tx_desc txdesc; 258 unsigned int value[TXDESC_SIZE >> 2]; 259 }; 260 #endif 261 262 #ifdef CONFIG_PCI_HCI 263 #define PCI_MAX_TX_QUEUE_COUNT 8 /* == HW_QUEUE_ENTRY */ 264 265 struct rtw_tx_ring { 266 unsigned char qid; 267 #ifdef CONFIG_TRX_BD_ARCH 268 struct tx_buf_desc *buf_desc; 269 #else 270 struct tx_desc *desc; 271 #endif 272 dma_addr_t dma; 273 unsigned int idx; 274 unsigned int entries; 275 _queue queue; 276 u32 qlen; 277 #ifdef CONFIG_TRX_BD_ARCH 278 u16 hw_rp_cache; 279 #endif 280 }; 281 282 #ifdef DBG_TXBD_DESC_DUMP 283 284 #define TX_BAK_FRMAE_CNT 10 285 #define TX_BAK_DESC_LEN 48 /* byte */ 286 #define TX_BAK_DATA_LEN 30 /* byte */ 287 288 struct rtw_tx_desc_backup { 289 int tx_bak_rp; 290 int tx_bak_wp; 291 u8 tx_bak_desc[TX_BAK_DESC_LEN]; 292 u8 tx_bak_data_hdr[TX_BAK_DATA_LEN]; 293 u8 tx_desc_size; 294 }; 295 #endif 296 #endif 297 298 struct hw_xmit { 299 /* _lock xmit_lock; */ 300 /* _list pending; */ 301 _queue *sta_queue; 302 /* struct hw_txqueue *phwtxqueue; */ 303 /* sint txcmdcnt; */ 304 int accnt; 305 }; 306 307 308 #if 1 //def RTW_PHL_TX 309 struct pkt_attrib { 310 //updated by rtw_core_update_xmitframe 311 u32 sz_payload_per_frag; 312 313 u32 sz_wlan_head; 314 u32 sz_wlan_tail; 315 316 u32 sz_phl_head; 317 u32 sz_phl_tail; 318 319 u8 nr_frags; 320 u32 frag_len; 321 u32 frag_datalen; 322 #ifdef CONFIG_CORE_TXSC 323 u32 frag_len_txsc; 324 #endif 325 326 //updated by 327 u16 ether_type; 328 329 u8 src[ETH_ALEN]; 330 u8 dst[ETH_ALEN]; 331 u8 ta[ETH_ALEN]; 332 u8 ra[ETH_ALEN]; 333 334 u16 pkt_hdrlen; /* the original 802.3 pkt header len */ 335 u32 sz_payload; 336 337 u8 dhcp_pkt; 338 u8 icmp_pkt; 339 u8 hipriority_pkt; /* high priority packet */ 340 341 //WLAN HDR 342 u16 hdrlen; /* the WLAN Header Len */ 343 u8 type; 344 u8 subtype; 345 u8 qos_en; 346 u16 seqnum; 347 u8 ampdu_en;/* tx ampdu enable */ 348 u8 ack_policy; 349 u8 amsdu; 350 u8 mdata;/* more data bit */ 351 u8 eosp; 352 u8 priority; 353 354 //Security 355 u8 bswenc; 356 /* 357 * encrypt 358 * indicate the encrypt algorithm, ref: enum security_type. 359 * 0: indicate no encrypt. 360 */ 361 u8 encrypt; 362 u8 iv_len; 363 u8 icv_len; 364 u8 iv[18]; 365 u8 icv[16]; 366 u8 key_idx; 367 union Keytype dot11tkiptxmickey; 368 /* union Keytype dot11tkiprxmickey; */ 369 union Keytype dot118021x_UncstKey; 370 371 //updated by rtw_core_update_xmitframe 372 u8 hw_ssn_sel; /* for HW_SEQ0,1,2,3 */ 373 u32 pktlen; /* the original 802.3 pkt raw_data len (not include ether_hdr data) */ 374 u32 last_txcmdsz; 375 376 #if defined(CONFIG_CONCURRENT_MODE) 377 u8 bmc_camid; 378 #endif 379 380 381 382 u8 mac_id; 383 u8 vcs_mode; /* virtual carrier sense method */ 384 #ifdef CONFIG_RTW_WDS 385 u8 wds; 386 #endif 387 #ifdef CONFIG_RTW_MESH 388 u8 mda[ETH_ALEN]; /* mesh da */ 389 u8 msa[ETH_ALEN]; /* mesh sa */ 390 u8 meshctrl_len; /* Length of Mesh Control field */ 391 u8 mesh_frame_mode; 392 #if CONFIG_RTW_MESH_DATA_BMC_TO_UC 393 u8 mb2u; 394 #endif 395 u8 mfwd_ttl; 396 u32 mseq; 397 #endif 398 #ifdef CONFIG_TCP_CSUM_OFFLOAD_TX 399 u8 hw_csum; 400 #endif 401 402 403 u8 ht_en; 404 u8 raid;/* rate adpative id */ 405 u8 bwmode; 406 u8 ch_offset;/* PRIME_CHNL_OFFSET */ 407 u8 sgi;/* short GI */ 408 u8 ampdu_spacing; /* ampdu_min_spacing for peer sta's rx */ 409 u8 amsdu_ampdu_en;/* tx amsdu in ampdu enable */ 410 u8 pctrl;/* per packet txdesc control enable */ 411 u8 triggered;/* for ap mode handling Power Saving sta */ 412 u8 qsel; 413 u8 order;/* order bit */ 414 u8 rate; 415 u8 intel_proxim; 416 u8 retry_ctrl; 417 u8 mbssid; 418 u8 ldpc; 419 u8 stbc; 420 #ifdef CONFIG_WMMPS_STA 421 u8 trigger_frame; 422 #endif /* CONFIG_WMMPS_STA */ 423 424 struct sta_info *psta; 425 426 u8 rtsen; 427 u8 cts2self; 428 u8 hw_rts_en; 429 430 #ifdef CONFIG_TDLS 431 u8 direct_link; 432 struct sta_info *ptdls_sta; 433 #endif /* CONFIG_TDLS */ 434 u8 key_type; 435 436 437 438 #ifdef CONFIG_BEAMFORMING 439 u16 txbf_p_aid;/*beamforming Partial_AID*/ 440 u16 txbf_g_id;/*beamforming Group ID*/ 441 442 /* 443 * 2'b00: Unicast NDPA 444 * 2'b01: Broadcast NDPA 445 * 2'b10: Beamforming Report Poll 446 * 2'b11: Final Beamforming Report Poll 447 */ 448 u8 bf_pkt_type; 449 #endif 450 u8 wdinfo_en;/*FPGA_test*/ 451 u8 dma_ch;/*FPGA_test*/ 452 }; 453 #endif 454 455 #if 0 //ndef RTW_PHL_TX 456 /* reduce size */ 457 struct pkt_attrib { 458 u8 type; 459 u8 subtype; 460 u8 bswenc; 461 u8 dhcp_pkt; 462 u16 ether_type; 463 u16 seqnum; 464 u8 hw_ssn_sel; /* for HW_SEQ0,1,2,3 */ 465 u16 pkt_hdrlen; /* the original 802.3 pkt header len */ 466 u16 hdrlen; /* the WLAN Header Len */ 467 u32 pktlen; /* the original 802.3 pkt raw_data len (not include ether_hdr data) */ 468 u32 last_txcmdsz; 469 u8 nr_frags; 470 u8 encrypt; /* when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith */ 471 #if defined(CONFIG_CONCURRENT_MODE) 472 u8 bmc_camid; 473 #endif 474 u8 iv_len; 475 u8 icv_len; 476 u8 iv[18]; 477 u8 icv[16]; 478 u8 priority; 479 u8 ack_policy; 480 u8 mac_id; 481 u8 vcs_mode; /* virtual carrier sense method */ 482 u8 dst[ETH_ALEN]; 483 u8 src[ETH_ALEN]; 484 u8 ta[ETH_ALEN]; 485 u8 ra[ETH_ALEN]; 486 #ifdef CONFIG_RTW_MESH 487 u8 mda[ETH_ALEN]; /* mesh da */ 488 u8 msa[ETH_ALEN]; /* mesh sa */ 489 u8 meshctrl_len; /* Length of Mesh Control field */ 490 u8 mesh_frame_mode; 491 #if CONFIG_RTW_MESH_DATA_BMC_TO_UC 492 u8 mb2u; 493 #endif 494 u8 mfwd_ttl; 495 u32 mseq; 496 #endif 497 #ifdef CONFIG_TCP_CSUM_OFFLOAD_TX 498 u8 hw_csum; 499 #endif 500 u8 key_idx; 501 u8 qos_en; 502 u8 ht_en; 503 u8 raid;/* rate adpative id */ 504 u8 bwmode; 505 u8 ch_offset;/* PRIME_CHNL_OFFSET */ 506 u8 sgi;/* short GI */ 507 u8 ampdu_en;/* tx ampdu enable */ 508 u8 ampdu_spacing; /* ampdu_min_spacing for peer sta's rx */ 509 u8 amsdu; 510 u8 amsdu_ampdu_en;/* tx amsdu in ampdu enable */ 511 u8 mdata;/* more data bit */ 512 u8 pctrl;/* per packet txdesc control enable */ 513 u8 triggered;/* for ap mode handling Power Saving sta */ 514 u8 qsel; 515 u8 order;/* order bit */ 516 u8 eosp; 517 u8 rate; 518 u8 intel_proxim; 519 u8 retry_ctrl; 520 u8 mbssid; 521 u8 ldpc; 522 u8 stbc; 523 #ifdef CONFIG_WMMPS_STA 524 u8 trigger_frame; 525 #endif /* CONFIG_WMMPS_STA */ 526 527 struct sta_info *psta; 528 529 u8 rtsen; 530 u8 cts2self; 531 union Keytype dot11tkiptxmickey; 532 /* union Keytype dot11tkiprxmickey; */ 533 union Keytype dot118021x_UncstKey; 534 535 #ifdef CONFIG_TDLS 536 u8 direct_link; 537 struct sta_info *ptdls_sta; 538 #endif /* CONFIG_TDLS */ 539 u8 key_type; 540 541 u8 icmp_pkt; 542 u8 hipriority_pkt; /* high priority packet */ 543 544 #ifdef CONFIG_BEAMFORMING 545 u16 txbf_p_aid;/*beamforming Partial_AID*/ 546 u16 txbf_g_id;/*beamforming Group ID*/ 547 548 /* 549 * 2'b00: Unicast NDPA 550 * 2'b01: Broadcast NDPA 551 * 2'b10: Beamforming Report Poll 552 * 2'b11: Final Beamforming Report Poll 553 */ 554 u8 bf_pkt_type; 555 #endif 556 u8 wdinfo_en;/*FPGA_test*/ 557 u8 dma_ch;/*FPGA_test*/ 558 }; 559 #endif 560 561 #ifdef CONFIG_RTW_WDS 562 #define XATTRIB_GET_WDS(xattrib) ((xattrib)->wds) 563 #else 564 #define XATTRIB_GET_WDS(xattrib) 0 565 #endif 566 567 #ifdef CONFIG_RTW_MESH 568 #define XATTRIB_GET_MCTRL_LEN(xattrib) ((xattrib)->meshctrl_len) 569 #else 570 #define XATTRIB_GET_MCTRL_LEN(xattrib) 0 571 #endif 572 573 #ifdef CONFIG_TX_AMSDU 574 enum { 575 RTW_AMSDU_TIMER_UNSET = 0, 576 RTW_AMSDU_TIMER_SETTING, 577 RTW_AMSDU_TIMER_TIMEOUT, 578 }; 579 #endif 580 581 #define WLANHDR_OFFSET 64 582 583 #define NULL_FRAMETAG (0x0) 584 #define DATA_FRAMETAG 0x01 585 #define L2_FRAMETAG 0x02 586 #define MGNT_FRAMETAG 0x03 587 #define AMSDU_FRAMETAG 0x04 588 589 #define EII_FRAMETAG 0x05 590 #define IEEE8023_FRAMETAG 0x06 591 592 #define MP_FRAMETAG 0x07 593 594 #define TXAGG_FRAMETAG 0x08 595 596 enum { 597 XMITBUF_DATA = 0, 598 XMITBUF_MGNT = 1, 599 XMITBUF_CMD = 2, 600 }; 601 602 bool rtw_xmit_ac_blocked(_adapter *adapter); 603 604 struct submit_ctx { 605 systime submit_time; /* */ 606 u32 timeout_ms; /* <0: not synchronous, 0: wait forever, >0: up to ms waiting */ 607 int status; /* status for operation */ 608 _completion done; 609 }; 610 611 enum { 612 RTW_SCTX_SUBMITTED = -1, 613 RTW_SCTX_DONE_SUCCESS = 0, 614 RTW_SCTX_DONE_UNKNOWN, 615 RTW_SCTX_DONE_TIMEOUT, 616 RTW_SCTX_DONE_BUF_ALLOC, 617 RTW_SCTX_DONE_BUF_FREE, 618 RTW_SCTX_DONE_WRITE_PORT_ERR, 619 RTW_SCTX_DONE_TX_DESC_NA, 620 RTW_SCTX_DONE_TX_DENY, 621 RTW_SCTX_DONE_CCX_PKT_FAIL, 622 RTW_SCTX_DONE_DRV_STOP, 623 RTW_SCTX_DONE_DEV_REMOVE, 624 RTW_SCTX_DONE_CMD_ERROR, 625 RTW_SCTX_DONE_CMD_DROP, 626 RTX_SCTX_CSTR_WAIT_RPT2, 627 }; 628 629 630 void rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms); 631 int rtw_sctx_wait(struct submit_ctx *sctx, const char *msg); 632 void rtw_sctx_done_err(struct submit_ctx **sctx, int status); 633 void rtw_sctx_done(struct submit_ctx **sctx); 634 635 #if 0 /*CONFIG_CORE_XMITBUF*/ 636 struct xmit_buf { 637 _list list; 638 639 _adapter *padapter; 640 641 u8 *pallocated_buf; 642 643 u8 *pbuf; 644 645 void *priv_data; 646 647 u16 buf_tag; /* 0: Normal xmitbuf, 1: extension xmitbuf, 2:cmd xmitbuf */ 648 u16 flags; 649 u32 alloc_sz; 650 651 u32 len; 652 653 struct submit_ctx *sctx; 654 655 #ifdef CONFIG_USB_HCI 656 657 /* u32 sz[8]; */ 658 u32 ff_hwaddr; 659 u8 bulkout_id; /* for halmac */ 660 661 PURB pxmit_urb[8]; 662 dma_addr_t dma_transfer_addr; /* (in) dma addr for transfer_buffer */ 663 664 u8 bpending[8]; 665 666 sint last[8]; 667 668 #endif 669 670 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) 671 u8 *phead; 672 u8 *pdata; 673 u8 *ptail; 674 u8 *pend; 675 u32 ff_hwaddr; 676 u8 pg_num; 677 u8 agg_num; 678 #endif 679 680 #ifdef CONFIG_PCI_HCI 681 #ifdef CONFIG_TRX_BD_ARCH 682 /*struct tx_buf_desc *buf_desc;*/ 683 #else 684 struct tx_desc *desc; 685 #endif 686 #endif 687 688 #if defined(DBG_XMIT_BUF) || defined(DBG_XMIT_BUF_EXT) 689 u8 no; 690 #endif 691 692 }; 693 #endif 694 695 #ifdef CONFIG_CORE_TXSC 696 #define MAX_TXSC_SKB_NUM 6 697 #endif 698 699 struct xmit_txreq_buf { 700 _list list; 701 u8 *txreq; 702 u8 *head; 703 u8 *tail; 704 u8 *pkt_list; 705 #ifdef CONFIG_CORE_TXSC 706 u8 *pkt[MAX_TXSC_SKB_NUM]; 707 u8 pkt_cnt; 708 _adapter *adapter; 709 u8 macid; 710 u8 txsc_id; 711 #endif 712 }; 713 714 struct xmit_frame { 715 _list list; 716 717 struct pkt_attrib attrib; 718 719 u16 os_qid; 720 721 struct sk_buff *pkt; 722 723 int frame_tag; 724 725 _adapter *padapter; 726 727 /*Only for MGNT Frame*/ 728 u8 *prealloc_buf_addr; 729 #ifdef CONFIG_USB_HCI 730 dma_addr_t dma_transfer_addr; 731 #endif 732 u8 *buf_addr; 733 #if 0 /*CONFIG_CORE_XMITBUF*/ 734 struct xmit_buf *pxmitbuf; 735 #endif 736 737 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) 738 u8 pg_num; 739 u8 agg_num; 740 #endif 741 742 #ifdef CONFIG_USB_HCI 743 #ifdef CONFIG_USB_TX_AGGREGATION 744 u8 agg_num; 745 #endif 746 s8 pkt_offset; 747 #endif 748 749 #ifdef CONFIG_XMIT_ACK 750 u8 ack_report; 751 #endif 752 753 u8 *alloc_addr; /* the actual address this xmitframe allocated */ 754 u8 ext_tag; /* 0:data, 1:mgmt */ 755 756 #ifdef RTW_PHL_TX 757 u8 xftype; 758 759 //struct sk_buff *skb; 760 //struct sta_info *psta; 761 //struct pkt_attrib tx_attrib; 762 763 u8 alloc_hdr; 764 u8 alloc_tail; 765 u8 *wlhdr[RTW_MAX_FRAG_NUM]; 766 u8 *wltail[RTW_MAX_FRAG_NUM]; 767 768 u32 txring_idx; 769 u32 txreq_cnt; 770 struct rtw_xmit_req *phl_txreq; 771 u32 txfree_cnt; 772 773 struct xmit_txreq_buf *ptxreq_buf;/* TXREQ_QMGT for recycle*/ 774 775 u16 buf_need_free; /* size is realted to RTW_MAX_FRAG_NUM */ 776 #endif 777 778 }; 779 780 struct tx_servq { 781 _list tx_pending; 782 _queue sta_pending; 783 int qcnt; 784 }; 785 786 787 struct sta_xmit_priv { 788 _lock lock; 789 sint option; 790 sint apsd_setting; /* When bit mask is on, the associated edca queue supports APSD. */ 791 792 793 /* struct tx_servq blk_q[MAX_NUMBLKS]; */ 794 struct tx_servq be_q; /* priority == 0,3 */ 795 struct tx_servq bk_q; /* priority == 1,2 */ 796 struct tx_servq vi_q; /* priority == 4,5 */ 797 struct tx_servq vo_q; /* priority == 6,7 */ 798 _list legacy_dz; 799 _list apsd; 800 801 u16 txseq_tid[16]; 802 803 /* uint sta_tx_bytes; */ 804 /* u64 sta_tx_pkts; */ 805 /* uint sta_tx_fail; */ 806 807 808 }; 809 810 811 struct hw_txqueue { 812 volatile sint head; 813 volatile sint tail; 814 volatile sint free_sz; /* in units of 64 bytes */ 815 volatile sint free_cmdsz; 816 volatile sint txsz[8]; 817 uint ff_hwaddr; 818 uint cmd_hwaddr; 819 sint ac_tag; 820 }; 821 822 struct agg_pkt_info { 823 u16 offset; 824 u16 pkt_len; 825 }; 826 #if 0 /*CONFIG_CORE_XMITBUF*/ 827 enum cmdbuf_type { 828 CMDBUF_BEACON = 0x00, 829 CMDBUF_RSVD, 830 CMDBUF_MAX 831 }; 832 #endif 833 struct xmit_priv { 834 835 _lock lock; 836 #if 0 /*def CONFIG_XMIT_THREAD_MODE*/ 837 _sema xmit_sema; 838 #endif 839 840 /* _queue blk_strms[MAX_NUMBLKS]; */ 841 _queue be_pending; 842 _queue bk_pending; 843 _queue vi_pending; 844 _queue vo_pending; 845 _queue bm_pending; 846 847 /* _queue legacy_dz_queue; */ 848 /* _queue apsd_queue; */ 849 850 u8 *pallocated_frame_buf; 851 u8 *pxmit_frame_buf; 852 uint free_xmitframe_cnt; 853 _queue free_xmit_queue; 854 855 /* uint mapping_addr; */ 856 /* uint pkt_sz; */ 857 858 u8 *xframe_ext_alloc_addr; 859 u8 *xframe_ext; 860 uint free_xframe_ext_cnt; 861 _queue free_xframe_ext_queue; 862 863 /* MGT_TXREQ_QMGT */ 864 u8 *xframe_ext_txreq_alloc_addr; 865 u8 *xframe_ext_txreq; 866 867 /* struct hw_txqueue be_txqueue; */ 868 /* struct hw_txqueue bk_txqueue; */ 869 /* struct hw_txqueue vi_txqueue; */ 870 /* struct hw_txqueue vo_txqueue; */ 871 /* struct hw_txqueue bmc_txqueue; */ 872 873 uint frag_len; 874 875 _adapter *adapter; 876 877 u8 vcs_setting; 878 u8 vcs; 879 u8 vcs_type; 880 /* u16 rts_thresh; */ 881 882 u64 tx_bytes; 883 u64 tx_pkts; 884 u64 tx_drop; 885 u64 last_tx_pkts; 886 887 struct hw_xmit *hwxmits; 888 u8 hwxmit_entry; 889 890 u8 wmm_para_seq[4];/* sequence for wmm ac parameter strength from large to small. it's value is 0->vo, 1->vi, 2->be, 3->bk. */ 891 892 #ifdef CONFIG_USB_HCI 893 _sema tx_retevt;/* all tx return event; */ 894 u8 txirp_cnt; 895 896 _tasklet xmit_tasklet; 897 898 /* per AC pending irp */ 899 int beq_cnt; 900 int bkq_cnt; 901 int viq_cnt; 902 int voq_cnt; 903 904 #endif 905 906 #ifdef CONFIG_PCI_HCI 907 /* Tx */ 908 struct rtw_tx_ring tx_ring[PCI_MAX_TX_QUEUE_COUNT]; 909 int txringcount[PCI_MAX_TX_QUEUE_COUNT]; 910 u8 beaconDMAing; /* flag of indicating beacon is transmiting to HW by DMA */ 911 _tasklet xmit_tasklet; 912 #endif 913 914 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) 915 #ifdef CONFIG_TX_AMSDU_SW_MODE 916 _tasklet xmit_tasklet; 917 #endif 918 #ifndef CONFIG_SDIO_TX_TASKLET 919 _thread_hdl_ SdioXmitThread; 920 _sema SdioXmitSema; 921 #endif 922 #endif /* CONFIG_SDIO_HCI */ 923 924 #if 0 /*CONFIG_CORE_XMITBUF*/ 925 _queue free_xmitbuf_queue; 926 _queue pending_xmitbuf_queue; 927 u8 *pallocated_xmitbuf; 928 u8 *pxmitbuf; 929 uint free_xmitbuf_cnt; 930 931 _queue free_xmit_extbuf_queue; 932 u8 *pallocated_xmit_extbuf; 933 u8 *pxmit_extbuf; 934 uint free_xmit_extbuf_cnt; 935 936 struct xmit_buf pcmd_xmitbuf[CMDBUF_MAX]; 937 #endif 938 u8 hw_ssn_seq_no;/* mapping to REG_HW_SEQ 0,1,2,3 */ 939 u16 nqos_ssn; 940 #ifdef CONFIG_TX_EARLY_MODE 941 942 #ifdef CONFIG_SDIO_HCI 943 #define MAX_AGG_PKT_NUM 20 944 #else 945 #define MAX_AGG_PKT_NUM 256 /* Max tx ampdu coounts */ 946 #endif 947 948 struct agg_pkt_info agg_pkt[MAX_AGG_PKT_NUM]; 949 #endif 950 951 #ifdef CONFIG_XMIT_ACK 952 int ack_tx; 953 _mutex ack_tx_mutex; 954 struct submit_ctx ack_tx_ops; 955 u8 seq_no; 956 #endif 957 958 #ifdef CONFIG_TX_AMSDU 959 _timer amsdu_vo_timer; 960 u8 amsdu_vo_timeout; 961 962 _timer amsdu_vi_timer; 963 u8 amsdu_vi_timeout; 964 965 _timer amsdu_be_timer; 966 u8 amsdu_be_timeout; 967 968 _timer amsdu_bk_timer; 969 u8 amsdu_bk_timeout; 970 971 u32 amsdu_debug_set_timer; 972 u32 amsdu_debug_timeout; 973 974 #ifndef AMSDU_DEBUG_MAX_COUNT 975 #define AMSDU_DEBUG_MAX_COUNT 5 976 #endif 977 u32 amsdu_debug_coalesce[AMSDU_DEBUG_MAX_COUNT]; 978 u32 amsdu_debug_tasklet; 979 u32 amsdu_debug_enqueue; 980 u32 amsdu_debug_dequeue; 981 #endif 982 #ifdef DBG_TXBD_DESC_DUMP 983 BOOLEAN dump_txbd_desc; 984 #endif 985 #ifdef CONFIG_PCI_TX_POLLING 986 _timer tx_poll_timer; 987 #endif 988 #ifdef CONFIG_LAYER2_ROAMING 989 _queue rpkt_queue; 990 #endif 991 _lock lock_sctx; 992 #ifdef CONFIG_CORE_TXSC 993 _lock txsc_lock; 994 u8 txsc_enable; 995 u8 txsc_debug_mode; 996 u8 txsc_debug_mask;/* BIT0:core txsc(no use), BIT1: phl txsc enable, BIT2: debug_print */ 997 998 struct sta_info *ptxsc_sta_cached; 999 1000 /* for debug */ 1001 u32 txsc_phl_err_cnt1; 1002 u32 txsc_phl_err_cnt2; 1003 #endif /* CONFIG_CORE_TXSC */ 1004 }; 1005 1006 #if 0 /*CONFIG_CORE_XMITBUF*/ 1007 extern struct xmit_frame *__rtw_alloc_cmdxmitframe(struct xmit_priv *pxmitpriv, 1008 enum cmdbuf_type buf_type); 1009 #define rtw_alloc_cmdxmitframe(p) __rtw_alloc_cmdxmitframe(p, CMDBUF_RSVD) 1010 #define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe(p, CMDBUF_BEACON) 1011 1012 extern struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv); 1013 extern s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); 1014 1015 extern struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv); 1016 extern s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); 1017 #endif 1018 void rtw_count_tx_stats(_adapter *padapter, struct xmit_frame *pxmitframe, int sz); 1019 extern void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len); 1020 1021 extern s32 rtw_make_wlanhdr(_adapter *padapter, u8 *hdr, struct pkt_attrib *pattrib); 1022 extern s32 rtw_put_snap(u8 *data, u16 h_proto); 1023 1024 extern struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv, u16 os_qid); 1025 struct xmit_frame *rtw_alloc_xmitframe_ext(struct xmit_priv *pxmitpriv); 1026 struct xmit_frame *rtw_alloc_xmitframe_once(struct xmit_priv *pxmitpriv); 1027 extern s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe); 1028 extern void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue); 1029 s32 core_tx_free_xmitframe(_adapter *padapter, struct xmit_frame *pxframe); 1030 struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, sint up, u8 *ac); 1031 extern s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); 1032 extern struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry); 1033 1034 extern s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe); 1035 extern u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib); 1036 #define rtw_wlan_pkt_size(f) rtw_calculate_wlan_pkt_size_by_attribue(&f->attrib) 1037 extern s32 rtw_xmitframe_coalesce(_adapter *padapter, struct sk_buff *pkt, 1038 struct xmit_frame *pxmitframe); 1039 #if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) 1040 extern s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, 1041 struct sk_buff *pkt, struct xmit_frame *pxmitframe); 1042 #endif 1043 #ifdef CONFIG_TDLS 1044 extern struct tdls_txmgmt *ptxmgmt; 1045 s32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, struct tdls_txmgmt *ptxmgmt); 1046 s32 update_tdls_attrib(_adapter *padapter, struct pkt_attrib *pattrib); 1047 #endif 1048 s32 _rtw_init_hw_txqueue(struct hw_txqueue *phw_txqueue, u8 ac_tag); 1049 void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv); 1050 1051 1052 s32 rtw_txframes_pending(_adapter *padapter); 1053 s32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib); 1054 void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry); 1055 1056 1057 s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter); 1058 void _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv); 1059 1060 u8 rtw_init_lite_xmit_resource(struct dvobj_priv *dvobj); 1061 void rtw_free_lite_xmit_resource(struct dvobj_priv *dvobj); 1062 1063 void rtw_alloc_hwxmits(_adapter *padapter); 1064 void rtw_free_hwxmits(_adapter *padapter); 1065 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) 1066 s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev); 1067 #endif 1068 void rtw_xmit_dequeue_callback(_workitem *work); 1069 void rtw_xmit_queue_set(struct sta_info *sta); 1070 void rtw_xmit_queue_clear(struct sta_info *sta); 1071 s32 rtw_xmit_posthandle(_adapter *padapter, struct xmit_frame *pxmitframe, struct sk_buff *pkt); 1072 s32 rtw_xmit(_adapter *padapter, struct sk_buff **pkt, u16 os_qid); 1073 bool xmitframe_hiq_filter(struct xmit_frame *xmitframe); 1074 #if defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS) 1075 sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe); 1076 void stop_sta_xmit(_adapter *padapter, struct sta_info *psta); 1077 void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta); 1078 void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta); 1079 #endif 1080 1081 #ifdef RTW_PHL_TX 1082 s32 core_tx_prepare_phl(_adapter *padapter, struct xmit_frame *pxframe); 1083 s32 core_tx_call_phl(_adapter *padapter, struct xmit_frame *pxframe, void *txsc_pkt); 1084 s32 core_tx_per_packet(_adapter *padapter, struct xmit_frame *pxframe, 1085 struct sk_buff **pskb, struct sta_info *psta); 1086 s32 rtw_core_tx(_adapter *padapter, struct sk_buff **ppkt, struct sta_info *psta, u16 os_qid); 1087 enum rtw_phl_status rtw_core_tx_recycle(void *drv_priv, struct rtw_xmit_req *txreq); 1088 s32 core_tx_alloc_xmitframe(_adapter *padapter, struct xmit_frame **pxmitframe, u16 os_qid); 1089 #ifdef CONFIG_CORE_TXSC 1090 void core_recycle_txreq_phyaddr(_adapter *padapter, struct rtw_xmit_req *txreq); 1091 s32 core_tx_free_xmitframe(_adapter *padapter, struct xmit_frame *pxframe); 1092 u8 *get_txreq_buffer(_adapter *padapter, u8 **txreq, u8 **pkt_list, u8 **head, u8 **tail); 1093 u8 tos_to_up(u8 tos); 1094 #endif 1095 #endif 1096 1097 void core_tx_amsdu_tasklet(_adapter *padapter); 1098 1099 u8 rtw_get_tx_bw_mode(_adapter *adapter, struct sta_info *sta); 1100 1101 void rtw_update_tx_rate_bmp(struct dvobj_priv *dvobj); 1102 u8 rtw_get_tx_bw_bmp_of_ht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw); 1103 u8 rtw_get_tx_bw_bmp_of_vht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw); 1104 s16 rtw_rfctl_get_oper_txpwr_max_mbm(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, u8 ifbmp_mod, u8 if_op, bool eirp); 1105 s16 rtw_rfctl_get_reg_max_txpwr_mbm(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, bool eirp); 1106 1107 u8 query_ra_short_GI(struct sta_info *psta, u8 bw); 1108 1109 u8 qos_acm(u8 acm_mask, u8 priority); 1110 1111 #if 0 /*def CONFIG_XMIT_THREAD_MODE*/ 1112 void enqueue_pending_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); 1113 void enqueue_pending_xmitbuf_to_head(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); 1114 struct xmit_buf *dequeue_pending_xmitbuf(struct xmit_priv *pxmitpriv); 1115 struct xmit_buf *select_and_dequeue_pending_xmitbuf(_adapter *padapter); 1116 sint check_pending_xmitbuf(struct xmit_priv *pxmitpriv); 1117 thread_return rtw_xmit_thread(thread_context context); 1118 #endif 1119 1120 #ifdef CONFIG_TX_AMSDU 1121 extern void rtw_amsdu_vo_timeout_handler(void *FunctionContext); 1122 extern void rtw_amsdu_vi_timeout_handler(void *FunctionContext); 1123 extern void rtw_amsdu_be_timeout_handler(void *FunctionContext); 1124 extern void rtw_amsdu_bk_timeout_handler(void *FunctionContext); 1125 1126 extern u8 rtw_amsdu_get_timer_status(_adapter *padapter, u8 priority); 1127 extern void rtw_amsdu_set_timer_status(_adapter *padapter, u8 priority, u8 status); 1128 extern void rtw_amsdu_set_timer(_adapter *padapter, u8 priority); 1129 extern void rtw_amsdu_cancel_timer(_adapter *padapter, u8 priority); 1130 1131 extern s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitframe, struct xmit_frame *pxmitframe_queue); 1132 extern s32 check_amsdu(struct xmit_frame *pxmitframe); 1133 extern s32 check_amsdu_tx_support(_adapter *padapter); 1134 extern struct xmit_frame *rtw_get_xframe(struct xmit_priv *pxmitpriv, int *num_frame); 1135 #endif 1136 1137 #ifdef DBG_TXBD_DESC_DUMP 1138 void rtw_tx_desc_backup(_adapter *padapter, struct xmit_frame *pxmitframe, u8 desc_size, u8 hwq); 1139 void rtw_tx_desc_backup_reset(void); 1140 u8 rtw_get_tx_desc_backup(_adapter *padapter, u8 hwq, struct rtw_tx_desc_backup **pbak); 1141 #endif 1142 1143 #ifdef CONFIG_PCI_TX_POLLING 1144 void rtw_tx_poll_init(_adapter *padapter); 1145 void rtw_tx_poll_timeout_handler(void *FunctionContext); 1146 void rtw_tx_poll_timer_set(_adapter *padapter, u32 delay); 1147 void rtw_tx_poll_timer_cancel(_adapter *padapter); 1148 #endif 1149 1150 #ifdef CONFIG_XMIT_ACK 1151 int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms); 1152 void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status); 1153 #endif /* CONFIG_XMIT_ACK */ 1154 1155 enum XMIT_BLOCK_REASON { 1156 XMIT_BLOCK_NONE = 0, 1157 XMIT_BLOCK_REDLMEM = BIT0, /*LPS-PG*/ 1158 XMIT_BLOCK_SUSPEND = BIT1, /*WOW*/ 1159 XMIT_BLOCK_MAX = 0xFF, 1160 }; 1161 void rtw_init_xmit_block(_adapter *padapter); 1162 void rtw_deinit_xmit_block(_adapter *padapter); 1163 1164 #ifdef DBG_XMIT_BLOCK 1165 void dump_xmit_block(void *sel, _adapter *padapter); 1166 #endif 1167 void rtw_set_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason); 1168 void rtw_clr_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason); 1169 bool rtw_is_xmit_blocked(_adapter *padapter); 1170 #ifdef CONFIG_LAYER2_ROAMING 1171 void dequeuq_roam_pkt(_adapter *padapter); 1172 #endif 1173 /* include after declaring struct xmit_buf, in order to avoid warning */ 1174 #include <xmit_osdep.h> 1175 1176 #endif /* _RTL871X_XMIT_H_ */ 1177