1*4882a593Smuzhiyun /******************************************************************************
2*4882a593Smuzhiyun *
3*4882a593Smuzhiyun * Copyright(c) 2007 - 2019 Realtek Corporation.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it
6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as
7*4882a593Smuzhiyun * published by the Free Software Foundation.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT
10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12*4882a593Smuzhiyun * more details.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun *****************************************************************************/
15*4882a593Smuzhiyun #ifndef __RTW_PWRCTRL_H_
16*4882a593Smuzhiyun #define __RTW_PWRCTRL_H_
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define PS_ACTIVE 0
19*4882a593Smuzhiyun #define PS_LPS 1
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define FW_PWR0 0
22*4882a593Smuzhiyun #define FW_PWR1 1
23*4882a593Smuzhiyun #define FW_PWR2 2
24*4882a593Smuzhiyun #define FW_PWR3 3
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define HW_PWR0 7
28*4882a593Smuzhiyun #define HW_PWR1 6
29*4882a593Smuzhiyun #define HW_PWR2 2
30*4882a593Smuzhiyun #define HW_PWR3 0
31*4882a593Smuzhiyun #define HW_PWR4 8
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define FW_PWRMSK 0x7
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define XMIT_ALIVE BIT(0)
37*4882a593Smuzhiyun #define RECV_ALIVE BIT(1)
38*4882a593Smuzhiyun #define CMD_ALIVE BIT(2)
39*4882a593Smuzhiyun #define EVT_ALIVE BIT(3)
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun enum power_mgnt {
42*4882a593Smuzhiyun PM_PS_MODE_ACTIVE = 0 ,
43*4882a593Smuzhiyun PM_PS_MODE_MIN ,
44*4882a593Smuzhiyun PM_PS_MODE_MAX ,
45*4882a593Smuzhiyun PM_PS_MODE_DTIM , /* PS_MODE_SELF_DEFINED */
46*4882a593Smuzhiyun PM_PS_MODE_VOIP ,
47*4882a593Smuzhiyun PM_PS_MODE_UAPSD_WMM ,
48*4882a593Smuzhiyun PM_PS_MODE_UAPSD ,
49*4882a593Smuzhiyun PM_PS_MODE_IBSS ,
50*4882a593Smuzhiyun PM_PS_MODE_WWLAN ,
51*4882a593Smuzhiyun PM_RADIO_OFF ,
52*4882a593Smuzhiyun PM_CARD_DISABLE ,
53*4882a593Smuzhiyun PM_PS_MODE_NUM,
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun enum lps_level {
57*4882a593Smuzhiyun LPS_NORMAL = 0,
58*4882a593Smuzhiyun LPS_LCLK,
59*4882a593Smuzhiyun LPS_PG,
60*4882a593Smuzhiyun LPS_LEVEL_MAX,
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /*
65*4882a593Smuzhiyun BIT[2:0] = HW state
66*4882a593Smuzhiyun BIT[3] = Protocol PS state, 0: register active state , 1: register sleep state
67*4882a593Smuzhiyun BIT[4] = sub-state
68*4882a593Smuzhiyun */
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun #define PS_DPS BIT(0)
71*4882a593Smuzhiyun #define PS_LCLK (PS_DPS)
72*4882a593Smuzhiyun #define PS_RF_OFF BIT(1)
73*4882a593Smuzhiyun #define PS_ALL_ON BIT(2)
74*4882a593Smuzhiyun #define PS_ST_ACTIVE BIT(3)
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun #define PS_ISR_ENABLE BIT(4)
77*4882a593Smuzhiyun #define PS_IMR_ENABLE BIT(5)
78*4882a593Smuzhiyun #define PS_ACK BIT(6)
79*4882a593Smuzhiyun #define PS_TOGGLE BIT(7)
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun #define PS_STATE_MASK (0x0F)
82*4882a593Smuzhiyun #define PS_STATE_HW_MASK (0x07)
83*4882a593Smuzhiyun #define PS_SEQ_MASK (0xc0)
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun #define PS_STATE(x) (PS_STATE_MASK & (x))
86*4882a593Smuzhiyun #define PS_STATE_HW(x) (PS_STATE_HW_MASK & (x))
87*4882a593Smuzhiyun #define PS_SEQ(x) (PS_SEQ_MASK & (x))
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun #define PS_STATE_S0 (PS_DPS)
90*4882a593Smuzhiyun #define PS_STATE_S1 (PS_LCLK)
91*4882a593Smuzhiyun #define PS_STATE_S2 (PS_RF_OFF)
92*4882a593Smuzhiyun #define PS_STATE_S3 (PS_ALL_ON)
93*4882a593Smuzhiyun #define PS_STATE_S4 ((PS_ST_ACTIVE) | (PS_ALL_ON))
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun #define PS_IS_RF_ON(x) ((x) & (PS_ALL_ON))
97*4882a593Smuzhiyun #define PS_IS_ACTIVE(x) ((x) & (PS_ST_ACTIVE))
98*4882a593Smuzhiyun #define CLR_PS_STATE(x) ((x) = ((x) & (0xF0)))
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun struct reportpwrstate_parm {
102*4882a593Smuzhiyun unsigned char mode;
103*4882a593Smuzhiyun unsigned char state; /* the CPWM value */
104*4882a593Smuzhiyun unsigned short rsvd;
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun typedef _sema _pwrlock;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun
_init_pwrlock(_pwrlock * plock)111*4882a593Smuzhiyun __inline static void _init_pwrlock(_pwrlock *plock)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun _rtw_init_sema(plock, 1);
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun
_free_pwrlock(_pwrlock * plock)116*4882a593Smuzhiyun __inline static void _free_pwrlock(_pwrlock *plock)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun _rtw_free_sema(plock);
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun
_enter_pwrlock(_pwrlock * plock)122*4882a593Smuzhiyun __inline static void _enter_pwrlock(_pwrlock *plock)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun _rtw_down_sema(plock);
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun
_exit_pwrlock(_pwrlock * plock)128*4882a593Smuzhiyun __inline static void _exit_pwrlock(_pwrlock *plock)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun _rtw_up_sema(plock);
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun #define LPS_DELAY_MS 1000 /* 1 sec */
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun #define EXE_PWR_NONE 0x01
136*4882a593Smuzhiyun #define EXE_PWR_IPS 0x02
137*4882a593Smuzhiyun #define EXE_PWR_LPS 0x04
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun /* RF state. */
140*4882a593Smuzhiyun typedef enum _rt_rf_power_state {
141*4882a593Smuzhiyun rf_on, /* RF is on after RFSleep or RFOff */
142*4882a593Smuzhiyun rf_sleep, /* 802.11 Power Save mode */
143*4882a593Smuzhiyun rf_off, /* HW/SW Radio OFF or Inactive Power Save */
144*4882a593Smuzhiyun /* =====Add the new RF state above this line===== */
145*4882a593Smuzhiyun rf_max
146*4882a593Smuzhiyun } rt_rf_power_state;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun /* ASPM OSC Control bit, added by Roger, 2013.03.29. */
149*4882a593Smuzhiyun #define RT_PCI_ASPM_OSC_IGNORE 0 /* PCI ASPM ignore OSC control in default */
150*4882a593Smuzhiyun #define RT_PCI_ASPM_OSC_ENABLE BIT0 /* PCI ASPM controlled by OS according to ACPI Spec 5.0 */
151*4882a593Smuzhiyun #define RT_PCI_ASPM_OSC_DISABLE BIT1 /* PCI ASPM controlled by driver or BIOS, i.e., force enable ASPM */
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun enum _PS_BBRegBackup_ {
155*4882a593Smuzhiyun PSBBREG_RF0 = 0,
156*4882a593Smuzhiyun PSBBREG_RF1,
157*4882a593Smuzhiyun PSBBREG_RF2,
158*4882a593Smuzhiyun PSBBREG_AFE0,
159*4882a593Smuzhiyun PSBBREG_TOTALCNT
160*4882a593Smuzhiyun };
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun enum { /* for ips_mode */
163*4882a593Smuzhiyun IPS_NONE = 0,
164*4882a593Smuzhiyun IPS_NORMAL,
165*4882a593Smuzhiyun IPS_LEVEL_2,
166*4882a593Smuzhiyun IPS_NUM
167*4882a593Smuzhiyun };
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun /* Design for pwrctrl_priv.ips_deny, 32 bits for 32 reasons at most */
170*4882a593Smuzhiyun typedef enum _PS_DENY_REASON {
171*4882a593Smuzhiyun PS_DENY_DRV_INITIAL = 0,
172*4882a593Smuzhiyun PS_DENY_SCAN,
173*4882a593Smuzhiyun PS_DENY_JOIN,
174*4882a593Smuzhiyun PS_DENY_DISCONNECT,
175*4882a593Smuzhiyun PS_DENY_SUSPEND,
176*4882a593Smuzhiyun PS_DENY_IOCTL,
177*4882a593Smuzhiyun PS_DENY_MGNT_TX,
178*4882a593Smuzhiyun PS_DENY_MONITOR_MODE,
179*4882a593Smuzhiyun PS_DENY_BEAMFORMING, /* Beamforming */
180*4882a593Smuzhiyun PS_DENY_DRV_REMOVE = 30,
181*4882a593Smuzhiyun PS_DENY_OTHERS = 31
182*4882a593Smuzhiyun } PS_DENY_REASON;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun struct rsvd_page_cache_t;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun struct pwrctrl_priv {
187*4882a593Smuzhiyun _pwrlock lock;
188*4882a593Smuzhiyun _pwrlock check_32k_lock;
189*4882a593Smuzhiyun volatile u8 rpwm; /* requested power state for fw */
190*4882a593Smuzhiyun volatile u8 cpwm; /* fw current power state. updated when 1. read from HCPWM 2. driver lowers power level */
191*4882a593Smuzhiyun volatile u8 tog; /* toggling */
192*4882a593Smuzhiyun volatile u8 cpwm_tog; /* toggling */
193*4882a593Smuzhiyun u8 rpwm_retry;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun u8 pwr_mode;
196*4882a593Smuzhiyun u8 smart_ps;
197*4882a593Smuzhiyun u8 bcn_ant_mode;
198*4882a593Smuzhiyun u8 dtim;
199*4882a593Smuzhiyun #ifdef CONFIG_LPS_CHK_BY_TP
200*4882a593Smuzhiyun u8 lps_chk_by_tp;
201*4882a593Smuzhiyun u16 lps_tx_tp_th;/*Mbps*/
202*4882a593Smuzhiyun u16 lps_rx_tp_th;/*Mbps*/
203*4882a593Smuzhiyun u16 lps_bi_tp_th;/*Mbps*//*TRX TP*/
204*4882a593Smuzhiyun int lps_chk_cnt_th;
205*4882a593Smuzhiyun int lps_chk_cnt;
206*4882a593Smuzhiyun u32 lps_tx_pkts;
207*4882a593Smuzhiyun u32 lps_rx_pkts;
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun #endif
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun #ifdef CONFIG_WMMPS_STA
212*4882a593Smuzhiyun u8 wmm_smart_ps;
213*4882a593Smuzhiyun #endif /* CONFIG_WMMPS_STA */
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun u32 alives;
216*4882a593Smuzhiyun _workitem cpwm_event;
217*4882a593Smuzhiyun _workitem dma_event; /*for handle un-synchronized tx dma*/
218*4882a593Smuzhiyun #ifdef CONFIG_LPS_RPWM_TIMER
219*4882a593Smuzhiyun u8 brpwmtimeout;
220*4882a593Smuzhiyun _workitem rpwmtimeoutwi;
221*4882a593Smuzhiyun _timer pwr_rpwm_timer;
222*4882a593Smuzhiyun #endif /* CONFIG_LPS_RPWM_TIMER */
223*4882a593Smuzhiyun u8 bpower_saving; /* for LPS/IPS */
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun u8 b_hw_radio_off;
226*4882a593Smuzhiyun u8 reg_rfoff;
227*4882a593Smuzhiyun u8 reg_pdnmode; /* powerdown mode */
228*4882a593Smuzhiyun u32 rfoff_reason;
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun uint ips_enter_cnts;
231*4882a593Smuzhiyun uint ips_leave_cnts;
232*4882a593Smuzhiyun uint lps_enter_cnts;
233*4882a593Smuzhiyun uint lps_leave_cnts;
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun u8 ips_mode;
236*4882a593Smuzhiyun u8 ips_org_mode;
237*4882a593Smuzhiyun u8 ips_mode_req; /* used to accept the mode setting request, will update to ipsmode later */
238*4882a593Smuzhiyun uint bips_processing;
239*4882a593Smuzhiyun systime ips_deny_time; /* will deny IPS when system time is smaller than this */
240*4882a593Smuzhiyun u8 pre_ips_type;/* 0: default flow, 1: carddisbale flow */
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun /* ps_deny: if 0, power save is free to go; otherwise deny all kinds of power save. */
243*4882a593Smuzhiyun /* Use PS_DENY_REASON to decide reason. */
244*4882a593Smuzhiyun /* Don't access this variable directly without control function, */
245*4882a593Smuzhiyun /* and this variable should be protected by lock. */
246*4882a593Smuzhiyun u32 ps_deny;
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun u8 ps_processing; /* temporarily used to mark whether in rtw_ps_processor */
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun u8 fw_psmode_iface_id;
251*4882a593Smuzhiyun u8 bLeisurePs;
252*4882a593Smuzhiyun u8 LpsIdleCount;
253*4882a593Smuzhiyun u8 power_mgnt;
254*4882a593Smuzhiyun u8 org_power_mgnt;
255*4882a593Smuzhiyun u8 bFwCurrentInPSMode;
256*4882a593Smuzhiyun systime lps_deny_time; /* will deny LPS when system time is smaller than this */
257*4882a593Smuzhiyun s32 pnp_current_pwr_state;
258*4882a593Smuzhiyun u8 pnp_bstop_trx;
259*4882a593Smuzhiyun u8 bInSuspend;
260*4882a593Smuzhiyun #ifdef CONFIG_BTC
261*4882a593Smuzhiyun u8 bAutoResume;
262*4882a593Smuzhiyun u8 autopm_cnt;
263*4882a593Smuzhiyun #endif
264*4882a593Smuzhiyun u8 bSupportRemoteWakeup;
265*4882a593Smuzhiyun u8 wowlan_wake_reason;
266*4882a593Smuzhiyun u8 wowlan_last_wake_reason;
267*4882a593Smuzhiyun u8 wowlan_ap_mode;
268*4882a593Smuzhiyun u8 wowlan_mode;
269*4882a593Smuzhiyun u8 wowlan_p2p_mode;
270*4882a593Smuzhiyun u8 wowlan_pno_enable;
271*4882a593Smuzhiyun u8 wowlan_in_resume;
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun #ifdef CONFIG_GPIO_WAKEUP
274*4882a593Smuzhiyun #endif /* CONFIG_GPIO_WAKEUP */
275*4882a593Smuzhiyun u8 hst2dev_high_active;
276*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN
277*4882a593Smuzhiyun #ifdef CONFIG_IPV6
278*4882a593Smuzhiyun u8 wowlan_ns_offload_en;
279*4882a593Smuzhiyun #endif /*CONFIG_IPV6*/
280*4882a593Smuzhiyun u8 wowlan_txpause_status;
281*4882a593Smuzhiyun u8 wowlan_pattern_idx;
282*4882a593Smuzhiyun u64 wowlan_fw_iv;
283*4882a593Smuzhiyun struct rtl_priv_pattern patterns[MAX_WKFM_CAM_NUM];
284*4882a593Smuzhiyun _mutex wowlan_pattern_cam_mutex;
285*4882a593Smuzhiyun u8 wowlan_aoac_rpt_loc;
286*4882a593Smuzhiyun struct aoac_report wowlan_aoac_rpt;
287*4882a593Smuzhiyun u8 wowlan_power_mgmt;
288*4882a593Smuzhiyun u8 wowlan_lps_level;
289*4882a593Smuzhiyun #ifdef CONFIG_LPS_1T1R
290*4882a593Smuzhiyun u8 wowlan_lps_1t1r;
291*4882a593Smuzhiyun #endif
292*4882a593Smuzhiyun #endif /* CONFIG_WOWLAN */
293*4882a593Smuzhiyun _timer pwr_state_check_timer;
294*4882a593Smuzhiyun int pwr_state_check_interval;
295*4882a593Smuzhiyun u8 pwr_state_check_cnts;
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun rt_rf_power_state rf_pwrstate;/* cur power state, only for IPS */
299*4882a593Smuzhiyun /* rt_rf_power_state current_rfpwrstate; */
300*4882a593Smuzhiyun rt_rf_power_state change_rfpwrstate;
301*4882a593Smuzhiyun u8 bkeepfwalive;
302*4882a593Smuzhiyun u8 brfoffbyhw;
303*4882a593Smuzhiyun unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT];
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun #ifdef CONFIG_RESUME_IN_WORKQUEUE
306*4882a593Smuzhiyun struct workqueue_struct *rtw_workqueue;
307*4882a593Smuzhiyun _workitem resume_work;
308*4882a593Smuzhiyun #endif
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun #ifdef CONFIG_HAS_EARLYSUSPEND
311*4882a593Smuzhiyun struct early_suspend early_suspend;
312*4882a593Smuzhiyun u8 do_late_resume;
313*4882a593Smuzhiyun #endif /* CONFIG_HAS_EARLYSUSPEND */
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun #ifdef CONFIG_ANDROID_POWER
316*4882a593Smuzhiyun android_early_suspend_t early_suspend;
317*4882a593Smuzhiyun u8 do_late_resume;
318*4882a593Smuzhiyun #endif
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun u8 lps_level_bk;
321*4882a593Smuzhiyun u8 lps_level; /*LPS_NORMAL,LPA_CG,LPS_PG*/
322*4882a593Smuzhiyun #ifdef CONFIG_LPS_1T1R
323*4882a593Smuzhiyun u8 lps_1t1r_bk;
324*4882a593Smuzhiyun u8 lps_1t1r;
325*4882a593Smuzhiyun #endif
326*4882a593Smuzhiyun #ifdef CONFIG_LPS_PG
327*4882a593Smuzhiyun struct rsvd_page_cache_t lpspg_info;
328*4882a593Smuzhiyun #ifdef CONFIG_RTL8822C
329*4882a593Smuzhiyun struct rsvd_page_cache_t lpspg_dpk_info;
330*4882a593Smuzhiyun struct rsvd_page_cache_t lpspg_iqk_info;
331*4882a593Smuzhiyun #endif
332*4882a593Smuzhiyun #endif
333*4882a593Smuzhiyun u8 current_lps_hw_port_id;
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun #ifdef CONFIG_RTW_CFGVENDOR_LLSTATS
336*4882a593Smuzhiyun systime radio_on_start_time;
337*4882a593Smuzhiyun systime pwr_saving_start_time;
338*4882a593Smuzhiyun u32 pwr_saving_time;
339*4882a593Smuzhiyun u32 on_time;
340*4882a593Smuzhiyun u32 tx_time;
341*4882a593Smuzhiyun u32 rx_time;
342*4882a593Smuzhiyun #endif /* CONFIG_RTW_CFGVENDOR_LLSTATS */
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun #ifdef CONFIG_LPS_ACK
345*4882a593Smuzhiyun struct submit_ctx lps_ack_sctx;
346*4882a593Smuzhiyun s8 lps_ack_status;
347*4882a593Smuzhiyun _mutex lps_ack_mutex;
348*4882a593Smuzhiyun #endif /* CONFIG_LPS_ACK */
349*4882a593Smuzhiyun };
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun #define rtw_get_ips_mode_req(pwrctl) \
352*4882a593Smuzhiyun (pwrctl)->ips_mode_req
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun #define rtw_ips_mode_req(pwrctl, ips_mode) \
355*4882a593Smuzhiyun (pwrctl)->ips_mode_req = (ips_mode)
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun #define RTW_PWR_STATE_CHK_INTERVAL 2000
358*4882a593Smuzhiyun #ifdef CONFIG_RTW_IPS
359*4882a593Smuzhiyun bool rtw_core_set_ips_state(void *drv_priv, enum rtw_rf_state state);
360*4882a593Smuzhiyun #endif
361*4882a593Smuzhiyun #ifdef CONFIG_POWER_SAVING
362*4882a593Smuzhiyun #define _rtw_set_pwr_state_check_timer(pwrctl, ms) \
363*4882a593Smuzhiyun do { \
364*4882a593Smuzhiyun /*RTW_INFO("%s _rtw_set_pwr_state_check_timer(%p, %d)\n", __FUNCTION__, (pwrctl), (ms));*/ \
365*4882a593Smuzhiyun _set_timer(&(pwrctl)->pwr_state_check_timer, (ms)); \
366*4882a593Smuzhiyun } while (0)
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun #define rtw_set_pwr_state_check_timer(pwrctl) \
369*4882a593Smuzhiyun _rtw_set_pwr_state_check_timer((pwrctl), (pwrctl)->pwr_state_check_interval)
370*4882a593Smuzhiyun #endif
371*4882a593Smuzhiyun extern void rtw_init_pwrctrl_priv(_adapter *adapter);
372*4882a593Smuzhiyun extern void rtw_free_pwrctrl_priv(_adapter *adapter);
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun #ifdef CONFIG_LPS_LCLK
375*4882a593Smuzhiyun s32 rtw_register_task_alive(_adapter *, u32 task);
376*4882a593Smuzhiyun void rtw_unregister_task_alive(_adapter *, u32 task);
377*4882a593Smuzhiyun extern s32 rtw_register_tx_alive(_adapter *padapter);
378*4882a593Smuzhiyun extern void rtw_unregister_tx_alive(_adapter *padapter);
379*4882a593Smuzhiyun extern s32 rtw_register_rx_alive(_adapter *padapter);
380*4882a593Smuzhiyun extern void rtw_unregister_rx_alive(_adapter *padapter);
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun #if 0 /*#ifdef CONFIG_CORE_CMD_THREAD*/
383*4882a593Smuzhiyun extern s32 rtw_register_cmd_alive(_adapter *padapter);
384*4882a593Smuzhiyun extern void rtw_unregister_cmd_alive(_adapter *padapter);
385*4882a593Smuzhiyun #endif
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun extern void cpwm_int_hdl(_adapter *padapter, struct reportpwrstate_parm *preportpwrstate);
388*4882a593Smuzhiyun extern void LPS_Leave_check(_adapter *padapter);
389*4882a593Smuzhiyun #endif
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun extern void LeaveAllPowerSaveMode(_adapter *adapter);
392*4882a593Smuzhiyun extern void LeaveAllPowerSaveModeDirect(_adapter *adapter);
393*4882a593Smuzhiyun #ifdef CONFIG_IPS
394*4882a593Smuzhiyun void _ips_enter(_adapter *padapter);
395*4882a593Smuzhiyun void ips_enter(_adapter *padapter);
396*4882a593Smuzhiyun int _ips_leave(_adapter *padapter);
397*4882a593Smuzhiyun int ips_leave(_adapter *padapter);
398*4882a593Smuzhiyun #endif
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun #ifdef CONFIG_POWER_SAVING
401*4882a593Smuzhiyun void rtw_ps_processor(_adapter *padapter);
402*4882a593Smuzhiyun #endif
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun #ifdef DBG_CHECK_FW_PS_STATE
405*4882a593Smuzhiyun int rtw_fw_ps_state(_adapter *padapter);
406*4882a593Smuzhiyun #endif
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun #ifdef CONFIG_LPS
409*4882a593Smuzhiyun extern const char * const LPS_CTRL_PHYDM;
410*4882a593Smuzhiyun void LPS_Enter(_adapter *padapter, const char *msg);
411*4882a593Smuzhiyun void LPS_Leave(_adapter *padapter, const char *msg);
412*4882a593Smuzhiyun void rtw_leave_lps_and_chk(_adapter *padapter, u8 ps_mode);
413*4882a593Smuzhiyun #ifdef CONFIG_CHECK_LEAVE_LPS
414*4882a593Smuzhiyun #ifdef CONFIG_LPS_CHK_BY_TP
415*4882a593Smuzhiyun void traffic_check_for_leave_lps_by_tp(_adapter *padapter, u8 tx, struct sta_info *sta);
416*4882a593Smuzhiyun #endif
417*4882a593Smuzhiyun void traffic_check_for_leave_lps(_adapter *padapter, u8 tx, u32 tx_packets);
418*4882a593Smuzhiyun #endif /*CONFIG_CHECK_LEAVE_LPS*/
419*4882a593Smuzhiyun void rtw_set_ps_mode(_adapter *padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg);
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun u8 rtw_set_rpwm(_adapter *padapter, u8 val8);
422*4882a593Smuzhiyun #endif /* CONFIG_LPS */
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun #ifdef CONFIG_RESUME_IN_WORKQUEUE
425*4882a593Smuzhiyun void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv);
426*4882a593Smuzhiyun #endif /* CONFIG_RESUME_IN_WORKQUEUE */
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun #if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
429*4882a593Smuzhiyun bool rtw_is_earlysuspend_registered(struct pwrctrl_priv *pwrpriv);
430*4882a593Smuzhiyun bool rtw_is_do_late_resume(struct pwrctrl_priv *pwrpriv);
431*4882a593Smuzhiyun void rtw_set_do_late_resume(struct pwrctrl_priv *pwrpriv, bool enable);
432*4882a593Smuzhiyun void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv);
433*4882a593Smuzhiyun void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv);
434*4882a593Smuzhiyun #else
435*4882a593Smuzhiyun #define rtw_is_earlysuspend_registered(pwrpriv) _FALSE
436*4882a593Smuzhiyun #define rtw_is_do_late_resume(pwrpriv) _FALSE
437*4882a593Smuzhiyun #define rtw_set_do_late_resume(pwrpriv, enable) do {} while (0)
438*4882a593Smuzhiyun #define rtw_register_early_suspend(pwrpriv) do {} while (0)
439*4882a593Smuzhiyun #define rtw_unregister_early_suspend(pwrpriv) do {} while (0)
440*4882a593Smuzhiyun #endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun void rtw_set_ips_deny(_adapter *padapter, u32 ms);
443*4882a593Smuzhiyun int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller);
444*4882a593Smuzhiyun #define rtw_pwr_wakeup(adapter) _rtw_pwr_wakeup(adapter, RTW_PWR_STATE_CHK_INTERVAL, __FUNCTION__)
445*4882a593Smuzhiyun #define rtw_pwr_wakeup_ex(adapter, ips_deffer_ms) _rtw_pwr_wakeup(adapter, ips_deffer_ms, __FUNCTION__)
446*4882a593Smuzhiyun int rtw_pm_set_ips(_adapter *padapter, u8 mode);
447*4882a593Smuzhiyun int rtw_pm_set_lps(_adapter *padapter, u8 mode);
448*4882a593Smuzhiyun int rtw_pm_set_lps_level(_adapter *padapter, u8 level);
449*4882a593Smuzhiyun #ifdef CONFIG_LPS_1T1R
450*4882a593Smuzhiyun int rtw_pm_set_lps_1t1r(_adapter *padapter, u8 en);
451*4882a593Smuzhiyun #endif
452*4882a593Smuzhiyun void rtw_set_lps_deny(_adapter *adapter, u32 ms);
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun void rtw_ps_deny(_adapter *padapter, PS_DENY_REASON reason);
455*4882a593Smuzhiyun void rtw_ps_deny_cancel(_adapter *padapter, PS_DENY_REASON reason);
456*4882a593Smuzhiyun u32 rtw_ps_deny_get(_adapter *padapter);
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun void rtw_ssmps_enter(_adapter *adapter, struct sta_info *sta);
459*4882a593Smuzhiyun void rtw_ssmps_leave(_adapter *adapter, struct sta_info *sta);
460*4882a593Smuzhiyun #endif /* __RTL871X_PWRCTRL_H_ */
461