1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2019 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #ifndef __RTW_PWRCTRL_H_
16 #define __RTW_PWRCTRL_H_
17
18 #define PS_ACTIVE 0
19 #define PS_LPS 1
20
21 #define FW_PWR0 0
22 #define FW_PWR1 1
23 #define FW_PWR2 2
24 #define FW_PWR3 3
25
26
27 #define HW_PWR0 7
28 #define HW_PWR1 6
29 #define HW_PWR2 2
30 #define HW_PWR3 0
31 #define HW_PWR4 8
32
33 #define FW_PWRMSK 0x7
34
35
36 #define XMIT_ALIVE BIT(0)
37 #define RECV_ALIVE BIT(1)
38 #define CMD_ALIVE BIT(2)
39 #define EVT_ALIVE BIT(3)
40
41 enum power_mgnt {
42 PM_PS_MODE_ACTIVE = 0 ,
43 PM_PS_MODE_MIN ,
44 PM_PS_MODE_MAX ,
45 PM_PS_MODE_DTIM , /* PS_MODE_SELF_DEFINED */
46 PM_PS_MODE_VOIP ,
47 PM_PS_MODE_UAPSD_WMM ,
48 PM_PS_MODE_UAPSD ,
49 PM_PS_MODE_IBSS ,
50 PM_PS_MODE_WWLAN ,
51 PM_RADIO_OFF ,
52 PM_CARD_DISABLE ,
53 PM_PS_MODE_NUM,
54 };
55
56 enum lps_level {
57 LPS_NORMAL = 0,
58 LPS_LCLK,
59 LPS_PG,
60 LPS_LEVEL_MAX,
61 };
62
63
64 /*
65 BIT[2:0] = HW state
66 BIT[3] = Protocol PS state, 0: register active state , 1: register sleep state
67 BIT[4] = sub-state
68 */
69
70 #define PS_DPS BIT(0)
71 #define PS_LCLK (PS_DPS)
72 #define PS_RF_OFF BIT(1)
73 #define PS_ALL_ON BIT(2)
74 #define PS_ST_ACTIVE BIT(3)
75
76 #define PS_ISR_ENABLE BIT(4)
77 #define PS_IMR_ENABLE BIT(5)
78 #define PS_ACK BIT(6)
79 #define PS_TOGGLE BIT(7)
80
81 #define PS_STATE_MASK (0x0F)
82 #define PS_STATE_HW_MASK (0x07)
83 #define PS_SEQ_MASK (0xc0)
84
85 #define PS_STATE(x) (PS_STATE_MASK & (x))
86 #define PS_STATE_HW(x) (PS_STATE_HW_MASK & (x))
87 #define PS_SEQ(x) (PS_SEQ_MASK & (x))
88
89 #define PS_STATE_S0 (PS_DPS)
90 #define PS_STATE_S1 (PS_LCLK)
91 #define PS_STATE_S2 (PS_RF_OFF)
92 #define PS_STATE_S3 (PS_ALL_ON)
93 #define PS_STATE_S4 ((PS_ST_ACTIVE) | (PS_ALL_ON))
94
95
96 #define PS_IS_RF_ON(x) ((x) & (PS_ALL_ON))
97 #define PS_IS_ACTIVE(x) ((x) & (PS_ST_ACTIVE))
98 #define CLR_PS_STATE(x) ((x) = ((x) & (0xF0)))
99
100
101 struct reportpwrstate_parm {
102 unsigned char mode;
103 unsigned char state; /* the CPWM value */
104 unsigned short rsvd;
105 };
106
107
108 typedef _sema _pwrlock;
109
110
_init_pwrlock(_pwrlock * plock)111 __inline static void _init_pwrlock(_pwrlock *plock)
112 {
113 _rtw_init_sema(plock, 1);
114 }
115
_free_pwrlock(_pwrlock * plock)116 __inline static void _free_pwrlock(_pwrlock *plock)
117 {
118 _rtw_free_sema(plock);
119 }
120
121
_enter_pwrlock(_pwrlock * plock)122 __inline static void _enter_pwrlock(_pwrlock *plock)
123 {
124 _rtw_down_sema(plock);
125 }
126
127
_exit_pwrlock(_pwrlock * plock)128 __inline static void _exit_pwrlock(_pwrlock *plock)
129 {
130 _rtw_up_sema(plock);
131 }
132
133 #define LPS_DELAY_MS 1000 /* 1 sec */
134
135 #define EXE_PWR_NONE 0x01
136 #define EXE_PWR_IPS 0x02
137 #define EXE_PWR_LPS 0x04
138
139 /* RF state. */
140 typedef enum _rt_rf_power_state {
141 rf_on, /* RF is on after RFSleep or RFOff */
142 rf_sleep, /* 802.11 Power Save mode */
143 rf_off, /* HW/SW Radio OFF or Inactive Power Save */
144 /* =====Add the new RF state above this line===== */
145 rf_max
146 } rt_rf_power_state;
147
148 /* ASPM OSC Control bit, added by Roger, 2013.03.29. */
149 #define RT_PCI_ASPM_OSC_IGNORE 0 /* PCI ASPM ignore OSC control in default */
150 #define RT_PCI_ASPM_OSC_ENABLE BIT0 /* PCI ASPM controlled by OS according to ACPI Spec 5.0 */
151 #define RT_PCI_ASPM_OSC_DISABLE BIT1 /* PCI ASPM controlled by driver or BIOS, i.e., force enable ASPM */
152
153
154 enum _PS_BBRegBackup_ {
155 PSBBREG_RF0 = 0,
156 PSBBREG_RF1,
157 PSBBREG_RF2,
158 PSBBREG_AFE0,
159 PSBBREG_TOTALCNT
160 };
161
162 enum { /* for ips_mode */
163 IPS_NONE = 0,
164 IPS_NORMAL,
165 IPS_LEVEL_2,
166 IPS_NUM
167 };
168
169 /* Design for pwrctrl_priv.ips_deny, 32 bits for 32 reasons at most */
170 typedef enum _PS_DENY_REASON {
171 PS_DENY_DRV_INITIAL = 0,
172 PS_DENY_SCAN,
173 PS_DENY_JOIN,
174 PS_DENY_DISCONNECT,
175 PS_DENY_SUSPEND,
176 PS_DENY_IOCTL,
177 PS_DENY_MGNT_TX,
178 PS_DENY_MONITOR_MODE,
179 PS_DENY_BEAMFORMING, /* Beamforming */
180 PS_DENY_DRV_REMOVE = 30,
181 PS_DENY_OTHERS = 31
182 } PS_DENY_REASON;
183
184 struct rsvd_page_cache_t;
185
186 struct pwrctrl_priv {
187 _pwrlock lock;
188 _pwrlock check_32k_lock;
189 volatile u8 rpwm; /* requested power state for fw */
190 volatile u8 cpwm; /* fw current power state. updated when 1. read from HCPWM 2. driver lowers power level */
191 volatile u8 tog; /* toggling */
192 volatile u8 cpwm_tog; /* toggling */
193 u8 rpwm_retry;
194
195 u8 pwr_mode;
196 u8 smart_ps;
197 u8 bcn_ant_mode;
198 u8 dtim;
199 #ifdef CONFIG_LPS_CHK_BY_TP
200 u8 lps_chk_by_tp;
201 u16 lps_tx_tp_th;/*Mbps*/
202 u16 lps_rx_tp_th;/*Mbps*/
203 u16 lps_bi_tp_th;/*Mbps*//*TRX TP*/
204 int lps_chk_cnt_th;
205 int lps_chk_cnt;
206 u32 lps_tx_pkts;
207 u32 lps_rx_pkts;
208
209 #endif
210
211 #ifdef CONFIG_WMMPS_STA
212 u8 wmm_smart_ps;
213 #endif /* CONFIG_WMMPS_STA */
214
215 u32 alives;
216 _workitem cpwm_event;
217 _workitem dma_event; /*for handle un-synchronized tx dma*/
218 #ifdef CONFIG_LPS_RPWM_TIMER
219 u8 brpwmtimeout;
220 _workitem rpwmtimeoutwi;
221 _timer pwr_rpwm_timer;
222 #endif /* CONFIG_LPS_RPWM_TIMER */
223 u8 bpower_saving; /* for LPS/IPS */
224
225 u8 b_hw_radio_off;
226 u8 reg_rfoff;
227 u8 reg_pdnmode; /* powerdown mode */
228 u32 rfoff_reason;
229
230 uint ips_enter_cnts;
231 uint ips_leave_cnts;
232 uint lps_enter_cnts;
233 uint lps_leave_cnts;
234
235 u8 ips_mode;
236 u8 ips_org_mode;
237 u8 ips_mode_req; /* used to accept the mode setting request, will update to ipsmode later */
238 uint bips_processing;
239 systime ips_deny_time; /* will deny IPS when system time is smaller than this */
240 u8 pre_ips_type;/* 0: default flow, 1: carddisbale flow */
241
242 /* ps_deny: if 0, power save is free to go; otherwise deny all kinds of power save. */
243 /* Use PS_DENY_REASON to decide reason. */
244 /* Don't access this variable directly without control function, */
245 /* and this variable should be protected by lock. */
246 u32 ps_deny;
247
248 u8 ps_processing; /* temporarily used to mark whether in rtw_ps_processor */
249
250 u8 fw_psmode_iface_id;
251 u8 bLeisurePs;
252 u8 LpsIdleCount;
253 u8 power_mgnt;
254 u8 org_power_mgnt;
255 u8 bFwCurrentInPSMode;
256 systime lps_deny_time; /* will deny LPS when system time is smaller than this */
257 s32 pnp_current_pwr_state;
258 u8 pnp_bstop_trx;
259 u8 bInSuspend;
260 #ifdef CONFIG_BTC
261 u8 bAutoResume;
262 u8 autopm_cnt;
263 #endif
264 u8 bSupportRemoteWakeup;
265 u8 wowlan_wake_reason;
266 u8 wowlan_last_wake_reason;
267 u8 wowlan_ap_mode;
268 u8 wowlan_mode;
269 u8 wowlan_p2p_mode;
270 u8 wowlan_pno_enable;
271 u8 wowlan_in_resume;
272
273 #ifdef CONFIG_GPIO_WAKEUP
274 #endif /* CONFIG_GPIO_WAKEUP */
275 u8 hst2dev_high_active;
276 #ifdef CONFIG_WOWLAN
277 #ifdef CONFIG_IPV6
278 u8 wowlan_ns_offload_en;
279 #endif /*CONFIG_IPV6*/
280 u8 wowlan_txpause_status;
281 u8 wowlan_pattern_idx;
282 u64 wowlan_fw_iv;
283 struct rtl_priv_pattern patterns[MAX_WKFM_CAM_NUM];
284 _mutex wowlan_pattern_cam_mutex;
285 u8 wowlan_aoac_rpt_loc;
286 struct aoac_report wowlan_aoac_rpt;
287 u8 wowlan_power_mgmt;
288 u8 wowlan_lps_level;
289 #ifdef CONFIG_LPS_1T1R
290 u8 wowlan_lps_1t1r;
291 #endif
292 #endif /* CONFIG_WOWLAN */
293 _timer pwr_state_check_timer;
294 int pwr_state_check_interval;
295 u8 pwr_state_check_cnts;
296
297
298 rt_rf_power_state rf_pwrstate;/* cur power state, only for IPS */
299 /* rt_rf_power_state current_rfpwrstate; */
300 rt_rf_power_state change_rfpwrstate;
301 u8 bkeepfwalive;
302 u8 brfoffbyhw;
303 unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT];
304
305 #ifdef CONFIG_RESUME_IN_WORKQUEUE
306 struct workqueue_struct *rtw_workqueue;
307 _workitem resume_work;
308 #endif
309
310 #ifdef CONFIG_HAS_EARLYSUSPEND
311 struct early_suspend early_suspend;
312 u8 do_late_resume;
313 #endif /* CONFIG_HAS_EARLYSUSPEND */
314
315 #ifdef CONFIG_ANDROID_POWER
316 android_early_suspend_t early_suspend;
317 u8 do_late_resume;
318 #endif
319
320 u8 lps_level_bk;
321 u8 lps_level; /*LPS_NORMAL,LPA_CG,LPS_PG*/
322 #ifdef CONFIG_LPS_1T1R
323 u8 lps_1t1r_bk;
324 u8 lps_1t1r;
325 #endif
326 #ifdef CONFIG_LPS_PG
327 struct rsvd_page_cache_t lpspg_info;
328 #ifdef CONFIG_RTL8822C
329 struct rsvd_page_cache_t lpspg_dpk_info;
330 struct rsvd_page_cache_t lpspg_iqk_info;
331 #endif
332 #endif
333 u8 current_lps_hw_port_id;
334
335 #ifdef CONFIG_RTW_CFGVENDOR_LLSTATS
336 systime radio_on_start_time;
337 systime pwr_saving_start_time;
338 u32 pwr_saving_time;
339 u32 on_time;
340 u32 tx_time;
341 u32 rx_time;
342 #endif /* CONFIG_RTW_CFGVENDOR_LLSTATS */
343
344 #ifdef CONFIG_LPS_ACK
345 struct submit_ctx lps_ack_sctx;
346 s8 lps_ack_status;
347 _mutex lps_ack_mutex;
348 #endif /* CONFIG_LPS_ACK */
349 };
350
351 #define rtw_get_ips_mode_req(pwrctl) \
352 (pwrctl)->ips_mode_req
353
354 #define rtw_ips_mode_req(pwrctl, ips_mode) \
355 (pwrctl)->ips_mode_req = (ips_mode)
356
357 #define RTW_PWR_STATE_CHK_INTERVAL 2000
358 #ifdef CONFIG_RTW_IPS
359 bool rtw_core_set_ips_state(void *drv_priv, enum rtw_rf_state state);
360 #endif
361 #ifdef CONFIG_POWER_SAVING
362 #define _rtw_set_pwr_state_check_timer(pwrctl, ms) \
363 do { \
364 /*RTW_INFO("%s _rtw_set_pwr_state_check_timer(%p, %d)\n", __FUNCTION__, (pwrctl), (ms));*/ \
365 _set_timer(&(pwrctl)->pwr_state_check_timer, (ms)); \
366 } while (0)
367
368 #define rtw_set_pwr_state_check_timer(pwrctl) \
369 _rtw_set_pwr_state_check_timer((pwrctl), (pwrctl)->pwr_state_check_interval)
370 #endif
371 extern void rtw_init_pwrctrl_priv(_adapter *adapter);
372 extern void rtw_free_pwrctrl_priv(_adapter *adapter);
373
374 #ifdef CONFIG_LPS_LCLK
375 s32 rtw_register_task_alive(_adapter *, u32 task);
376 void rtw_unregister_task_alive(_adapter *, u32 task);
377 extern s32 rtw_register_tx_alive(_adapter *padapter);
378 extern void rtw_unregister_tx_alive(_adapter *padapter);
379 extern s32 rtw_register_rx_alive(_adapter *padapter);
380 extern void rtw_unregister_rx_alive(_adapter *padapter);
381
382 #if 0 /*#ifdef CONFIG_CORE_CMD_THREAD*/
383 extern s32 rtw_register_cmd_alive(_adapter *padapter);
384 extern void rtw_unregister_cmd_alive(_adapter *padapter);
385 #endif
386
387 extern void cpwm_int_hdl(_adapter *padapter, struct reportpwrstate_parm *preportpwrstate);
388 extern void LPS_Leave_check(_adapter *padapter);
389 #endif
390
391 extern void LeaveAllPowerSaveMode(_adapter *adapter);
392 extern void LeaveAllPowerSaveModeDirect(_adapter *adapter);
393 #ifdef CONFIG_IPS
394 void _ips_enter(_adapter *padapter);
395 void ips_enter(_adapter *padapter);
396 int _ips_leave(_adapter *padapter);
397 int ips_leave(_adapter *padapter);
398 #endif
399
400 #ifdef CONFIG_POWER_SAVING
401 void rtw_ps_processor(_adapter *padapter);
402 #endif
403
404 #ifdef DBG_CHECK_FW_PS_STATE
405 int rtw_fw_ps_state(_adapter *padapter);
406 #endif
407
408 #ifdef CONFIG_LPS
409 extern const char * const LPS_CTRL_PHYDM;
410 void LPS_Enter(_adapter *padapter, const char *msg);
411 void LPS_Leave(_adapter *padapter, const char *msg);
412 void rtw_leave_lps_and_chk(_adapter *padapter, u8 ps_mode);
413 #ifdef CONFIG_CHECK_LEAVE_LPS
414 #ifdef CONFIG_LPS_CHK_BY_TP
415 void traffic_check_for_leave_lps_by_tp(_adapter *padapter, u8 tx, struct sta_info *sta);
416 #endif
417 void traffic_check_for_leave_lps(_adapter *padapter, u8 tx, u32 tx_packets);
418 #endif /*CONFIG_CHECK_LEAVE_LPS*/
419 void rtw_set_ps_mode(_adapter *padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg);
420
421 u8 rtw_set_rpwm(_adapter *padapter, u8 val8);
422 #endif /* CONFIG_LPS */
423
424 #ifdef CONFIG_RESUME_IN_WORKQUEUE
425 void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv);
426 #endif /* CONFIG_RESUME_IN_WORKQUEUE */
427
428 #if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
429 bool rtw_is_earlysuspend_registered(struct pwrctrl_priv *pwrpriv);
430 bool rtw_is_do_late_resume(struct pwrctrl_priv *pwrpriv);
431 void rtw_set_do_late_resume(struct pwrctrl_priv *pwrpriv, bool enable);
432 void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv);
433 void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv);
434 #else
435 #define rtw_is_earlysuspend_registered(pwrpriv) _FALSE
436 #define rtw_is_do_late_resume(pwrpriv) _FALSE
437 #define rtw_set_do_late_resume(pwrpriv, enable) do {} while (0)
438 #define rtw_register_early_suspend(pwrpriv) do {} while (0)
439 #define rtw_unregister_early_suspend(pwrpriv) do {} while (0)
440 #endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */
441
442 void rtw_set_ips_deny(_adapter *padapter, u32 ms);
443 int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller);
444 #define rtw_pwr_wakeup(adapter) _rtw_pwr_wakeup(adapter, RTW_PWR_STATE_CHK_INTERVAL, __FUNCTION__)
445 #define rtw_pwr_wakeup_ex(adapter, ips_deffer_ms) _rtw_pwr_wakeup(adapter, ips_deffer_ms, __FUNCTION__)
446 int rtw_pm_set_ips(_adapter *padapter, u8 mode);
447 int rtw_pm_set_lps(_adapter *padapter, u8 mode);
448 int rtw_pm_set_lps_level(_adapter *padapter, u8 level);
449 #ifdef CONFIG_LPS_1T1R
450 int rtw_pm_set_lps_1t1r(_adapter *padapter, u8 en);
451 #endif
452 void rtw_set_lps_deny(_adapter *adapter, u32 ms);
453
454 void rtw_ps_deny(_adapter *padapter, PS_DENY_REASON reason);
455 void rtw_ps_deny_cancel(_adapter *padapter, PS_DENY_REASON reason);
456 u32 rtw_ps_deny_get(_adapter *padapter);
457
458 void rtw_ssmps_enter(_adapter *adapter, struct sta_info *sta);
459 void rtw_ssmps_leave(_adapter *adapter, struct sta_info *sta);
460 #endif /* __RTL871X_PWRCTRL_H_ */
461