1 /****************************************************************************** 2 * 3 * Copyright(c) 2019 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef _TRX_TEST_H_ 16 #define _TRX_TEST_H_ 17 18 #ifdef CONFIG_PHL_TEST_SUITE 19 20 #define MAX_TEST_TXREQ_NUM 256 21 #define MAX_TEST_PAYLOAD_NUM MAX_TEST_TXREQ_NUM 22 #define MAX_TEST_RXREQ_NUM 256 23 #define MAX_TEST_PAYLOAD_SIZE 2308 24 25 26 enum test_mode { 27 TEST_MODE_PHL_TX_RING_TEST = 1, 28 TEST_MODE_PHL_RX_RING_TEST = 2, 29 TEST_MODE_PHL_RING_LOOPBACK = 3, 30 TEST_MODE_PHL_PCIE_LOOPBACK = 4, 31 TEST_MODE_HAL_TX_TEST = 5, 32 TEST_MODE_HAL_RX_TEST = 6, 33 TEST_MODE_HAL_WP_REPORT_PARSE = 7, 34 TEST_MODE_HAL_RXDESC_PARSE = 8, 35 TEST_MODE_HAL_RXBD_PARSE = 9 36 }; 37 38 enum pkt_type { 39 TEST_PKT_TYPE_UNI = 1, 40 TEST_PKT_TYPE_MC = 2, 41 TEST_PKT_TYPE_BC = 3, 42 TEST_PKT_TYPE_MAX = 0xFF, 43 }; 44 45 struct rtw_tx_cap { 46 u16 macid; 47 u8 tid; 48 u8 wmm; /* for halmac add role */ 49 u8 dma_ch; 50 u8 band; 51 u8 force_txcap; 52 u16 rate; 53 u8 bw; 54 u8 gi_ltf; 55 u8 stbc; 56 u8 ldpc; 57 u8 bk; 58 u8 type; 59 }; 60 61 struct rtw_pool { 62 u8 *buf; 63 u32 buf_len; 64 _os_list idle_list; 65 _os_list busy_list; 66 _os_lock idle_lock; 67 _os_lock busy_lock; 68 u32 total_cnt; 69 u32 idle_cnt; 70 u32 busy_cnt; 71 }; 72 73 struct rtw_test_rx { 74 _os_list list; 75 u32 test_id; 76 struct rtw_recv_pkt rx; 77 u8 *tpkt; /* for loopback mode */ 78 }; 79 80 struct rtw_payload { 81 _os_list list; 82 u32 test_id; 83 struct rtw_pkt_buf_list pkt; 84 void *os_rsvd[1]; 85 }; 86 87 struct rtw_trx_test_param { 88 u8 is_trx_test_end; 89 u8 mode; 90 /* parameter for trx resource*/ 91 u32 tx_req_num; 92 u32 rx_req_num; 93 u32 tx_payload_num; 94 u32 tx_payload_size; 95 enum pkt_type pkt_type; 96 u8 ap_mode; 97 u8 trx_mode; 98 u8 qta_mode; 99 u8 qos; 100 u8 cur_addr[6]; /* mac address of this device */ 101 u8 sta_addr[6]; /* mac address of associating device */ 102 u8 bssid[6]; 103 /* parameter for tx capability */ 104 struct rtw_t_meta_data tx_cap; 105 /* parameter for hw configure */ 106 /* misc */ 107 108 }; 109 110 struct phl_trx_test { 111 _os_list rx_q; 112 _os_lock rx_q_lock; 113 struct rtw_pool tx_req_pool; 114 struct rtw_pool rx_req_pool; 115 struct rtw_pool tx_pkt_pool; 116 struct test_obj_ctrl_interface trx_test_obj; 117 struct rtw_trx_test_param test_param; 118 struct rtw_phl_handler test_rxq_handler; 119 }; 120 121 #define WHDR_OFST_FRAME_CONTROL 0 122 #define WHDR_OFST_DURATION 2 123 #define WHDR_OFST_ADDRESS1 4 124 #define WHDR_OFST_ADDRESS2 10 125 #define WHDR_OFST_ADDRESS3 16 126 #define WHDR_OFST_SEQUENCE 22 127 #define WHDR_OFST_ADDRESS4 24 128 #define WHDR_QOS_LENGTH 2 129 130 #define SET_WHDR_PROTOCOL_VERSION(_hdr, _val) \ 131 SET_BITS_TO_LE_2BYTE(_hdr, 0, 2, _val) 132 #define SET_WHDR_TYPE(_hdr, _val) \ 133 SET_BITS_TO_LE_2BYTE(_hdr, 2, 2, _val) 134 #define SET_WHDR_SUBTYPE(_hdr, _val) \ 135 SET_BITS_TO_LE_2BYTE(_hdr, 4, 4, _val) 136 #define SET_WHDR_TO_DS(_hdr, _val) \ 137 SET_BITS_TO_LE_2BYTE(_hdr, 8, 1, _val) 138 #define SET_WHDR_FROM_DS(_hdr, _val) \ 139 SET_BITS_TO_LE_2BYTE(_hdr, 9, 1, _val) 140 #define SET_WHDR_MORE_FRAG(_hdr, _val) \ 141 SET_BITS_TO_LE_2BYTE(_hdr, 10, 1, _val) 142 #define SET_WHDR_RETRY(_hdr, _val) \ 143 SET_BITS_TO_LE_2BYTE(_hdr, 11, 1, _val) 144 #define SET_WHDR_PWR_MGNT(_hdr, _val) \ 145 SET_BITS_TO_LE_2BYTE(_hdr, 12, 1, _val) 146 #define SET_WHDR_MORE_DATA(_hdr, _val) \ 147 SET_BITS_TO_LE_2BYTE(_hdr, 13, 1, _val) 148 #define SET_WHDR_WEP(_hdr, _val) \ 149 SET_BITS_TO_LE_2BYTE(_hdr, 14, 1, _val) 150 #define SET_WHDR_ORDER(_hdr, _val) \ 151 SET_BITS_TO_LE_2BYTE(_hdr, 15, 1, _val) 152 #define SET_WHDR_QOS_EN(_hdr, _val) \ 153 SET_BITS_TO_LE_2BYTE(_hdr, 7, 1, _val) 154 #define SET_WHDR_DURATION(_hdr, _val) \ 155 WriteLE2Byte(_hdr + WHDR_OFST_DURATION, _val) 156 #define SET_WHDR_ADDRESS1(_drv, _hdr, _val) \ 157 _os_mem_cpy(_drv, _hdr + WHDR_OFST_ADDRESS1, _val, 6) 158 #define SET_WHDR_ADDRESS2(_drv, _hdr, _val) \ 159 _os_mem_cpy(_drv, _hdr + WHDR_OFST_ADDRESS2, _val, 6) 160 #define SET_WHDR_ADDRESS3(_drv, _hdr, _val) \ 161 _os_mem_cpy(_drv, _hdr + WHDR_OFST_ADDRESS3, _val, 6) 162 #define SET_WHDR_FRAGMENT_SEQUENCE(_hdr, _val) \ 163 WriteLE2Byte(_hdr + WHDR_OFST_SEQUENCE, _val) 164 #define SET_WHDR_ADDRESS4(_drv, _hdr, _val) \ 165 _os_mem_cpy(_drv, _hdr + WHDR_OFST_ADDRESS4, _val, 6) 166 167 168 #define SET_WHDR_QOS_CTRL_STA_DATA_TID(_qos, _value) \ 169 SET_BITS_TO_LE_2BYTE((u8 *)_qos, 0, 4, (u8)(_value)) 170 171 #define SET_WHDR_QOS_CTRL_STA_DATA_EOSP(_qos, _value) \ 172 SET_BITS_TO_LE_2BYTE((u8 *)_qos, 4, 1, (u8)(_value)) 173 174 #define SET_WHDR_QOS_CTRL_STA_DATA_ACK_POLICY(_qos, _value) \ 175 SET_BITS_TO_LE_2BYTE((u8 *)_qos, 5, 2, (u8)(_value)) 176 177 #define SET_WHDR_QOS_CTRL_STA_DATA_AMSDU(_qos, _value) \ 178 SET_BITS_TO_LE_2BYTE((u8 *)_qos, 7, 1, (u8)(_value)) 179 180 #define SET_WHDR_QOS_CTRL_STA_DATA_TXOP(_qos, _value) \ 181 SET_BITS_TO_LE_1BYTE((u8 *)_qos + 1, 0, 8, (u8)(_value)) 182 183 184 enum rtw_phl_status phl_trx_test_init(void *phl); 185 void phl_trx_test_deinit(void *phl); 186 void rtw_phl_trx_default_param(void *phl, 187 struct rtw_trx_test_param *test_param); 188 enum rtw_phl_status rtw_phl_trx_testsuite(void *phl, 189 struct rtw_trx_test_param *test_param); 190 191 #else /*!CONFIG_PHL_TEST_SUITE*/ 192 #define phl_trx_test_init(phl) 193 #define phl_trx_test_deinit(phl) 194 #define rtw_phl_trx_default_param(phl, test_param) 195 #define rtw_phl_trx_testsuite(phl, test_param) RTW_PHL_STATUS_SUCCESS 196 #endif 197 198 #endif /*_TRX_TEST_H_*/ 199