1 /****************************************************************************** 2 * 3 * Copyright(c) 2019 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef __PHL_TRX_DEF_H_ 16 #define __PHL_TRX_DEF_H_ 17 18 /* core / phl common structrue */ 19 20 #ifdef CONFIG_PHL_REDUCE_MEM 21 #define MAX_PHL_RING_ENTRY_NUM 512 22 #else 23 #define MAX_PHL_RING_ENTRY_NUM 4096 24 #endif 25 #define MAX_PHL_RING_CAT_NUM 10 /* 8 tid + 1 mgnt + 1 hiq*/ 26 #ifdef CONFIG_PHL_REDUCE_MEM 27 #define MAX_PHL_RING_RX_PKT_NUM 1024 28 #else 29 #define MAX_PHL_RING_RX_PKT_NUM 8192 30 #endif 31 #define MAX_RX_BUF_SEG_NUM 4 32 33 #define _H2CB_CMD_QLEN 32 34 #define _H2CB_DATA_QLEN 32 35 #define _H2CB_LONG_DATA_QLEN 200 /* should be refined */ 36 #define MAX_H2C_PKT_NUM (_H2CB_CMD_QLEN + _H2CB_DATA_QLEN + _H2CB_LONG_DATA_QLEN) 37 38 #define FWCMD_HDR_LEN 8 39 #define _WD_BODY_LEN 24 40 #define H2C_CMD_LEN 64 41 #define H2C_DATA_LEN 256 42 #define H2C_LONG_DATA_LEN 2048 43 44 #define get_h2c_size_by_range(i) \ 45 ((i < _H2CB_CMD_QLEN) ? \ 46 (FWCMD_HDR_LEN + _WD_BODY_LEN + H2C_CMD_LEN) : \ 47 ((i < (_H2CB_CMD_QLEN + _H2CB_DATA_QLEN)) ? \ 48 (FWCMD_HDR_LEN + _WD_BODY_LEN + H2C_DATA_LEN) : \ 49 (FWCMD_HDR_LEN + _WD_BODY_LEN + H2C_LONG_DATA_LEN))) 50 51 struct rtw_h2c_pkt { 52 _os_list list; 53 u8 *vir_head; /* should not reset */ 54 u8 *vir_data; 55 u8 *vir_end; 56 u8 *vir_tail; 57 void *os_rsvd[1]; 58 u8 type; 59 u32 id; /* h2c id */ 60 u32 buf_len; 61 u32 data_len; 62 63 u32 phy_addr_l; 64 u32 phy_addr_h; 65 u8 cache; 66 u16 host_idx; 67 u8 h2c_seq; /* h2c seq */ 68 }; 69 70 /** 71 * the category of phl ring 72 */ 73 enum rtw_phl_ring_cat { 74 RTW_PHL_RING_CAT_TID0 = 0, 75 RTW_PHL_RING_CAT_TID1 = 1, 76 RTW_PHL_RING_CAT_TID2 = 2, 77 RTW_PHL_RING_CAT_TID3 = 3, 78 RTW_PHL_RING_CAT_TID4 = 4, 79 RTW_PHL_RING_CAT_TID5 = 5, 80 RTW_PHL_RING_CAT_TID6 = 6, 81 RTW_PHL_RING_CAT_TID7 = 7, 82 RTW_PHL_RING_CAT_MGNT = 8, 83 RTW_PHL_RING_CAT_HIQ = 9, 84 RTW_PHL_RING_CAT_MAX = 0xff 85 }; 86 87 88 /** 89 * @RTW_PHL_TREQ_TYPE_PHL_UPDATE_TXSC: 90 * this is for phl tx shortcut entry to update 91 * @RTW_PHL_TREQ_TYPE_CORE_TXSC: 92 * it means this txreq is a shortcut pkt, so it need a txsc recycle 93 * @RTW_PHL_TREQ_TYPE_PHL_ADD_TXSC: 94 * it means this txreq is a new cache in core layer and also need cache 95 * in phl layer 96 */ 97 98 enum rtw_treq_type { 99 #if defined(CONFIG_CORE_TXSC) || defined(CONFIG_PHL_TXSC) 100 RTW_PHL_TREQ_TYPE_PHL_UPDATE_TXSC = 0x80, 101 #endif 102 RTW_PHL_TREQ_TYPE_NORMAL = 0, 103 RTW_PHL_TREQ_TYPE_TEST_PATTERN = 1, 104 #if defined(CONFIG_CORE_TXSC) || defined(CONFIG_PHL_TXSC) 105 RTW_PHL_TREQ_TYPE_CORE_TXSC = 2, 106 RTW_PHL_TREQ_TYPE_PHL_ADD_TXSC = 3, 107 #endif 108 RTW_PHL_TREQ_TYPE_MAX = 0xFF 109 }; 110 111 112 enum rtw_packet_type { 113 RTW_PHL_PKT_TYPE_DATA = 0, 114 RTW_PHL_PKT_TYPE_MGNT = 1, 115 RTW_PHL_PKT_TYPE_H2C = 2, 116 RTW_PHL_PKT_TYPE_CTRL = 3, 117 RTW_PHL_PKT_TYPE_FWDL = 4, 118 RTW_PHL_PKT_TYPE_MAX = 0xFF 119 }; 120 121 122 /** 123 * struct rtw_t_mdata_non_dcpu: 124 * this settings are only used in non-dcpu mode. 125 */ 126 struct rtw_t_mdata_non_dcpu { 127 u8 tbd; 128 }; 129 130 /** 131 * struct rtw_t_mdata_dcpu: 132 * this settings are only used in dcpu mode. 133 */ 134 struct rtw_t_mdata_dcpu { 135 u8 tbd; 136 }; 137 138 /** 139 * tx packet descrption 140 * 141 * @u: the union separates dpcu mode and non-dpcu mode unique settings 142 * @mac_priv: the mac private struture only used by HV tool. 143 * normal driver won't allocate memory for this pointer. 144 */ 145 struct rtw_t_meta_data { 146 /* basic */ 147 u8 *ta; 148 u8 *ra; 149 u8 da[6]; 150 u8 sa[6]; 151 u8 to_ds; 152 u8 from_ds; 153 u8 band; /*0 or 1*/ 154 u8 wmm; /*0 or 1*/ 155 enum rtw_packet_type type; 156 u8 tid; 157 u8 bc; 158 u8 mc; 159 u16 pktlen; /* MAC header length + frame body length */ 160 161 u16 macid; 162 u8 hal_port; 163 164 /* sequence */ 165 u8 hw_seq_mode; 166 u8 hw_ssn_sel; 167 u16 sw_seq; 168 169 /* hdr conversion & hw amsdu */ 170 u8 smh_en; 171 u8 hw_amsdu; 172 u8 hdr_len; 173 u8 wp_offset; 174 u8 shcut_camid; 175 u8 upd_wlan_hdr; 176 u8 reuse_start_num; 177 u8 reuse_size; 178 179 /* sec */ 180 u8 hw_sec_iv; 181 u8 sw_sec_iv; 182 u8 sec_keyid; 183 u8 sec_cam_idx; 184 u8 sec_hw_enc; 185 u8 sec_type; 186 u8 force_key_en; 187 u8 iv[6]; 188 189 /* dma */ 190 u8 dma_ch; 191 u8 wd_page_size; 192 u8 wdinfo_en; 193 u8 addr_info_num; 194 u8 usb_pkt_ofst; 195 u8 usb_txagg_num; 196 197 /* ampdu */ 198 u8 ampdu_en; 199 u8 max_agg_num; 200 u8 bk; 201 u8 ampdu_density; 202 203 /* rate */ 204 u8 data_bw_er; 205 u8 f_ldpc; 206 u8 f_stbc; 207 u8 f_dcm; 208 u8 f_er; 209 u16 f_rate; 210 u8 f_gi_ltf; 211 u8 f_bw; 212 u8 userate_sel; 213 214 /* a ctrl */ 215 u8 a_ctrl_bqr; 216 u8 a_ctrl_uph; 217 u8 a_ctrl_bsr; 218 u8 a_ctrl_cas; 219 220 /* tx cnt & rty rate */ 221 u8 dis_rts_rate_fb; 222 u8 dis_data_rate_fb; 223 u16 data_rty_lowest_rate; 224 u8 data_tx_cnt_lmt; 225 u8 data_tx_cnt_lmt_en; 226 227 /* protection */ 228 u8 rts_en; 229 u8 cts2self; 230 u8 rts_cca_mode; 231 u8 hw_rts_en; 232 233 /* misc */ 234 u8 mbssid; 235 u8 nav_use_hdr; 236 u8 ack_ch_info; 237 u8 life_time_sel; 238 u8 no_ack; 239 u8 ndpa; 240 u8 snd_pkt_sel; 241 u8 sifs_tx; 242 u8 rtt_en; 243 u8 spe_rpt; 244 u8 raw; 245 u8 sw_define; 246 247 union { 248 struct rtw_t_mdata_non_dcpu non_dcpu; 249 struct rtw_t_mdata_dcpu dcpu; 250 } u; 251 252 void *mac_priv; 253 }; 254 255 256 /** 257 * packet recv information 258 */ 259 struct rtw_r_meta_data { 260 u8 dma_ch; 261 u8 hal_port; 262 u8 ta[6]; /* Transmitter Address */ 263 u8 ppdu_cnt_chg; 264 #ifdef CONFIG_PHL_CSUM_OFFLOAD_RX 265 u8 chksum_status; /*return mac_chk_rx_tcpip_chksum_ofd,0 is ok ,1 is fail*/ 266 #endif 267 268 u16 pktlen; /* DW0 [0:13] */ 269 u8 shift; /* DW0 [14:15] */ 270 u8 wl_hd_iv_len; /* DW0 [16:21] */ 271 u8 bb_sel; /* DW0 [22:22] */ 272 u8 mac_info_vld; /* DW0 [23:23] */ 273 u8 rpkt_type; /* DW0 [24:27] */ 274 u8 drv_info_size; /* DW0 [28:30] */ 275 u8 long_rxd; /* DW0 [31:31] */ 276 277 u8 ppdu_type; /* DW1 [0:3] */ 278 u8 ppdu_cnt; /* DW1 [4:6] */ 279 u8 sr_en; /* DW1 [7:7] */ 280 u8 user_id; /* DW1 [8:15] */ 281 u16 rx_rate; /* DW1 [16:24] */ 282 u8 rx_gi_ltf; /* DW1 [25:27] */ 283 u8 non_srg_ppdu; /* DW1 [28:28] */ 284 u8 inter_ppdu; /* DW1 [29:29] */ 285 u8 bw; /* DW1 [30:31] */ 286 287 u32 freerun_cnt; /* DW2 [0:31] */ 288 289 u8 a1_match; /* DW3 [0:0] */ 290 u8 sw_dec; /* DW3 [1:1] */ 291 u8 hw_dec; /* DW3 [2:2] */ 292 u8 ampdu; /* DW3 [3:3] */ 293 u8 ampdu_end_pkt; /* DW3 [4:4] */ 294 u8 amsdu; /* DW3 [5:5] */ 295 u8 amsdu_cut; /* DW3 [6:6] */ 296 u8 last_msdu; /* DW3 [7:7] */ 297 u8 bypass; /* DW3 [8:8] */ 298 u8 crc32; /* DW3 [9:9] */ 299 u8 icverr; /* DW3 [10:10] */ 300 u8 magic_wake; /* DW3 [11:11] */ 301 u8 unicast_wake; /* DW3 [12:12] */ 302 u8 pattern_wake; /* DW3 [13:13] */ 303 u8 get_ch_info; /* DW3 [14:15] */ 304 u8 pattern_idx; /* DW3 [16:20] */ 305 u8 target_idc; /* DW3 [21:23] */ 306 u8 chksum_ofld_en; /* DW3 [24:24] */ 307 u8 with_llc; /* DW3 [25:25] */ 308 u8 rx_statistics; /* DW3 [26:26] */ 309 310 u8 frame_type; /* DW4 [0:1] */ 311 u8 mc; /* DW4 [2:2] */ 312 u8 bc; /* DW4 [3:3] */ 313 u8 more_data; /* DW4 [4:4] */ 314 u8 more_frag; /* DW4 [5:5] */ 315 u8 pwr_bit; /* DW4 [6:6] */ 316 u8 qos; /* DW4 [7:7] */ 317 u8 tid; /* DW4 [8:11] */ 318 u8 eosp; /* DW4 [12:12] */ 319 u8 htc; /* DW4 [13:13] */ 320 u8 q_null; /* DW4 [14:14] */ 321 u16 seq; /* DW4 [16:27] */ 322 u8 frag_num; /* DW4 [28:31] */ 323 324 u8 sec_cam_idx; /* DW5 [0:7] */ 325 u8 addr_cam; /* DW5 [8:15] */ 326 u16 macid; /* DW5 [16:23] */ 327 u8 rx_pl_id; /* DW5 [24:27] */ 328 u8 addr_cam_vld; /* DW5 [28:28] */ 329 u8 addr_fwd_en; /* DW5 [29:29] */ 330 u8 rx_pl_match; /* DW5 [30:30] */ 331 332 u8 mac_addr[6]; /* DW6 [0:31] DW7 [0:15] */ 333 u8 smart_ant; /* DW7 [16:16] */ 334 u8 sec_type; /* DW7 [17:20] */ 335 }; 336 337 338 /** 339 * rtw_pkt_buf_list -- store pakcet from upper layer(ex. ndis, kernel, ethernet..) 340 * @vir_addr: virtual address of this packet 341 * @phy_addr_l: lower 32-bit physical address of this packet 342 * @phy_addr_h: higher 32-bit physical address of this packet 343 * @length: length of this packet 344 * @type: tbd 345 */ 346 struct rtw_pkt_buf_list { 347 u8 *vir_addr; 348 u32 phy_addr_l; 349 u32 phy_addr_h; 350 u16 length; 351 }; 352 353 enum rtw_tx_status { 354 TX_STATUS_TX_DONE, 355 TX_STATUS_TX_FAIL_REACH_RTY_LMT, 356 TX_STATUS_TX_FAIL_LIFETIME_DROP, 357 TX_STATUS_TX_FAIL_MACID_DROP, 358 TX_STATUS_TX_FAIL_SW_DROP, 359 TX_STATUS_TX_FAIL_MAX 360 }; 361 362 #ifdef CONFIG_PHL_TX_DBG 363 typedef 364 void 365 (*CORE_TX_HANDLE_CALLBACK) 366 ( 367 void *drv_priv, 368 void *pctx, 369 bool btx_ok 370 ); 371 372 /** 373 * @en_dbg: if en_dbg = true, phl tx will print tx dbg info for this dbg pkt. set the flag from core layer. 374 * @tx_dbg_pkt_type: Identification type, define by core layer 375 * @core_add_tx_t: core layer add tx req to phl time 376 * @enq_pending_wd_t: phl tx enqueue pending wd page time 377 * @recycle_wd_t: phl tx handle the wp report and recycle wd time 378 */ 379 struct rtw_tx_dbg { 380 bool en_dbg; 381 u16 tx_dbg_pkt_type; 382 u32 core_add_tx_t; 383 u32 enq_pending_wd_t; 384 u32 recycle_wd_t; 385 CORE_TX_HANDLE_CALLBACK statecb; 386 void *pctx; 387 }; 388 #endif /* CONFIG_PHL_TX_DBG */ 389 390 /** 391 * context for tx feedback handler 392 * @drvpriv: driver private 393 * @ctx: private context 394 * @id: module id of this tx packet 395 * @txsts: detail tx status 396 * @txfb_cb: tx feedback handler, currently assign by core layer 397 */ 398 struct rtw_txfb_t { 399 void *drvpriv; 400 void *ctx; 401 enum phl_module_id id; 402 enum rtw_tx_status txsts; 403 void (*txfb_cb)(struct rtw_txfb_t *txfb); 404 }; 405 406 407 /** 408 * the xmit request from core layer, store in xmit phl ring 409 * @list: list 410 * @os_priv: the private context from core layer 411 * @mdata: see structure rtw_t_meta_data 412 * @tx_time: xmit requset tx time, unit in ms 413 * @shortcut_id: short cut id this packet will use in phl/hal 414 * @total_len: the total length of pkt_list 415 * @pkt_cnt: the packet number of pkt_list 416 * @pkt_list: see structure rtw_pkt_buf_list 417 * @cache: 0: pkt_list->phy_addr_l/h use noncache coherent meory(DMA) 418 * @txfb: tx feedback context 419 * 420 * Note, this structure are visible to core, phl and hal layer 421 */ 422 struct rtw_xmit_req { 423 _os_list list; 424 void *os_priv; 425 enum rtw_treq_type treq_type; 426 struct rtw_t_meta_data mdata; 427 u32 tx_time; 428 u8 shortcut_id; 429 u32 total_len; 430 u8 pkt_cnt; 431 u8 *pkt_list; 432 u8 cache; 433 struct rtw_txfb_t *txfb; 434 #ifdef CONFIG_PHL_TX_DBG 435 struct rtw_tx_dbg tx_dbg; 436 #endif /* CONFIG_PHL_TX_DBG */ 437 }; 438 439 /** 440 * the recv packet to core layer, store in recv phl ring 441 * @os_priv: the private context from core layer 442 * @mdata: see structure rtw_r_meta_data 443 * @shortcut_id: short cut id this packet will use in phl/hal 444 * @pkt_cnt: the packet counts of pkt_list 445 * @rx_role: the role to which the RX packet is targeted 446 * @tx_sta: the phl sta that sends this packet 447 * @pkt_list: see structure rtw_pkt_buf_list 448 * 449 * Note, this structure are visible to core, phl and hal layer 450 */ 451 struct rtw_recv_pkt { 452 void *os_priv; 453 struct rtw_r_meta_data mdata; 454 u8 shortcut_id; 455 u8 pkt_cnt; 456 u16 os_netbuf_len; 457 struct rtw_wifi_role_t *rx_role; 458 struct rtw_phl_stainfo_t *tx_sta; 459 struct rtw_pkt_buf_list pkt_list[MAX_RX_BUF_SEG_NUM]; 460 struct rtw_phl_ppdu_phy_info phy_info; 461 }; 462 463 464 /** 465 * the phl ring which stores XMIT requests can be access by both 466 * core and phl, and all the requests in this ring have the same TID value 467 * @tid: the TID value of this phl ring 468 * @dma_ch: dma channel of this phl ring, query by rtw_hal_tx_chnl_mapping() 469 * @tx_thres: tx threshold of this phl ring for batch handling tx requests 470 * @core_idx: record the index of latest entry accessed by core layer 471 * @phl_idx: record the index of handling done by phl layer 472 * @phl_next_idx: record the index of latest entry accessed by phl layer 473 * @entry: store the pointer of requests assigned to this phl ring 474 */ 475 struct rtw_phl_tx_ring { 476 u8 tid; 477 u8 dma_ch; 478 u16 tx_thres; 479 u16 core_idx; 480 _os_atomic phl_idx; 481 _os_atomic phl_next_idx; 482 u8 *entry[MAX_PHL_RING_ENTRY_NUM];/* change to dynamic allocation */ 483 }; 484 485 /** 486 * this structure stores sorted tx rings having frames to tx to the same sta 487 * it will change everytime _phl_check_tring_list() executed 488 * @list: link to the next sta which has frames to transmit 489 * @sleep: true if this macid is under power-saving mode 490 * @has_mgnt: true if this macid has management frames to transmit 491 * @has_hiq: true if this macid has hiq frames to transmit 492 * @sorted_ring: pre-sorted phl ring status list of this macid 493 */ 494 struct phl_tx_plan { 495 _os_list list; 496 bool sleep; 497 bool has_mgnt; 498 bool has_hiq; 499 _os_list sorted_ring; 500 }; 501 502 /** 503 * this phl ring list contains a list of phl TX rings that have the same macid 504 * and different tid, and it can be access by both core and phl 505 * @list: link to next phl ring list with other macid 506 * @macid: the MACID value of this phl ring list 507 * @band: band of this phl ring list, band idx 0~1 508 * @wmm: wmm of this phl ring list, wmm idx 0~1 509 * @port: port of this phl ring list, port idx 0~4 510 * @mbssid: TODO 511 * @phl_ring: the phl rings with same macid but different tid, see rtw_phl_tx_ring 512 * @tx_plan: transmission plan for this macid, decide by _phl_check_tring_list() 513 */ 514 struct rtw_phl_tring_list { 515 _os_list list; 516 u16 macid; 517 u8 band;/*0 or 1*/ 518 u8 wmm;/*0 or 1*/ 519 u8 port; 520 /*u8 mbssid*/ 521 struct rtw_phl_tx_ring phl_ring[MAX_PHL_RING_CAT_NUM];/* tid 0~7, 8:mgnt, 9:hiq */ 522 struct phl_tx_plan tx_plan; 523 }; 524 525 /** 526 * this phl RX ring can be access by both core and phl 527 * @core_idx: record the index of latest entry accessed by core layer 528 * @phl_idx: record the index of handling done by phl layer 529 * @entry: store the pointer of requests assigned to this phl ring 530 */ 531 struct rtw_phl_rx_ring { 532 _os_atomic core_idx; 533 _os_atomic phl_idx; 534 struct rtw_recv_pkt *entry[MAX_PHL_RING_ENTRY_NUM];/* change to dynamic allocation */ 535 }; 536 537 538 /** 539 * the physical address list 540 */ 541 struct rtw_phy_addr_list { 542 _os_list list; 543 u32 phy_addr_l; 544 u32 phy_addr_h; 545 }; 546 547 /** 548 * the phl pkt tx request from phl layer to hal layer 549 * @wd_page: the buffer of wd page allocated by phl and filled by hal 550 * @wd_len: the phl tx shortcut cached wd_page length, if wd_len = 0 means no phl txsc 551 * @wp_seq: pcie only, wp sequence of this phl packet request 552 * @tx_req: see struct rtw_xmit_req 553 * 554 * Note, this structure should be visible to phl and hal layer (hana_todo) 555 */ 556 struct rtw_phl_pkt_req { 557 u8 *wd_page; 558 u8 wd_len; 559 u16 wp_seq; 560 struct rtw_xmit_req *tx_req; 561 }; 562 563 /* 564 0000: WIFI packet 565 0001: PPDU status 566 0010: channel info 567 0011: BB scope mode 568 0100: F2P TX CMD report 569 0101: SS2FW report 570 0110: TX report 571 0111: TX payload release to host 572 1000: DFS report 573 1001: TX payload release to WLCPU 574 1010: C2H packet */ 575 enum rtw_rx_type { 576 RTW_RX_TYPE_WIFI = 0, 577 RTW_RX_TYPE_PPDU_STATUS = 1, 578 RTW_RX_TYPE_CHANNEL_INFO = 2, 579 RTW_RX_TYPE_TX_RPT = 3, 580 RTW_RX_TYPE_TX_WP_RELEASE_HOST = 4, 581 RTW_RX_TYPE_DFS_RPT = 5, 582 RTW_RX_TYPE_C2H = 6, 583 RTW_RX_TYPE_MAX = 0xFF 584 }; 585 586 struct rtw_phl_rx_pkt { 587 _os_list list; 588 enum rtw_rx_type type; 589 u8 *rxbuf_ptr; 590 struct rtw_recv_pkt r; 591 }; 592 593 594 struct rtw_xmit_recycle { 595 u16 wp_seq; 596 struct rtw_xmit_req *tx_req; 597 }; 598 599 enum rtw_traffic_dir { 600 TRAFFIC_UL = 0, /* Uplink */ 601 TRAFFIC_DL, /* Downlink */ 602 TRAFFIC_BALANCE, 603 TRAFFIC_MAX 604 }; 605 606 enum rtw_rx_fltr_mode { 607 RX_FLTR_MODE_SNIFFER, /* 0 */ 608 RX_FLTR_MODE_SCAN, 609 RX_FLTR_MODE_STA_LINKING, 610 RX_FLTR_MODE_STA_NORMAL, 611 RX_FLTR_MODE_AP_NORMAL, 612 RX_FLTR_MODE_RESTORE = 0xFF 613 }; 614 615 #endif /* __PHL_TRX_DEF_H_ */ 616