xref: /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/phl_config.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /******************************************************************************
2*4882a593Smuzhiyun  *
3*4882a593Smuzhiyun  * Copyright(c) 2019 - 2021 Realtek Corporation.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify it
6*4882a593Smuzhiyun  * under the terms of version 2 of the GNU General Public License as
7*4882a593Smuzhiyun  * published by the Free Software Foundation.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * This program is distributed in the hope that it will be useful, but WITHOUT
10*4882a593Smuzhiyun  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12*4882a593Smuzhiyun  * more details.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  *****************************************************************************/
15*4882a593Smuzhiyun #ifndef _PHL_CONFIG_H_
16*4882a593Smuzhiyun #define _PHL_CONFIG_H_
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun /* Define correspoding PHL Feature based on information from the Core */
19*4882a593Smuzhiyun #ifdef PHL_PLATFORM_AP
20*4882a593Smuzhiyun #define PHL_FEATURE_AP
21*4882a593Smuzhiyun #elif defined(PHL_PLATFORM_LINUX) || defined(PHL_PLATFORM_WINDOWS)
22*4882a593Smuzhiyun #define PHL_FEATURE_NIC
23*4882a593Smuzhiyun #else
24*4882a593Smuzhiyun #define PHL_FEATURE_NONE
25*4882a593Smuzhiyun #endif
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun /******************* PLATFORM Section **************************/
28*4882a593Smuzhiyun #ifdef PHL_FEATURE_NONE/* enable compile flag for phl only compilation check */
29*4882a593Smuzhiyun 	#define CONFIG_DFS 1
30*4882a593Smuzhiyun 	#define CONFIG_USB_TX_AGGREGATION
31*4882a593Smuzhiyun 	#define CONFIG_USB_RX_AGGREGATION
32*4882a593Smuzhiyun 	#define CONFIG_USB_TX_PADDING_CHK
33*4882a593Smuzhiyun 	#define CONFIG_LOAD_PHY_PARA_FROM_FILE
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun 	#define CONFIG_WOW
36*4882a593Smuzhiyun 	#define CONFIG_WPA3_SUITEB_SUPPORT
37*4882a593Smuzhiyun 	#define CONFIG_SYNC_INTERRUPT
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun 	#define CONFIG_MR_SUPPORT
40*4882a593Smuzhiyun 	#ifdef CONFIG_MR_SUPPORT
41*4882a593Smuzhiyun 		#define CONFIG_SCC_SUPPORT
42*4882a593Smuzhiyun 		#define CONFIG_MCC_SUPPORT
43*4882a593Smuzhiyun 		#ifdef CONFIG_MCC_SUPPORT
44*4882a593Smuzhiyun 			#define MCC_ROLE_NUM 2
45*4882a593Smuzhiyun 			#define RTW_WKARD_GO_BT_TS_ADJUST_VIA_NOA
46*4882a593Smuzhiyun 			#define RTW_WKARD_HALRF_MCC
47*4882a593Smuzhiyun 			#define RTW_WKARD_TDMRA_AUTO_GET_STAY_ROLE
48*4882a593Smuzhiyun 		#endif /*CONFIG_MCC_SUPPORT*/
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun 		#define CONFIG_DBCC_SUPPORT
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 		#define DBG_PHL_CHAN
53*4882a593Smuzhiyun 		#define DBG_PHL_MR
54*4882a593Smuzhiyun 		#define PHL_MR_PROC_CMD
55*4882a593Smuzhiyun 		#define DBG_CHCTX_RMAP
56*4882a593Smuzhiyun 	#endif /*CONFIG_MR_SUPPORT*/
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	#define DBG_PHL_MAC_REG_RW
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun 	#define CONFIG_RTW_ACS
61*4882a593Smuzhiyun 	#define CONFIG_RX_PSTS_PER_PKT
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun 	#define CONFIG_PHL_TXSC
64*4882a593Smuzhiyun 	#define RTW_PHL_BCN
65*4882a593Smuzhiyun 	#define CONFIG_PHL_SDIO_RX_NETBUF_ALLOC_IN_PHL
66*4882a593Smuzhiyun 	#define CONFIG_PHL_TWT
67*4882a593Smuzhiyun 	#define CONFIG_CMD_DISP
68*4882a593Smuzhiyun 	#ifdef CONFIG_CMD_DISP
69*4882a593Smuzhiyun 		#define CONFIG_PHL_ECSA
70*4882a593Smuzhiyun 		/*#define CONFIG_CMD_DISP_SOLO_MODE*/
71*4882a593Smuzhiyun 		#define CONFIG_PHL_CMD_SCAN
72*4882a593Smuzhiyun 		#define CONFIG_PHL_CMD_SER
73*4882a593Smuzhiyun 		#define CONFIG_PHL_CMD_BTC
74*4882a593Smuzhiyun 	#endif
75*4882a593Smuzhiyun 	#ifdef CONFIG_PCI_HCI
76*4882a593Smuzhiyun 		#define PCIE_TRX_MIT_EN
77*4882a593Smuzhiyun 	#endif
78*4882a593Smuzhiyun 	#define CONFIG_PHL_P2PPS
79*4882a593Smuzhiyun 	#define CONFIG_6GHZ
80*4882a593Smuzhiyun 	#define RTW_WKARD_BFEE_SET_AID
81*4882a593Smuzhiyun 	#define CONFIG_PHL_THERMAL_PROTECT
82*4882a593Smuzhiyun 	#define CONFIG_PHL_TX_DBG
83*4882a593Smuzhiyun 	#define CONFIG_PHL_RELEASE_RPT_ENABLE
84*4882a593Smuzhiyun #endif /* PHL_FEATURE_NONE */
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun #ifdef PHL_PLATFORM_WINDOWS
87*4882a593Smuzhiyun 	#ifndef CONFIG_FSM
88*4882a593Smuzhiyun 		#define CONFIG_FSM
89*4882a593Smuzhiyun 	#endif
90*4882a593Smuzhiyun 	#ifndef CONFIG_CMD_DISP
91*4882a593Smuzhiyun 		#define CONFIG_CMD_DISP
92*4882a593Smuzhiyun 	#endif
93*4882a593Smuzhiyun #endif
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun #ifdef PHL_PLATFORM_LINUX
96*4882a593Smuzhiyun 	/* comment out cfg temporarily */
97*4882a593Smuzhiyun 	/*
98*4882a593Smuzhiyun 	#define CONFIG_FSM
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	#ifndef CONFIG_FSM
101*4882a593Smuzhiyun 		#define CONFIG_CMD_DISP
102*4882a593Smuzhiyun 	#endif
103*4882a593Smuzhiyun 	*/
104*4882a593Smuzhiyun #endif
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun /******************* Feature flags **************************/
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun #ifdef CONFIG_PHL_TEST_SUITE
109*4882a593Smuzhiyun #define CONFIG_PHL_TEST_MP
110*4882a593Smuzhiyun #define CONFIG_PHL_TEST_VERIFY
111*4882a593Smuzhiyun #endif
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun #ifdef CONFIG_CORE_SYNC_INTERRUPT
114*4882a593Smuzhiyun #define CONFIG_SYNC_INTERRUPT
115*4882a593Smuzhiyun #endif
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun #ifdef CONFIG_WOW
118*4882a593Smuzhiyun #define CONFIG_WOWLAN
119*4882a593Smuzhiyun /* #define RTW_WKARD_WOW_SKIP_AOAC_RPT */
120*4882a593Smuzhiyun /* #define RTW_WKARD_WOW_SKIP_WOW_CAM_CONFIG */
121*4882a593Smuzhiyun #define RTW_WKARD_WOW_L2_PWR
122*4882a593Smuzhiyun #define DBG_RST_BDRAM_TIME
123*4882a593Smuzhiyun #endif
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun #define DBG_PHY_ON_TIME
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun /*CONFIG_IFACE_NUMBER*/
128*4882a593Smuzhiyun #ifdef CONFIG_IFACE_NUMBER
129*4882a593Smuzhiyun #define MAX_WIFI_ROLE_NUMBER CONFIG_IFACE_NUMBER
130*4882a593Smuzhiyun #else
131*4882a593Smuzhiyun #define MAX_WIFI_ROLE_NUMBER 5
132*4882a593Smuzhiyun #endif
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun #ifdef CONFIG_CONCURRENT_MODE
135*4882a593Smuzhiyun #define CONFIG_MR_SUPPORT
136*4882a593Smuzhiyun #endif
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun #ifdef CONFIG_REUSED_FWDL_BUF
139*4882a593Smuzhiyun 	#define CONFIG_PHL_REUSED_FWDL_BUF
140*4882a593Smuzhiyun #endif
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun #ifdef CONFIG_MR_SUPPORT
143*4882a593Smuzhiyun #define CONFIG_SCC_SUPPORT
144*4882a593Smuzhiyun #define CONFIG_MCC_SUPPORT
145*4882a593Smuzhiyun #ifdef CONFIG_MCC_SUPPORT
146*4882a593Smuzhiyun #define MCC_ROLE_NUM 2
147*4882a593Smuzhiyun #define RTW_WKARD_GO_BT_TS_ADJUST_VIA_NOA
148*4882a593Smuzhiyun #define RTW_WKARD_HALRF_MCC
149*4882a593Smuzhiyun #define RTW_WKARD_TDMRA_AUTO_GET_STAY_ROLE
150*4882a593Smuzhiyun #endif /*CONFIG_MCC_SUPPORT*/
151*4882a593Smuzhiyun /*#define CONFIG_DBCC_SUPPORT*/
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun #define DBG_PHL_CHAN
154*4882a593Smuzhiyun #define DBG_PHL_MR
155*4882a593Smuzhiyun #define PHL_MR_PROC_CMD
156*4882a593Smuzhiyun #define DBG_CHCTX_RMAP
157*4882a593Smuzhiyun #endif
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun #define DBG_PHL_STAINFO
160*4882a593Smuzhiyun #define PHL_MAX_STA_NUM 128
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun /**** CONFIG_CMD_DISP ***/
163*4882a593Smuzhiyun #ifdef DISABLE_CMD_DISPR
164*4882a593Smuzhiyun #undef CONFIG_CMD_DISP
165*4882a593Smuzhiyun #endif
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun #ifdef CONFIG_CMD_DISP
168*4882a593Smuzhiyun /* enable SOLO mode define to create seperated background thread per dispatcher,
169*4882a593Smuzhiyun  * otherwise, all dispatcher would share single background thread, which is in share mode.
170*4882a593Smuzhiyun */
171*4882a593Smuzhiyun /*#define CONFIG_CMD_DISP_SOLO_MODE*/
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun /* Enable Self-Defined Sequence feature for sender to rearrange dispatch order,
174*4882a593Smuzhiyun  * Since this is not a mandatory feature and would have addiional memory cost (arround 2200 Bytes)
175*4882a593Smuzhiyun  * Disable by default.
176*4882a593Smuzhiyun */
177*4882a593Smuzhiyun /*#define CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ*/
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun #ifndef CONFIG_FSM
180*4882a593Smuzhiyun 	#define CONFIG_SND_CMD
181*4882a593Smuzhiyun #endif
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun #define CONFIG_PHL_CMD_SCAN
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun #ifdef CONFIG_CMD_SER
186*4882a593Smuzhiyun #define CONFIG_PHL_CMD_SER
187*4882a593Smuzhiyun #endif
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun #define CONFIG_PHL_CMD_BTC
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun #ifdef CONFIG_MSG_NUM
192*4882a593Smuzhiyun 	#define CONFIG_PHL_MSG_NUM CONFIG_MSG_NUM
193*4882a593Smuzhiyun #endif
194*4882a593Smuzhiyun #endif /**** CONFIG_CMD_DISP ***/
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun #define CONFIG_GEN_GIT_INFO 1
197*4882a593Smuzhiyun /*#define CONFIG_NEW_HALMAC_INTERFACE*/
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun #define CONFIG_BTCOEX
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun #ifdef CONFIG_USB_TX_PADDING_CHK
202*4882a593Smuzhiyun #define CONFIG_PHL_USB_TX_PADDING_CHK
203*4882a593Smuzhiyun #endif
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun #ifdef CONFIG_USB_TX_AGGREGATION
206*4882a593Smuzhiyun #define CONFIG_PHL_USB_TX_AGGREGATION
207*4882a593Smuzhiyun #endif
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun #ifdef CONFIG_USB_RX_AGGREGATION
210*4882a593Smuzhiyun #define CONFIG_PHL_USB_RX_AGGREGATION
211*4882a593Smuzhiyun #endif
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun #ifdef CONFIG_DFS_MASTER
214*4882a593Smuzhiyun #define CONFIG_PHL_DFS
215*4882a593Smuzhiyun #endif
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun #ifdef CONFIG_PHL_DFS
218*4882a593Smuzhiyun /*#define CONFIG_PHL_DFS_REGD_FCC*/
219*4882a593Smuzhiyun /*#define CONFIG_PHL_DFS_REGD_JAP*/
220*4882a593Smuzhiyun #define CONFIG_PHL_DFS_REGD_ETSI
221*4882a593Smuzhiyun #endif
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun #ifdef CONFIG_WPP
224*4882a593Smuzhiyun #define CONFIG_PHL_WPP
225*4882a593Smuzhiyun #endif
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun #ifdef CONFIG_TCP_CSUM_OFFLOAD_RX
228*4882a593Smuzhiyun #define CONFIG_PHL_CSUM_OFFLOAD_RX
229*4882a593Smuzhiyun #endif
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun #ifdef CONFIG_RX_PSTS_PER_PKT
232*4882a593Smuzhiyun #define CONFIG_PHL_RX_PSTS_PER_PKT
233*4882a593Smuzhiyun #define RTW_WKARD_DISABLE_PSTS_PER_PKT_DATA
234*4882a593Smuzhiyun #endif
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun #ifdef CONFIG_SDIO_RX_NETBUF_ALLOC_IN_PHL
237*4882a593Smuzhiyun #define CONFIG_PHL_SDIO_RX_NETBUF_ALLOC_IN_PHL
238*4882a593Smuzhiyun #endif
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun #ifdef CONFIG_SDIO_READ_RXFF_IN_INT
241*4882a593Smuzhiyun #define CONFIG_PHL_SDIO_READ_RXFF_IN_INT
242*4882a593Smuzhiyun #endif
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun #ifdef CONFIG_ECSA
245*4882a593Smuzhiyun #define CONFIG_PHL_ECSA
246*4882a593Smuzhiyun #ifdef CONFIG_ECSA_EXTEND_OPTION
247*4882a593Smuzhiyun #define CONFIG_PHL_ECSA_EXTEND_OPTION
248*4882a593Smuzhiyun #endif
249*4882a593Smuzhiyun #endif
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun #ifdef CONFIG_TWT
252*4882a593Smuzhiyun #define CONFIG_PHL_TWT
253*4882a593Smuzhiyun #endif
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun #ifdef CONFIG_RA_TXSTS_DBG
256*4882a593Smuzhiyun #define CONFIG_PHL_RA_TXSTS_DBG
257*4882a593Smuzhiyun #endif
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun #ifdef CONFIG_RELEASE_RPT
260*4882a593Smuzhiyun #define CONFIG_PHL_RELEASE_RPT_ENABLE
261*4882a593Smuzhiyun #endif
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun #ifdef CONFIG_PS_FW_DBG
264*4882a593Smuzhiyun #define CONFIG_PHL_PS_FW_DBG
265*4882a593Smuzhiyun #endif
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun #ifdef CONFIG_P2PPS
268*4882a593Smuzhiyun #define CONFIG_PHL_P2PPS
269*4882a593Smuzhiyun #endif
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun #ifdef CONFIG_TX_DBG
272*4882a593Smuzhiyun #define CONFIG_PHL_TX_DBG
273*4882a593Smuzhiyun #endif
274*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI
275*4882a593Smuzhiyun #ifdef CONFIG_PCIE_TRX_MIT
276*4882a593Smuzhiyun #define PCIE_TRX_MIT_EN
277*4882a593Smuzhiyun #endif
278*4882a593Smuzhiyun #endif
279*4882a593Smuzhiyun #ifdef CONFIG_THERMAL_PROTECT
280*4882a593Smuzhiyun #define CONFIG_PHL_THERMAL_PROTECT
281*4882a593Smuzhiyun #endif
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun #ifdef CONFIG_RX_BATCH_IND
284*4882a593Smuzhiyun #define PHL_RX_BATCH_IND
285*4882a593Smuzhiyun #endif
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun #ifdef CONFIG_TDLS
288*4882a593Smuzhiyun #define CONFIG_PHL_TDLS
289*4882a593Smuzhiyun #endif
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun #ifdef CONFIG_SDIO_HCI
292*4882a593Smuzhiyun /* For SDIO TX TP TST - START */
293*4882a593Smuzhiyun #ifdef CONFIG_SDIO_TX_AGG_NUM_MAX
294*4882a593Smuzhiyun #define PHL_SDIO_TX_AGG_MAX	CONFIG_SDIO_TX_AGG_NUM_MAX
295*4882a593Smuzhiyun #endif /* CONFIG_SDIO_TX_AGG_NUM_MAX */
296*4882a593Smuzhiyun #define SDIO_TX_THREAD			/* Use dedicate thread for SDIO TX */
297*4882a593Smuzhiyun /* For SDIO TX TP TST - ENDT */
298*4882a593Smuzhiyun #endif /* CONFIG_SDIO_HCI */
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun #ifdef CONFIG_MAC_REG_RW_CHK
301*4882a593Smuzhiyun #define DBG_PHL_MAC_REG_RW
302*4882a593Smuzhiyun #endif
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun #ifdef CONFIG_RTW_REDUCE_MEM
305*4882a593Smuzhiyun #define CONFIG_PHL_REDUCE_MEM
306*4882a593Smuzhiyun #endif
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun /******************* WKARD flags **************************/
309*4882a593Smuzhiyun #define RTW_WKARD_P2PPS_REFINE
310*4882a593Smuzhiyun #define RTW_WKARD_P2PPS_SINGLE_NOA
311*4882a593Smuzhiyun #define RTW_WKARD_P2PPS_NOA_MCC
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun #ifdef PHL_PLATFORM_LINUX
314*4882a593Smuzhiyun #define RTW_WKARD_RF_CR_DUMP
315*4882a593Smuzhiyun #define RTW_WKARD_LINUX_CMD_WKARD
316*4882a593Smuzhiyun #endif
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun #ifdef PHL_PLATFORM_WINDOWS
319*4882a593Smuzhiyun /* Workaround for doing hal reset in changing MP mode will lost the mac entry */
320*4882a593Smuzhiyun #define RTW_WKARD_MP_MODE_CHANGE
321*4882a593Smuzhiyun #define RTW_WKARD_WIN_TRX_BALANCE
322*4882a593Smuzhiyun #define RTW_WKARD_DYNAMIC_LTR
323*4882a593Smuzhiyun #define RTW_WKARD_GET_PROCESSOR_ID
324*4882a593Smuzhiyun #endif
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun #define RTW_WKARD_PHY_CAP
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun #define RTW_WKARD_BTC_STBC_CAP
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun #define RTW_WKARD_LAMODE
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun #define RTW_WKARD_TXSC
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun #define RTW_WKARD_BB_C2H
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun /*
337*4882a593Smuzhiyun  * One workaround of EFUSE operation
338*4882a593Smuzhiyun  *  1. Dump EFUSE with FW fail
339*4882a593Smuzhiyun  */
340*4882a593Smuzhiyun #define RTW_WKARD_EFUSE_OPERATION
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun #define RTW_WKARD_STA_BCN_INTERVAL
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun #define RTW_WKARD_SER_L1_EXPIRE
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun #ifdef CONFIG_USB_HCI
347*4882a593Smuzhiyun #define RTW_WKARD_SER_USB_POLLING_EVENT
348*4882a593Smuzhiyun #endif
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun /* #define RTW_WKARD_SER_USB_DISABLE_L1_RCVY_FLOW */
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun #define RTW_WKARD_BTC_RFETYPE
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun #define RTW_WKARD_TXBD_UPD_LMT 	/* 8852AE/8852BE txbd index update limitation */
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun #ifdef CONFIG_WPA3_SUITEB_SUPPORT
357*4882a593Smuzhiyun #define RTW_WKARD_HW_MGNT_GCMP_256_DISABLE
358*4882a593Smuzhiyun #endif
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun /* Workaround for cmac table config
361*4882a593Smuzhiyun  * - Default is disabled until halbb is ready
362*4882a593Smuzhiyun  * - This workaround will be removed once fw handles this cfg
363*4882a593Smuzhiyun  */
364*4882a593Smuzhiyun /*#define RTW_WKARD_DEF_CMACTBL_CFG*/
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun /* Workaround for efuse read hidden report
367*4882a593Smuzhiyun  * - Default is disabled until halmac is ready
368*4882a593Smuzhiyun  */
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun #define RTW_WKARD_PRELOAD_TRX_RESET
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun /* Workaround for cmac table config
373*4882a593Smuzhiyun  * - This workaround will be removed once fw handles this cfg
374*4882a593Smuzhiyun  */
375*4882a593Smuzhiyun #define RTW_WKARD_DEF_CMACTBL_CFG
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun #define RTW_WKARD_USB_TXAGG_BULK_END_WD
378*4882a593Smuzhiyun #ifdef CONFIG_HOMOLOGATION
379*4882a593Smuzhiyun #define CONFIG_PHL_HOMOLOGATION
380*4882a593Smuzhiyun #endif
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun #ifdef RTW_WKARD_TX_DISABLE_BFEE
383*4882a593Smuzhiyun #define RTW_WKARD_DYNAMIC_BFEE_CAP
384*4882a593Smuzhiyun #endif
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun #ifdef RTW_WKARD_NTFY_MEDIA_STS
387*4882a593Smuzhiyun #define RTW_WKARD_PHL_NTFY_MEDIA_STS
388*4882a593Smuzhiyun #endif
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun #ifdef RTW_WKARD_PHY_INFO_NTFY
391*4882a593Smuzhiyun #define CONFIG_PHY_INFO_NTFY
392*4882a593Smuzhiyun #endif
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun #ifdef PHL_PLATFORM_WINDOWS
395*4882a593Smuzhiyun #define CONFIG_WOW_WITH_SER
396*4882a593Smuzhiyun #endif
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun #ifdef PHL_PLATFORM_WINDOWS
399*4882a593Smuzhiyun #define CONFIG_DBG_H2C_TX
400*4882a593Smuzhiyun #endif
401*4882a593Smuzhiyun 
402*4882a593Smuzhiyun /*
403*4882a593Smuzhiyun  * Workaround for MRC bk module call phl_mr_offch_hdl with scan_issue_null_data
404*4882a593Smuzhiyun  * ops, this should be replaced with phl issue null data function.
405*4882a593Smuzhiyun  */
406*4882a593Smuzhiyun #define RTW_WKARD_MRC_ISSUE_NULL_WITH_SCAN_OPS
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun /*
409*4882a593Smuzhiyun  * Workaround for phl_mr_offch_hdl sleep after issue null data,
410*4882a593Smuzhiyun  * - This workaround will be removed once tx report is ready
411*4882a593Smuzhiyun  */
412*4882a593Smuzhiyun #ifndef RTW_WKARD_TX_NULL_WD_RP
413*4882a593Smuzhiyun #define RTW_WKARD_ISSUE_NULL_SLEEP_PROTECTION
414*4882a593Smuzhiyun #endif
415*4882a593Smuzhiyun #ifdef RTW_WKARD_LPS_IQK_TWICE
416*4882a593Smuzhiyun #define RTW_WKARD_PHL_LPS_IQK_TWICE
417*4882a593Smuzhiyun #endif
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun #ifdef RTW_WKARD_FSM_SCAN_PASSIVE_TO_ACTIVE
420*4882a593Smuzhiyun #define RTW_WKARD_PHL_FSM_SCAN_PASSIVE_TO_ACTIVE
421*4882a593Smuzhiyun #endif
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun #define RTW_WKARD_BUSCAP_IN_HALSPEC
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun #define RTW_WKARD_IBSS_SNIFFER_MODE
426*4882a593Smuzhiyun 
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun #define RTW_WKARD_SINGLE_PATH_RSSI
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun /* #define CONFIG_6GHZ */
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun #define RTW_WKARD_BFEE_DISABLE_NG16
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun #define RTW_WKARD_HW_WMM_ALLOCATE
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun #ifdef RTW_WKARD_BFEE_AID
438*4882a593Smuzhiyun #define RTW_WKARD_BFEE_SET_AID
439*4882a593Smuzhiyun #endif
440*4882a593Smuzhiyun 
441*4882a593Smuzhiyun #define RTW_WKARD_AP_CLIENT_ADD_DEL_NTY
442*4882a593Smuzhiyun 
443*4882a593Smuzhiyun #ifdef RTW_WKARD_DISABLE_2G40M_ULOFDMA
444*4882a593Smuzhiyun #define RTW_WKARD_BB_DISABLE_STA_2G40M_ULOFDMA
445*4882a593Smuzhiyun #endif
446*4882a593Smuzhiyun 
447*4882a593Smuzhiyun #define RTW_WKARD_CHECK_STAINFO_DOUBLE_DEL
448*4882a593Smuzhiyun 
449*4882a593Smuzhiyun #endif /*_PHL_CONFIG_H_*/
450