1 /** @file */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2019 Realtek Corporation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 ******************************************************************************/ 16 17 #ifndef _MAC_AX_RXDESC_H_ 18 #define _MAC_AX_RXDESC_H_ 19 20 /* dword0 */ 21 #define AX_RXD_RPKT_LEN_SH 0 22 #define AX_RXD_RPKT_LEN_MSK 0x3fff 23 #define AX_RXD_SHIFT_SH 14 24 #define AX_RXD_SHIFT_MSK 0x3 25 #define AX_RXD_WL_HD_IV_LEN_SH 16 26 #define AX_RXD_WL_HD_IV_LEN_MSK 0x3f 27 #define AX_RXD_BB_SEL BIT(22) 28 #define AX_RXD_MAC_INFO_VLD BIT(23) 29 #define AX_RXD_RPKT_TYPE_SH 24 30 #define AX_RXD_RPKT_TYPE_MSK 0xf 31 #define AX_RXD_DRV_INFO_SIZE_SH 28 32 #define AX_RXD_DRV_INFO_SIZE_MSK 0x7 33 #define AX_RXD_LONG_RXD BIT(31) 34 35 /* dword1 */ 36 #define AX_RXD_PPDU_TYPE_SH 0 37 #define AX_RXD_PPDU_TYPE_MSK 0xf 38 #define AX_RXD_PPDU_CNT_SH 4 39 #define AX_RXD_PPDU_CNT_MSK 0x7 40 #define AX_RXD_SR_EN BIT(7) 41 #define AX_RXD_USER_ID_SH 8 42 #define AX_RXD_USER_ID_MSK 0xff 43 #define AX_RXD_USER_ID_v1_SH 8 44 #define AX_RXD_USER_ID_v1_MSK 0x3f 45 #define AX_RXD_RX_DATARATE_SH 16 46 #define AX_RXD_RX_DATARATE_MSK 0x1ff 47 #define AX_RXD_RX_GI_LTF_SH 25 48 #define AX_RXD_RX_GI_LTF_MSK 0x7 49 #define AX_RXD_NON_SRG_PPDU BIT(28) 50 #define AX_RXD_INTER_PPDU BIT(29) 51 #define AX_RXD_NON_SRG_PPDU_v1 BIT(14) 52 #define AX_RXD_INTER_PPDU_v1 BIT(15) 53 #define AX_RXD_BW_SH 30 54 #define AX_RXD_BW_MSK 0x3 55 #define AX_RXD_BW_v1_SH 29 56 #define AX_RXD_BW_v1_MSK 0x7 57 58 /* dword2 */ 59 #define AX_RXD_FREERUN_CNT_SH 0 60 #define AX_RXD_FREERUN_CNT_MSK 0xffffffff 61 62 /* dword3 */ 63 #define AX_RXD_A1_MATCH BIT(0) 64 #define AX_RXD_SW_DEC BIT(1) 65 #define AX_RXD_HW_DEC BIT(2) 66 #define AX_RXD_AMPDU BIT(3) 67 #define AX_RXD_AMPDU_END_PKT BIT(4) 68 #define AX_RXD_AMSDU BIT(5) 69 #define AX_RXD_AMSDU_CUT BIT(6) 70 #define AX_RXD_LAST_MSDU BIT(7) 71 #define AX_RXD_BYPASS BIT(8) 72 #define AX_RXD_CRC32_ERR BIT(9) 73 #define AX_RXD_ICV_ERR BIT(10) 74 #define AX_RXD_MAGIC_WAKE BIT(11) 75 #define AX_RXD_UNICAST_WAKE BIT(12) 76 #define AX_RXD_PATTERN_WAKE BIT(13) 77 #define AX_RXD_GET_CH_INFO_SH 14 78 #define AX_RXD_GET_CH_INFO_MSK 0x3 79 #define AX_RXD_PATTERN_IDX_SH 16 80 #define AX_RXD_PATTERN_IDX_MSK 0x1f 81 #define AX_RXD_TARGET_IDC_SH 21 82 #define AX_RXD_TARGET_IDC_MSK 0x7 83 #define AX_RXD_CHKSUM_OFFLOAD_EN BIT(24) 84 #define AX_RXD_WITH_LLC BIT(25) 85 #define AX_RXD_RX_STATISTICS BIT(26) 86 87 /* dword4 */ 88 #define AX_RXD_TYPE_SH 0 89 #define AX_RXD_TYPE_MSK 0x3 90 #define AX_RXD_MC BIT(2) 91 #define AX_RXD_BC BIT(3) 92 #define AX_RXD_MD BIT(4) 93 #define AX_RXD_MF BIT(5) 94 #define AX_RXD_PWR BIT(6) 95 #define AX_RXD_QOS BIT(7) 96 #define AX_RXD_TID_SH 8 97 #define AX_RXD_TID_MSK 0xf 98 #define AX_RXD_EOSP BIT(12) 99 #define AX_RXD_HTC BIT(13) 100 #define AX_RXD_QNULL BIT(14) 101 #define AX_RXD_SEQ_SH 16 102 #define AX_RXD_SEQ_MSK 0xfff 103 #define AX_RXD_FRAG_SH 28 104 #define AX_RXD_FRAG_MSK 0xf 105 106 /* dword5 */ 107 #define AX_RXD_SEC_CAM_IDX_SH 0 108 #define AX_RXD_SEC_CAM_IDX_MSK 0xff 109 #define AX_RXD_ADDR_CAM_SH 8 110 #define AX_RXD_ADDR_CAM_MSK 0xff 111 #define AX_RXD_MAC_ID_SH 16 112 #define AX_RXD_MAC_ID_MSK 0xff 113 #define AX_RXD_RX_PL_ID_SH 24 114 #define AX_RXD_RX_PL_ID_MSK 0xf 115 #define AX_RXD_ADDR_CAM_VLD BIT(28) 116 #define AX_RXD_ADDR_FWD_EN BIT(29) 117 #define AX_RXD_RX_PL_MATCH BIT(30) 118 119 /* dword6 */ 120 #define AX_RXD_MAC_ADDR_SH 0 121 #define AX_RXD_MAC_ADDR_MSK 0xffffffff 122 123 /* dword7 */ 124 #define AX_RXD_MAC_ADDR_H_SH 0 125 #define AX_RXD_MAC_ADDR_H_MSK 0xffff 126 #define AX_RXD_SMART_ANT BIT(16) 127 #define AX_RXD_SEC_TYPE_SH 17 128 #define AX_RXD_SEC_TYPE_MSK 0xf 129 #define AX_RXD_HDR_CNV BIT(21) 130 #define AX_RXD_HDR_OFFSET_SH 22 131 #define AX_RXD_HDR_OFFSET_MSK 0x1f 132 #define AX_RXD_BIP_KEYID BIT(27) 133 #define AX_RXD_BIP_ENC BIT(28) 134 135 #define RXD_S_RPKT_TYPE_WIFI 0 136 #define RXD_S_RPKT_TYPE_PPDU 1 137 #define RXD_S_RPKT_TYPE_CH_INFO 2 138 #define RXD_S_RPKT_TYPE_BB_SCORE 3 139 #define RXD_S_RPKT_TYPE_TXCMD_RPT 4 140 #define RXD_S_RPKT_TYPE_SS2FW_RPT 5 141 #define RXD_S_RPKT_TYPE_TXRPT 6 142 #define RXD_S_RPKT_TYPE_PLDREL_HOST 7 143 #define RXD_S_RPKT_TYPE_DFS_RPT 8 144 #define RXD_S_RPKT_TYPE_PLDREL_WLCPU 9 145 #define RXD_S_RPKT_TYPE_C2H 10 146 #define RXD_S_RPKT_TYPE_CSI 11 147 #define RXD_S_RPKT_TYPE_CQI 12 148 #define RXD_S_RPKT_TYPE_H2C 13 149 #define RXD_S_RPKT_TYPE_FWDL 14 150 151 #endif 152 153