1 #ifndef __INC_BTC_FW_DEF_H__ 2 #define __INC_BTC_FW_DEF_H__ 3 4 #pragma pack(push) 5 #pragma pack(1) 6 /* 7 * shared FW Definition 8 */ 9 10 #define CXMREG_MAX 30 11 #define FCXDEF_STEP 50 /* MUST fw_step size*/ 12 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 13 14 enum btc_bt_rfk_counter { 15 BTC_BCNT_RFK_REQ = 0, 16 BTC_BCNT_RFK_GO = 1, 17 BTC_BCNT_RFK_REJECT = 2, 18 BTC_BCNT_RFK_FAIL = 3, 19 BTC_BCNT_RFK_TIMEOUT = 4, 20 BTC_BCNT_RFK_MAX 21 }; 22 23 struct btc_rpt_ctrl_wl_fw_info { 24 u32 cx_ver; /* match which driver's coex version */ 25 u32 cx_offload; 26 u32 fw_ver; 27 }; 28 29 struct btc_rpt_ctrl_info { 30 u32 cnt; /* fw report counter */ 31 u32 en; /* report map */ 32 u32 para; /* not used */ 33 34 u32 cnt_c2h; /* fw send c2h counter */ 35 u32 cnt_h2c; /* fw recv h2c counter */ 36 u32 len_c2h; /* The total length of the last C2H */ 37 }; 38 39 struct btc_rpt_ctrl_a2dp_empty { 40 u32 cnt_empty; /* a2dp empty count */ 41 u32 cnt_flowctrl; /* a2dp empty flow control counter */ 42 u32 cnt_tx; 43 u32 cnt_ack; 44 u32 cnt_nack; 45 }; 46 47 struct btc_rpt_ctrl_bt_mailbox { 48 u32 cnt_send_ok; /* fw send mailbox ok counter */ 49 u32 cnt_send_fail; /* fw send mailbox fail counter */ 50 u32 cnt_recv; /* fw recv mailbox counter */ 51 struct btc_rpt_ctrl_a2dp_empty a2dp; 52 }; 53 54 #define FCX_BTCRPT_VER 2 55 struct fbtc_rpt_ctrl { 56 u8 fver; 57 u8 rsvd; 58 u16 rsvd1; 59 struct btc_rpt_ctrl_info rpt_info; 60 struct btc_rpt_ctrl_wl_fw_info wl_fw_info; 61 struct btc_rpt_ctrl_bt_mailbox bt_mbx_info; 62 u32 bt_rfk_cnt[BTC_BCNT_RFK_MAX]; 63 }; 64 65 /* 66 * ============== TDMA related ============== 67 */ 68 enum fbtc_tdma_template { 69 CXTD_OFF = 0x0, 70 CXTD_OFF_B2, 71 CXTD_OFF_EXT, 72 CXTD_FIX, 73 CXTD_PFIX, 74 CXTD_AUTO, 75 CXTD_PAUTO, 76 CXTD_AUTO2, 77 CXTD_PAUTO2, 78 CXTD_MAX 79 }; 80 81 enum fbtc_tdma_type { 82 CXTDMA_OFF = 0x0, /* tdma off */ 83 CXTDMA_FIX = 0x1, /* fixed slot */ 84 CXTDMA_AUTO = 0x2, /* auto slot */ 85 CXTDMA_AUTO2 = 0x3, /* extended auto slot */ 86 CXTDMA_MAX 87 }; 88 89 enum fbtc_tdma_rx_flow_ctrl { 90 CXFLC_OFF = 0x0, /* rx flow off */ 91 CXFLC_NULLP = 0x1, /* Null/Null-P */ 92 CXFLC_QOSNULL = 0x2, /* QOS Null/Null-P */ 93 CXFLC_CTS = 0x3, /* CTS to Self control */ 94 CXFLC_MAX 95 }; 96 97 enum fbtc_tdma_wlan_tx_pause { 98 CXTPS_OFF = 0x0, /* no wl tx pause*/ 99 CXTPS_ON = 0x1, 100 CXTPS_MAX 101 }; 102 103 /* define if ext-ctrl-slot allowed while TDMA off */ 104 enum fbtc_ext_ctrl_type { 105 CXECTL_OFF = 0x0, /* tdma off */ 106 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 107 CXECTL_EXT = 0x2, 108 CXECTL_MAX 109 }; 110 111 union fbtc_rxflct { 112 u8 val; 113 u8 type: 3; 114 u8 tgln_n: 5; 115 }; 116 117 #define FCX_TDMA_VER 2 118 struct fbtc_tdma { 119 u8 type; /* refer to fbtc_tdma_type*/ 120 u8 rxflctrl; /* refer to fbtc_tdma_rx_flow_ctrl */ 121 u8 txflctrl; /* If WL stop Tx while enter BT-slot */ 122 u8 wtgle_n; /* wl slot toggle every toggle_n cycles */ 123 u8 leak_n; /* every leak_n cycle do leak detection */ 124 u8 ext_ctrl; /* refer to fbtc_ext_ctrl_type*/ 125 /* send rxflctrl to which role 126 * enum role_type, default: 0 for single-role 127 * if multi-role: [7:4] second-role, [3:0] fisrt-role 128 */ 129 u8 rxflctrl_role; 130 u8 rsvd; 131 }; 132 133 struct fbtc_1tdma { 134 u8 fver; 135 u8 rsvd; 136 u16 rsvd1; 137 struct fbtc_tdma tdma; 138 }; 139 140 141 /* 142 * ============== SLOT related ============== 143 */ 144 enum { /* slot */ 145 CXST_OFF = 0x0, 146 CXST_B2W = 0x1, 147 CXST_W1 = 0x2, 148 CXST_W2 = 0x3, 149 CXST_W2B = 0x4, 150 CXST_B1 = 0x5, 151 CXST_B2 = 0x6, 152 CXST_B3 = 0x7, 153 CXST_B4 = 0x8, 154 CXST_LK = 0x9, 155 CXST_BLK = 0xa, 156 CXST_E2G = 0xb, /* for ext-control-slot 2G*/ 157 CXST_E5G = 0xc, /* for ext-control-slot 5G*/ 158 CXST_EBT = 0xd, /* for ext-control-slot BT*/ 159 CXST_ENULL = 0xe, /* for ext-control-slot Null*/ 160 CXST_WLK = 0xf, /* for WL link slot */ 161 CXST_W1FDD = 0x10, 162 CXST_B1FDD = 0x11, 163 CXST_MAX = 0x12 /* The max slot must be even*/ 164 }; 165 166 enum { 167 CXEVNT_TDMA_ENTRY = 0x0, 168 CXEVNT_WL_TMR, 169 CXEVNT_B1_TMR, 170 CXEVNT_B2_TMR, 171 CXEVNT_B3_TMR, 172 CXEVNT_B4_TMR, 173 CXEVNT_W2B_TMR, 174 CXEVNT_B2W_TMR, 175 CXEVNT_BCN_EARLY, 176 CXEVNT_A2DP_EMPTY, 177 CXEVNT_LK_END, 178 CXEVNT_RX_ISR, 179 CXEVNT_RX_FC0, 180 CXEVNT_RX_FC1, 181 CXEVNT_BT_RELINK, 182 CXEVNT_BT_RETRY, 183 CXEVNT_E2G, 184 CXEVNT_E5G, 185 CXEVNT_EBT, 186 CXEVNT_ENULL, 187 CXEVNT_DRV_WLK, 188 CXEVNT_BCN_OK, 189 CXEVNT_BT_CHANGE, 190 CXEVNT_EBT_EXTEND, 191 CXEVNT_E2G_NULL1, 192 CXEVNT_MAX 193 }; 194 195 enum { 196 CXBCN_ALL = 0x0, 197 CXBCN_ALL_OK, 198 CXBCN_BT_SLOT, 199 CXBCN_BT_OK, 200 CXBCN_MAX 201 }; 202 203 /* Slot isolation Definition 204 * Same definition as WL RX Definition 205 */ 206 enum { 207 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 208 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 209 CXSTYPE_MAX 210 }; 211 212 enum { /* TIME */ 213 CXT_BT = 0x0, 214 CXT_WL = 0x1, 215 CXT_MAX 216 }; 217 218 enum { /* TIME-A2DP */ 219 CXT_FLCTRL_OFF = 0x0, 220 CXT_FLCTRL_ON = 0x1, 221 CXT_FLCTRL_MAX 222 }; 223 224 enum { /* STEP TYPE */ 225 CXSTEP_NONE = 0x0, 226 CXSTEP_EVNT = 0x1, 227 CXSTEP_SLOT = 0x2, 228 CXSTEP_MAX 229 }; 230 231 enum { 232 CXNULL_STATE_0 = 0, 233 CXNULL_STATE_1 = 1, 234 CXNULL_STATE_MAX = 2 235 }; 236 237 enum { 238 CXNULL_FAIL = 0, 239 CXNULL_OK = 1, 240 CXNULL_LATE = 2, 241 CXNULL_RETRY = 3, 242 CXNULL_TX = 4, 243 CXNULL_MAX = 5 244 }; 245 246 struct fbtc_set_drvinfo { 247 u8 type; 248 u8 len; 249 u8 buf[1]; 250 }; 251 252 #define FCX_GPIODBG_VER 1 253 #define BTC_DBG_MAX1 32 254 struct fbtc_gpio_dbg { 255 u8 fver; 256 u8 rsvd; 257 u16 rsvd2; 258 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 259 u32 pre_state; /* the debug signal is 1 or 0 */ 260 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position mapping */ 261 }; 262 263 #define FCX_MREG_VER 1 264 struct fbtc_mreg_val { 265 u8 fver; 266 u8 reg_num; 267 u16 rsvd; 268 u32 mreg_val[CXMREG_MAX]; 269 }; 270 271 struct fbtc_mreg { 272 u16 type; 273 u16 bytes; 274 u32 offset; 275 }; 276 277 #define FCX_SLOT_VER 1 278 struct fbtc_slot { 279 u16 dur; /* slot duration */ 280 u32 cxtbl; 281 u16 cxtype; 282 }; 283 284 struct fbtc_1slot { 285 u8 fver; 286 u8 sid; /* slot id */ 287 struct fbtc_slot slot; 288 }; 289 290 struct fbtc_slots { 291 u8 fver; 292 u8 tbl_num; 293 u16 rsvd; 294 u32 update_map; 295 struct fbtc_slot slot[CXST_MAX]; 296 }; 297 298 #define FCX_STEP_VER 3 299 struct fbtc_step { 300 u8 type; 301 u8 val; 302 u16 difft; 303 }; 304 305 struct fbtc_steps { 306 u8 fver; 307 u8 en; 308 u16 rsvd; 309 u32 cnt; 310 struct fbtc_step step[FCXDEF_STEP]; 311 }; 312 313 #define FCX_CYSTA_VER 3 314 struct fbtc_fdd_try_info { 315 u16 cycles[CXT_FLCTRL_MAX]; 316 u16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 317 u16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 318 }; 319 320 struct fbtc_cycle_time_info { 321 u16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 322 u16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 323 u16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 324 }; 325 326 struct fbtc_a2dp_trx_stat { 327 u8 empty_cnt; 328 u8 retry_cnt; 329 u8 tx_rate; 330 u8 tx_cnt; 331 u8 ack_cnt; 332 u8 nack_cnt; 333 u8 rsvd1; 334 u8 rsvd2; 335 }; 336 337 struct fbtc_cycle_a2dp_empty_info { 338 u16 cnt; /* a2dp empty cnt */ 339 u16 cnt_timeout; /* a2dp empty timeout cnt*/ 340 u16 tavg; /* avg a2dp empty time */ 341 u16 tmax; /* max a2dp empty time */ 342 }; 343 344 struct fbtc_cycle_leak_info { 345 u32 cnt_rximr; /* the rximr occur at leak slot */ 346 u16 tavg; /* avg leak-slot time */ 347 u16 tamx; /* max leak-slot time */ 348 }; 349 350 struct fbtc_cysta { /* statistics for cycles */ 351 u8 fver; 352 u8 rsvd; 353 u16 cycles; /* total cycle number */ 354 u16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /*record the wl/bt slot time, max_step = BTC_CYCLE_SLOT_MAX */ 355 struct fbtc_cycle_time_info cycle_time; 356 struct fbtc_fdd_try_info fdd_try; 357 struct fbtc_cycle_a2dp_empty_info a2dp_ept; 358 struct fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 359 struct fbtc_cycle_leak_info leak_slot; 360 u32 slot_cnt[CXST_MAX]; /* slot count */ 361 u32 bcn_cnt[CXBCN_MAX]; 362 u32 collision_cnt; /* counter for event/timer occur at the same time */ 363 u32 skip_cnt; 364 u32 except_cnt; 365 u32 except_map; 366 }; 367 368 #define FCX_NULLSTA_VER 2 369 struct fbtc_cynullsta { /* cycle null statistics */ 370 u8 fver; 371 u8 rsvd; 372 u16 rsvd2; 373 u32 tmax[CXNULL_STATE_MAX]; /* max_t for 0:null0/1:null1 */ 374 u32 tavg[CXNULL_STATE_MAX]; /* avg_t for 0:null0/1:null1 */ 375 u32 result[CXNULL_STATE_MAX][CXNULL_MAX]; /* result for null , 0:fail, 1:ok, 2:late, 3:retry */ 376 }; 377 378 #define FCX_BTVER_VER 1 379 struct fbtc_btver { 380 u8 fver; 381 u8 rsvd; 382 u16 rsvd2; 383 u32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 384 u32 fw_ver; 385 u32 feature; 386 }; 387 388 #define FCX_BTSCAN_VER 1 389 struct fbtc_btscan { 390 u8 fver; 391 u8 rsvd; 392 u16 rsvd2; 393 u8 scan[6]; 394 }; 395 396 #define FCX_BTAFH_VER 1 397 struct fbtc_btafh { 398 u8 fver; 399 u8 rsvd; 400 u16 rsvd2; 401 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 402 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 403 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 404 }; 405 406 #define FCX_BTDEVINFO_VER 1 407 struct fbtc_btdevinfo { 408 u8 fver; 409 u8 rsvd; 410 u16 vendor_id; 411 u32 dev_name; /* only 24 bits valid */ 412 u32 flush_time; 413 }; 414 415 /* 416 * End of FW Definition 417 */ 418 #pragma pack(pop) 419 420 #endif /* __INC_BTC_FW_DEF_H__ */ 421