1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2019 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #define _HCI_INTF_C_
16
17 #include <drv_types.h>
18
19 #include <linux/pci_regs.h>
20 #include <rtw_trx_pci.h>
21 #ifndef CONFIG_PCI_HCI
22
23 #error "CONFIG_PCI_HCI shall be on!\n"
24
25 #endif
26
27
28 #ifdef CONFIG_80211N_HT
29 extern int rtw_ht_enable;
30 extern int rtw_bw_mode;
31 extern int rtw_ampdu_enable;/* for enable tx_ampdu */
32 #endif
33
34 #ifdef CONFIG_GLOBAL_UI_PID
35 int ui_pid[3] = {0, 0, 0};
36 #endif
37
38 #ifdef CONFIG_PM
39 static int rtw_pci_suspend(struct pci_dev *pdev, pm_message_t state);
40 static int rtw_pci_resume(struct pci_dev *pdev);
41 #endif
42
43 static int rtw_dev_probe(struct pci_dev *pdev, const struct pci_device_id *pdid);
44 static void rtw_dev_remove(struct pci_dev *pdev);
45 static void rtw_dev_shutdown(struct pci_dev *pdev);
46
47 static struct specific_device_id specific_device_id_tbl[] = {
48 {.idVendor = 0x0b05, .idProduct = 0x1791, .flags = SPEC_DEV_ID_DISABLE_HT},
49 {.idVendor = 0x13D3, .idProduct = 0x3311, .flags = SPEC_DEV_ID_DISABLE_HT},
50 {}
51 };
52
53 struct pci_device_id rtw_pci_id_tbl[] = {
54 #ifdef CONFIG_RTL8852A
55 {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0xA852), .driver_data = RTL8852A},/*FPGA*/
56 {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8852), .driver_data = RTL8852A},
57 {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x885B), .driver_data = RTL8852A},
58 {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x885C), .driver_data = RTL8852A},
59 #endif
60 #ifdef CONFIG_RTL8852B
61 {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0xB852), .driver_data = RTL8852B},/*FPGA*/
62 #endif
63 {},
64 };
65
66 struct pci_drv_priv {
67 struct pci_driver rtw_pci_drv;
68 int drv_registered;
69 };
70
71
72 static struct pci_drv_priv pci_drvpriv = {
73 .rtw_pci_drv.name = (char *)DRV_NAME,
74 .rtw_pci_drv.probe = rtw_dev_probe,
75 .rtw_pci_drv.remove = rtw_dev_remove,
76 .rtw_pci_drv.shutdown = rtw_dev_shutdown,
77 .rtw_pci_drv.id_table = rtw_pci_id_tbl,
78 #ifdef CONFIG_PM
79 .rtw_pci_drv.suspend = rtw_pci_suspend,
80 .rtw_pci_drv.resume = rtw_pci_resume,
81 #endif
82 };
83
84
85 MODULE_DEVICE_TABLE(pci, rtw_pci_id_tbl);
86
PlatformClearPciPMEStatus(_adapter * adapter)87 void PlatformClearPciPMEStatus(_adapter *adapter)
88 {
89 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapter);
90 PPCI_DATA pci_data = dvobj_to_pci(pdvobjpriv);
91 struct pci_dev *pdev = pci_data->ppcidev;
92 BOOLEAN PCIClkReq = _FALSE;
93 u8 PMCSReg;
94
95 if (pdev->pm_cap) {
96 /* Get the PM CSR (Control/Status Register), */
97 /* The PME_Status is located at PM Capatibility offset 5, bit 7 */
98
99 pci_read_config_byte(pdev, pdev->pm_cap + 5, &PMCSReg);
100 if (PMCSReg & BIT7) {
101 /* PME event occurred, clear the PM_Status by write 1 */
102 PMCSReg = PMCSReg | BIT7;
103
104 pci_write_config_byte(pdev, pdev->pm_cap + 5, PMCSReg);
105 PCIClkReq = _TRUE;
106 /* Read it back to check */
107 pci_read_config_byte(pdev, pdev->pm_cap + 5, &PMCSReg);
108 RTW_INFO("%s(): Clear PME status 0x%2x to 0x%2x\n", __func__, pdev->pm_cap + 5, PMCSReg);
109 } else {
110 RTW_INFO("%s(): PME status(0x%2x) = 0x%2x\n", __func__, pdev->pm_cap + 5, PMCSReg);
111 }
112 } else {
113 RTW_INFO("%s(): Cannot find PME Capability\n", __func__);
114 }
115
116 RTW_INFO("PME, value_offset = %x, PME EN = %x\n", pdev->pm_cap + 5, PCIClkReq);
117 }
118
119
120
121 #ifdef CONFIG_PCI_DYNAMIC_ASPM_LINK_CTRL
_rtw_pci_set_aspm_lnkctl_reg(struct pci_dev * pdev,u8 mask,u8 val)122 static bool _rtw_pci_set_aspm_lnkctl_reg(struct pci_dev *pdev, u8 mask, u8 val)
123 {
124 u8 linkctrl, new_val;
125
126 if (!pdev || !pdev->pcie_cap || !mask)
127 return false;
128
129 pci_read_config_byte(pdev, pdev->pcie_cap + PCI_EXP_LNKCTL, &linkctrl);
130 new_val = (linkctrl & ~mask) | val;
131 if (new_val == linkctrl)
132 return false;
133
134 pci_write_config_byte(pdev, pdev->pcie_cap + PCI_EXP_LNKCTL, new_val);
135
136 return true;
137 }
138
rtw_pci_set_aspm_lnkctl(_adapter * padapter,u8 mode)139 void rtw_pci_set_aspm_lnkctl(_adapter *padapter, u8 mode)
140 {
141 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
142 PPCI_DATA pci_data = dvobj_to_pci(pdvobjpriv);
143 struct pci_priv *pcipriv = &(pci_data->pcipriv);
144 struct pci_dev *pdev = pci_data->ppcidev;
145 struct pci_dev *br_pdev = pdev->bus->self;
146 struct registry_priv *registry_par = &padapter->registrypriv;
147 u32 pci_dynamic_aspm_linkctrl = registry_par->pci_dynamic_aspm_linkctrl;
148 u8 lnkctl_val, lnkctl_mask;
149 u8 dev_lnkctl_val, br_lnkctl_val;
150
151 if (!pci_dynamic_aspm_linkctrl)
152 return;
153
154 switch (mode) {
155 case ASPM_MODE_PERF:
156 lnkctl_val = pci_dynamic_aspm_linkctrl & GENMASK(1, 0);
157 lnkctl_mask = (pci_dynamic_aspm_linkctrl & GENMASK(5, 4)) >> 4;
158 break;
159 case ASPM_MODE_PS:
160 lnkctl_val = (pci_dynamic_aspm_linkctrl & GENMASK(9, 8)) >> 8;
161 lnkctl_mask = (pci_dynamic_aspm_linkctrl & GENMASK(13, 12)) >> 12;
162 break;
163 case ASPM_MODE_DEF:
164 lnkctl_val = 0x0; /* fill val to make checker happy */
165 lnkctl_mask = 0x0;
166 break;
167 default:
168 return;
169 }
170
171 /* if certain mask==0x0, we restore the default value with mask 0x03 */
172 if (lnkctl_mask == 0x0) {
173 lnkctl_mask = PCI_EXP_LNKCTL_ASPMC;
174 dev_lnkctl_val = pcipriv->linkctrl_reg;
175 br_lnkctl_val = pcipriv->pcibridge_linkctrlreg;
176 } else {
177 dev_lnkctl_val = lnkctl_val;
178 br_lnkctl_val = lnkctl_val;
179 }
180
181 if (_rtw_pci_set_aspm_lnkctl_reg(pdev, lnkctl_mask, dev_lnkctl_val))
182 rtw_udelay_os(50);
183 _rtw_pci_set_aspm_lnkctl_reg(br_pdev, lnkctl_mask, br_lnkctl_val);
184 }
185 #endif
186
187
rtw_pci_get_amd_l1_patch(struct dvobj_priv * pdvobjpriv,struct pci_dev * pdev)188 static u8 rtw_pci_get_amd_l1_patch(struct dvobj_priv *pdvobjpriv, struct pci_dev *pdev)
189 {
190 u8 status = _FALSE;
191 u8 offset_e0;
192 u32 offset_e4;
193
194 pci_write_config_byte(pdev, 0xE0, 0xA0);
195 pci_read_config_byte(pdev, 0xE0, &offset_e0);
196
197 if (offset_e0 == 0xA0) {
198 pci_read_config_dword(pdev, 0xE4, &offset_e4);
199 if (offset_e4 & BIT(23))
200 status = _TRUE;
201 }
202
203 return status;
204 }
205
rtw_set_pci_cache_line_size(struct pci_dev * pdev,u8 CacheLineSizeToSet)206 static s32 rtw_set_pci_cache_line_size(struct pci_dev *pdev, u8 CacheLineSizeToSet)
207 {
208 u8 ucPciCacheLineSize;
209 s32 Result;
210
211 /* ucPciCacheLineSize = pPciConfig->CacheLineSize; */
212 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &ucPciCacheLineSize);
213
214 if (ucPciCacheLineSize < 8 || ucPciCacheLineSize > 16) {
215 RTW_INFO("Driver Sets default Cache Line Size...\n");
216
217 ucPciCacheLineSize = CacheLineSizeToSet;
218
219 Result = pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, ucPciCacheLineSize);
220
221 if (Result != 0) {
222 RTW_INFO("pci_write_config_byte (CacheLineSize) Result=%d\n", Result);
223 goto _SET_CACHELINE_SIZE_FAIL;
224 }
225
226 Result = pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &ucPciCacheLineSize);
227 if (Result != 0) {
228 RTW_INFO("pci_read_config_byte (PciCacheLineSize) Result=%d\n", Result);
229 goto _SET_CACHELINE_SIZE_FAIL;
230 }
231
232 if (ucPciCacheLineSize != CacheLineSizeToSet) {
233 RTW_INFO("Failed to set Cache Line Size to 0x%x! ucPciCacheLineSize=%x\n", CacheLineSizeToSet, ucPciCacheLineSize);
234 goto _SET_CACHELINE_SIZE_FAIL;
235 }
236 }
237
238 return _SUCCESS;
239
240 _SET_CACHELINE_SIZE_FAIL:
241
242 return _FAIL;
243 }
244
245
246 #define PCI_CMD_ENABLE_BUS_MASTER BIT(2)
247 #define PCI_CMD_DISABLE_INTERRUPT BIT(10)
248 #define CMD_BUS_MASTER BIT(2)
249
rtw_pci_parse_configuration(struct pci_dev * pdev,struct dvobj_priv * dvobj)250 static s32 rtw_pci_parse_configuration(struct pci_dev *pdev, struct dvobj_priv *dvobj)
251 {
252 PPCI_DATA pci_data = dvobj_to_pci(dvobj);
253 struct pci_priv *pcipriv = &(pci_data->pcipriv);
254 /* PPCI_COMMON_CONFIG pPciConfig = (PPCI_COMMON_CONFIG) pucBuffer; */
255 /* u16 usPciCommand = pPciConfig->Command; */
256 u16 usPciCommand = 0;
257 int Result, ret = _FAIL;
258 u8 LinkCtrlReg;
259 u8 ClkReqReg;
260
261 /* RTW_INFO("%s==>\n", __func__); */
262
263 pci_read_config_word(pdev, PCI_COMMAND, &usPciCommand);
264
265 do {
266 /* 3 Enable bus matering if it isn't enabled by the BIOS */
267 if (!(usPciCommand & PCI_CMD_ENABLE_BUS_MASTER)) {
268 RTW_INFO("Bus master is not enabled by BIOS! usPciCommand=%x\n", usPciCommand);
269
270 usPciCommand |= CMD_BUS_MASTER;
271
272 Result = pci_write_config_word(pdev, PCI_COMMAND, usPciCommand);
273 if (Result != 0) {
274 RTW_INFO("pci_write_config_word (Command) Result=%d\n", Result);
275 ret = _FAIL;
276 break;
277 }
278
279 Result = pci_read_config_word(pdev, PCI_COMMAND, &usPciCommand);
280 if (Result != 0) {
281 RTW_INFO("pci_read_config_word (Command) Result=%d\n", Result);
282 ret = _FAIL;
283 break;
284 }
285
286 if (!(usPciCommand & PCI_CMD_ENABLE_BUS_MASTER)) {
287 RTW_INFO("Failed to enable bus master! usPciCommand=%x\n", usPciCommand);
288 ret = _FAIL;
289 break;
290 }
291 }
292 RTW_INFO("Bus master is enabled. usPciCommand=%x\n", usPciCommand);
293
294 /* 3 Enable interrupt */
295 if ((usPciCommand & PCI_CMD_DISABLE_INTERRUPT)) {
296 RTW_INFO("INTDIS==1 usPciCommand=%x\n", usPciCommand);
297
298 usPciCommand &= (~PCI_CMD_DISABLE_INTERRUPT);
299
300 Result = pci_write_config_word(pdev, PCI_COMMAND, usPciCommand);
301 if (Result != 0) {
302 RTW_INFO("pci_write_config_word (Command) Result=%d\n", Result);
303 ret = _FAIL;
304 break;
305 }
306
307 Result = pci_read_config_word(pdev, PCI_COMMAND, &usPciCommand);
308 if (Result != 0) {
309 RTW_INFO("pci_read_config_word (Command) Result=%d\n", Result);
310 ret = _FAIL;
311 break;
312 }
313
314 if ((usPciCommand & PCI_CMD_DISABLE_INTERRUPT)) {
315 RTW_INFO("Failed to set INTDIS to 0! usPciCommand=%x\n", usPciCommand);
316 ret = _FAIL;
317 break;
318 }
319 }
320
321 /* */
322 /* Description: Find PCI express capability offset. Porting from 818xB by tynli 2008.12.19 */
323 /* */
324 /* ------------------------------------------------------------- */
325
326 /* 3 PCIeCap */
327 if (pdev->pcie_cap) {
328 pcipriv->pciehdr_offset = pdev->pcie_cap;
329 RTW_INFO("PCIe Header Offset =%x\n", pdev->pcie_cap);
330
331 /* 3 Link Control Register */
332 /* Read "Link Control Register" Field (80h ~81h) */
333 Result = pci_read_config_byte(pdev, pdev->pcie_cap + 0x10, &LinkCtrlReg);
334 if (Result != 0) {
335 RTW_INFO("pci_read_config_byte (Link Control Register) Result=%d\n", Result);
336 break;
337 }
338
339 pcipriv->linkctrl_reg = LinkCtrlReg;
340 RTW_INFO("Link Control Register =%x\n", LinkCtrlReg);
341
342 /* 3 Get Capability of PCI Clock Request */
343 /* The clock request setting is located at 0x81[0] */
344 Result = pci_read_config_byte(pdev, pdev->pcie_cap + 0x11, &ClkReqReg);
345 if (Result != 0) {
346 pcipriv->pci_clk_req = _FALSE;
347 RTW_INFO("pci_read_config_byte (Clock Request Register) Result=%d\n", Result);
348 break;
349 }
350 if (ClkReqReg & BIT(0))
351 pcipriv->pci_clk_req = _TRUE;
352 else
353 pcipriv->pci_clk_req = _FALSE;
354 RTW_INFO("Clock Request =%x\n", pcipriv->pci_clk_req);
355 } else {
356 /* We didn't find a PCIe capability. */
357 RTW_INFO("Didn't Find PCIe Capability\n");
358 break;
359 }
360
361 /* 3 Fill Cacheline */
362 ret = rtw_set_pci_cache_line_size(pdev, 8);
363 if (ret != _SUCCESS) {
364 RTW_INFO("rtw_set_pci_cache_line_size fail\n");
365 break;
366 }
367
368 /* Include 92C suggested by SD1. Added by tynli. 2009.11.25.
369 * Enable the Backdoor
370 */
371 {
372 u8 tmp;
373
374 Result = pci_read_config_byte(pdev, 0x98, &tmp);
375
376 tmp |= BIT4;
377
378 Result = pci_write_config_byte(pdev, 0x98, tmp);
379
380 }
381 ret = _SUCCESS;
382 } while (_FALSE);
383
384 return ret;
385 }
386
387 /*
388 * 2009/10/28 MH Enable rtl8192ce DMA64 function. We need to enable 0x719 BIT5
389 * */
390 #ifdef CONFIG_64BIT_DMA
PlatformEnableDMA64(_adapter * adapter)391 u8 PlatformEnableDMA64(_adapter *adapter)
392 {
393 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapter);
394 PPCI_DATA pci_data = dvobj_to_pci(pdvobjpriv);
395 struct pci_dev *pdev = pci_data->ppcidev;
396
397 u8 bResult = _TRUE;
398 u8 value;
399
400 pci_read_config_byte(pdev, 0x719, &value);
401
402 /* 0x719 Bit5 is DMA64 bit fetch. */
403 value |= (BIT5);
404
405 pci_write_config_byte(pdev, 0x719, value);
406
407 return bResult;
408 }
409 #endif
410
411 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)) || (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18))
412 #define rtw_pci_interrupt(x, y, z) rtw_pci_interrupt(x, y)
413 #endif
414
rtw_pci_interrupt(int irq,void * priv,struct pt_regs * regs)415 static irqreturn_t rtw_pci_interrupt(int irq, void *priv, struct pt_regs *regs)
416 {
417 struct dvobj_priv *dvobj = (struct dvobj_priv *)priv;
418 PPCI_DATA pci_data = dvobj_to_pci(dvobj);
419 enum rtw_phl_status pstatus = RTW_PHL_STATUS_SUCCESS;
420 unsigned long sp_flags;
421
422 if (pci_data->irq_enabled == 0)
423 return IRQ_HANDLED;
424
425 _rtw_spinlock_irq(&pci_data->irq_th_lock, &sp_flags);
426 if (rtw_phl_recognize_interrupt(dvobj->phl)) {
427 pstatus = rtw_phl_interrupt_handler(dvobj->phl);
428 }
429 _rtw_spinunlock_irq(&pci_data->irq_th_lock, &sp_flags);
430
431 if (pstatus == RTW_PHL_STATUS_FAILURE)
432 return IRQ_HANDLED;
433 /* return IRQ_NONE; */
434
435 return IRQ_HANDLED;
436 }
437
438 #if defined(RTK_DMP_PLATFORM) || defined(CONFIG_PLATFORM_RTL8197D)
439 #define pci_iounmap(x, y) iounmap(y)
440 #endif
441
pci_alloc_irq(struct dvobj_priv * dvobj)442 int pci_alloc_irq(struct dvobj_priv *dvobj)
443 {
444 int err;
445 PPCI_DATA pci_data = dvobj_to_pci(dvobj);
446 struct pci_dev *pdev = pci_data->ppcidev;
447 int ret;
448
449 #ifndef CONFIG_RTW_PCI_MSI_DISABLE
450 ret = pci_enable_msi(pdev);
451
452 RTW_INFO("pci_enable_msi ret=%d\n", ret);
453 #endif
454
455 #if defined(IRQF_SHARED)
456 err = request_irq(pdev->irq, &rtw_pci_interrupt, IRQF_SHARED, DRV_NAME, dvobj);
457 #else
458 err = request_irq(pdev->irq, &rtw_pci_interrupt, SA_SHIRQ, DRV_NAME, dvobj);
459 #endif
460 if (err)
461 RTW_INFO("Error allocating IRQ %d", pdev->irq);
462 else {
463 pci_data->irq_alloc = 1;
464 pci_data->irq = pdev->irq;
465 RTW_INFO("Request_irq OK, IRQ %d\n", pdev->irq);
466 }
467
468 return err ? _FAIL : _SUCCESS;
469 }
470
pci_dvobj_init(struct pci_dev * pdev,const struct pci_device_id * pdid)471 static struct dvobj_priv *pci_dvobj_init(struct pci_dev *pdev,
472 const struct pci_device_id *pdid)
473 {
474 int err;
475 u32 status = _FAIL;
476 struct dvobj_priv *dvobj = NULL;
477 struct pci_priv *pcipriv = NULL;
478 struct pci_dev *bridge_pdev = pdev->bus->self;
479 /* u32 pci_cfg_space[16]; */
480 unsigned long pmem_start, pmem_len, pmem_flags;
481 int i;
482 PPCI_DATA pci_data;
483
484 dvobj = devobj_init();
485 if (dvobj == NULL)
486 goto exit;
487
488 pci_data = dvobj_to_pci(dvobj);
489
490 pci_data->ppcidev = pdev;
491 pcipriv = &(pci_data->pcipriv);
492 pci_set_drvdata(pdev, dvobj);
493
494
495 err = pci_enable_device(pdev);
496 if (err != 0) {
497 RTW_ERR("%s : Cannot enable new PCI device\n", pci_name(pdev));
498 goto free_dvobj;
499 }
500
501 #ifdef CONFIG_64BIT_DMA
502 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
503 RTW_INFO("RTL819xCE: Using 64bit DMA\n");
504 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
505 if (err != 0) {
506 RTW_ERR("Unable to obtain 64bit DMA for consistent allocations\n");
507 goto disable_picdev;
508 }
509 pci_data->bdma64 = _TRUE;
510 } else
511 #endif
512 {
513 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
514 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
515 if (err != 0) {
516 RTW_ERR("Unable to obtain 32bit DMA for consistent allocations\n");
517 goto disable_picdev;
518 }
519 }
520 }
521
522 pci_set_master(pdev);
523
524 err = pci_request_regions(pdev, DRV_NAME);
525 if (err != 0) {
526 RTW_ERR("Can't obtain PCI resources\n");
527 goto disable_picdev;
528 }
529
530 #ifdef RTK_129X_PLATFORM
531 if (pdev->bus->number == 0x00) {
532 pmem_start = PCIE_SLOT1_MEM_START;
533 pmem_len = PCIE_SLOT1_MEM_LEN;
534 pmem_flags = 0;
535 RTW_PRINT("RTD129X: PCIE SLOT1\n");
536 } else if (pdev->bus->number == 0x01) {
537 pmem_start = PCIE_SLOT2_MEM_START;
538 pmem_len = PCIE_SLOT2_MEM_LEN;
539 pmem_flags = 0;
540 RTW_PRINT("RTD129X: PCIE SLOT2\n");
541 } else {
542 RTW_ERR(KERN_ERR "RTD129X: Wrong Slot Num\n");
543 goto release_regions;
544 }
545 #else
546 /* Search for memory map resource (index 0~5) */
547 for (i = 0 ; i < 6 ; i++) {
548 pmem_start = pci_resource_start(pdev, i);
549 pmem_len = pci_resource_len(pdev, i);
550 pmem_flags = pci_resource_flags(pdev, i);
551
552 if (pmem_flags & IORESOURCE_MEM)
553 break;
554 }
555
556 if (i == 6) {
557 RTW_ERR("%s: No MMIO resource found, abort!\n", __func__);
558 goto release_regions;
559 }
560 #endif /* RTK_DMP_PLATFORM */
561
562 #ifdef RTK_DMP_PLATFORM
563 pci_data->pci_mem_start = (unsigned long)ioremap_nocache(pmem_start, pmem_len);
564 #elif defined(RTK_129X_PLATFORM)
565 if (pdev->bus->number == 0x00)
566 pci_data->ctrl_start =
567 (unsigned long)ioremap(PCIE_SLOT1_CTRL_START, 0x200);
568 else if (pdev->bus->number == 0x01)
569 pci_data->ctrl_start =
570 (unsigned long)ioremap(PCIE_SLOT2_CTRL_START, 0x200);
571
572 if (pci_data->ctrl_start == 0) {
573 RTW_ERR("RTD129X: Can't map CTRL mem\n");
574 goto release_regions;
575 }
576
577 pci_data->mask_addr = pci_data->ctrl_start + PCIE_MASK_OFFSET;
578 pci_data->tran_addr = pci_data->ctrl_start + PCIE_TRANSLATE_OFFSET;
579
580 pci_data->pci_mem_start =
581 (unsigned long)ioremap_nocache(pmem_start, pmem_len);
582 #else
583 /* shared mem start */
584 pci_data->pci_mem_start = (unsigned long)pci_iomap(pdev, i, pmem_len);
585 #endif
586 if (pci_data->pci_mem_start == 0) {
587 RTW_ERR("Can't map PCI mem\n");
588 goto release_regions;
589 }
590
591 RTW_INFO("Memory mapped space start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
592 pmem_start, pmem_len, pmem_flags, pci_data->pci_mem_start);
593
594 #if 0
595 /* Read PCI configuration Space Header */
596 for (i = 0; i < 16; i++)
597 pci_read_config_dword(pdev, (i << 2), &pci_cfg_space[i]);
598 #endif
599
600 /*step 1-1., decide the chip_type via device info*/
601 dvobj->interface_type = RTW_HCI_PCIE;
602 dvobj->ic_id = pdid->driver_data;
603 dvobj->intf_ops = &pci_ops;
604
605 /* rtw_pci_parse_configuration(pdev, dvobj, (u8 *)&pci_cfg_space); */
606 if (rtw_pci_parse_configuration(pdev, dvobj) == _FAIL) {
607 RTW_ERR("PCI parse configuration error\n");
608 goto iounmap;
609 }
610
611 if (bridge_pdev) {
612 pci_read_config_byte(bridge_pdev,
613 bridge_pdev->pcie_cap + PCI_EXP_LNKCTL,
614 &pcipriv->pcibridge_linkctrlreg);
615
616 if (bridge_pdev->vendor == AMD_VENDOR_ID)
617 pcipriv->amd_l1_patch = rtw_pci_get_amd_l1_patch(dvobj, bridge_pdev);
618 }
619
620 status = _SUCCESS;
621
622 iounmap:
623 if (status != _SUCCESS && pci_data->pci_mem_start != 0) {
624 #if 1/* def RTK_DMP_PLATFORM */
625 pci_iounmap(pdev, (void *)pci_data->pci_mem_start);
626 #endif
627 pci_data->pci_mem_start = 0;
628 }
629
630 #ifdef RTK_129X_PLATFORM
631 if (status != _SUCCESS && pci_data->ctrl_start != 0) {
632 pci_iounmap(pdev, (void *)pci_data->ctrl_start);
633 pci_data->ctrl_start = 0;
634 }
635 #endif
636
637 release_regions:
638 if (status != _SUCCESS)
639 pci_release_regions(pdev);
640 disable_picdev:
641 if (status != _SUCCESS)
642 pci_disable_device(pdev);
643 free_dvobj:
644 if (status != _SUCCESS && dvobj) {
645 pci_set_drvdata(pdev, NULL);
646 devobj_deinit(dvobj);
647 dvobj = NULL;
648 }
649 exit:
650 return dvobj;
651 }
652
653
pci_dvobj_deinit(struct pci_dev * pdev)654 static void pci_dvobj_deinit(struct pci_dev *pdev)
655 {
656 struct dvobj_priv *dvobj = pci_get_drvdata(pdev);
657 PPCI_DATA pci_data = dvobj_to_pci(dvobj);
658
659 pci_set_drvdata(pdev, NULL);
660 if (dvobj) {
661 if (pci_data->irq_alloc) {
662 free_irq(pdev->irq, dvobj);
663 #ifndef CONFIG_RTW_PCI_MSI_DISABLE
664 pci_disable_msi(pdev);
665 #endif
666 pci_data->irq_alloc = 0;
667 }
668
669 if (pci_data->pci_mem_start != 0) {
670 #if 1/* def RTK_DMP_PLATFORM */
671 pci_iounmap(pdev, (void *)pci_data->pci_mem_start);
672 #endif
673 pci_data->pci_mem_start = 0;
674 }
675
676 #ifdef RTK_129X_PLATFORM
677 if (pci_data->ctrl_start != 0) {
678 pci_iounmap(pdev, (void *)pci_data->ctrl_start);
679 pci_data->ctrl_start = 0;
680 }
681 #endif
682 devobj_deinit(dvobj);
683 }
684
685 pci_release_regions(pdev);
686 pci_disable_device(pdev);
687
688 }
689
690
691
692 /*GEORGIA_TODO_FIXIT-FOR Multi-ICs*/
disable_ht_for_spec_devid(const struct pci_device_id * pdid)693 static void disable_ht_for_spec_devid(const struct pci_device_id *pdid)
694 {
695 #ifdef CONFIG_80211N_HT
696 u16 vid, pid;
697 u32 flags;
698 int i;
699 int num = sizeof(specific_device_id_tbl) / sizeof(struct specific_device_id);
700
701 for (i = 0; i < num; i++) {
702 vid = specific_device_id_tbl[i].idVendor;
703 pid = specific_device_id_tbl[i].idProduct;
704 flags = specific_device_id_tbl[i].flags;
705
706 if ((pdid->vendor == vid) && (pdid->device == pid) && (flags & SPEC_DEV_ID_DISABLE_HT)) {
707 rtw_ht_enable = 0;
708 rtw_bw_mode = 0;
709 rtw_ampdu_enable = 0;
710 }
711
712 }
713 #endif
714 }
715
716 #ifdef CONFIG_PM
rtw_pci_suspend(struct pci_dev * pdev,pm_message_t state)717 static int rtw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
718 {
719 int ret = 0;
720 struct dvobj_priv *dvobj = pci_get_drvdata(pdev);
721 _adapter *padapter = dvobj_get_primary_adapter(dvobj);
722
723 ret = rtw_suspend_common(padapter);
724 ret = pci_save_state(pdev);
725 if (ret != 0) {
726 RTW_INFO("%s Failed on pci_save_state (%d)\n", __func__, ret);
727 goto exit;
728 }
729
730 #ifdef CONFIG_WOWLAN
731 device_set_wakeup_enable(&pdev->dev, true);
732 #endif
733 pci_disable_device(pdev);
734
735 #ifdef CONFIG_WOWLAN
736 ret = pci_enable_wake(pdev, pci_choose_state(pdev, state), true);
737 if (ret != 0)
738 RTW_INFO("%s Failed on pci_enable_wake (%d)\n", __func__, ret);
739 #endif
740 ret = pci_set_power_state(pdev, pci_choose_state(pdev, state));
741 if (ret != 0)
742 RTW_INFO("%s Failed on pci_set_power_state (%d)\n", __func__, ret);
743
744 exit:
745 return ret;
746
747 }
748
rtw_resume_process(_adapter * padapter)749 static int rtw_resume_process(_adapter *padapter)
750 {
751 return rtw_resume_common(padapter);
752 }
753
rtw_pci_resume(struct pci_dev * pdev)754 static int rtw_pci_resume(struct pci_dev *pdev)
755 {
756 struct dvobj_priv *dvobj = pci_get_drvdata(pdev);
757 _adapter *padapter = dvobj_get_primary_adapter(dvobj);
758 struct net_device *pnetdev = padapter->pnetdev;
759 struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
760 int err = 0;
761
762 err = pci_set_power_state(pdev, PCI_D0);
763 if (err != 0) {
764 RTW_INFO("%s Failed on pci_set_power_state (%d)\n", __func__, err);
765 goto exit;
766 }
767
768 err = pci_enable_device(pdev);
769 if (err != 0) {
770 RTW_INFO("%s Failed on pci_enable_device (%d)\n", __func__, err);
771 goto exit;
772 }
773
774
775 #ifdef CONFIG_WOWLAN
776 err = pci_enable_wake(pdev, PCI_D0, 0);
777 if (err != 0) {
778 RTW_INFO("%s Failed on pci_enable_wake (%d)\n", __func__, err);
779 goto exit;
780 }
781 #endif
782 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 37))
783 pci_restore_state(pdev);
784 #else
785 err = pci_restore_state(pdev);
786 if (err != 0) {
787 RTW_INFO("%s Failed on pci_restore_state (%d)\n", __func__, err);
788 goto exit;
789 }
790 #endif
791
792 #ifdef CONFIG_WOWLAN
793 device_set_wakeup_enable(&pdev->dev, false);
794 #endif
795
796 if (pwrpriv->wowlan_mode || pwrpriv->wowlan_ap_mode) {
797 rtw_resume_lock_suspend();
798 err = rtw_resume_process(padapter);
799 rtw_resume_unlock_suspend();
800 } else {
801 #ifdef CONFIG_RESUME_IN_WORKQUEUE
802 rtw_resume_in_workqueue(pwrpriv);
803 #else
804 if (rtw_is_earlysuspend_registered(pwrpriv)) {
805 /* jeff: bypass resume here, do in late_resume */
806 rtw_set_do_late_resume(pwrpriv, _TRUE);
807 } else {
808 rtw_resume_lock_suspend();
809 err = rtw_resume_process(padapter);
810 rtw_resume_unlock_suspend();
811 }
812 #endif
813 }
814
815 exit:
816
817 return err;
818 }
819 #endif/* CONFIG_PM */
820
rtw_pci_primary_adapter_init(struct dvobj_priv * dvobj,struct pci_dev * pdev)821 _adapter *rtw_pci_primary_adapter_init(struct dvobj_priv *dvobj, struct pci_dev *pdev)
822 {
823 _adapter *padapter = NULL;
824 int status = _FAIL;
825 u8 hw_mac_addr[ETH_ALEN] = {0};
826
827 padapter = (_adapter *)rtw_zvmalloc(sizeof(*padapter));
828 if (padapter == NULL)
829 goto exit;
830
831 /*registry_priv*/
832 if (rtw_load_registry(padapter) != _SUCCESS)
833 goto free_adapter;
834
835 padapter->dvobj = dvobj;
836
837 dvobj->padapters[dvobj->iface_nums++] = padapter;
838 padapter->iface_id = IFACE_ID0;
839
840 /* set adapter_type/iface type for primary padapter */
841 padapter->isprimary = _TRUE;
842 padapter->adapter_type = PRIMARY_ADAPTER;
843
844 if (rtw_init_drv_sw(padapter) == _FAIL)
845 goto free_adapter;
846
847 /* get mac addr */
848 rtw_hw_get_mac_addr(dvobj, hw_mac_addr);
849
850 rtw_macaddr_cfg(adapter_mac_addr(padapter), hw_mac_addr);
851
852 status = _SUCCESS;
853
854 free_adapter:
855 if (status != _SUCCESS && padapter) {
856 rtw_vmfree((u8 *)padapter, sizeof(*padapter));
857 padapter = NULL;
858 }
859 exit:
860 return padapter;
861 }
862
rtw_pci_primary_adapter_deinit(_adapter * padapter)863 static void rtw_pci_primary_adapter_deinit(_adapter *padapter)
864 {
865 rtw_free_drv_sw(padapter);
866
867 /* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */
868 rtw_os_ndev_free(padapter);
869
870 rtw_vmfree((u8 *)padapter, sizeof(_adapter));
871 }
872
873 /*
874 * drv_init() - a device potentially for us
875 *
876 * notes: drv_init() is called when the bus driver has located a card for us to support.
877 * We accept the new device by returning 0.
878 */
rtw_dev_probe(struct pci_dev * pdev,const struct pci_device_id * pdid)879 static int rtw_dev_probe(struct pci_dev *pdev, const struct pci_device_id *pdid)
880 {
881 _adapter *padapter = NULL;
882 struct dvobj_priv *dvobj;
883
884 RTW_INFO("+%s\n", __func__);
885
886 /* step 0. */
887 disable_ht_for_spec_devid(pdid);
888
889 /* Initialize dvobj_priv */
890 dvobj = pci_dvobj_init(pdev, pdid);
891 if (dvobj == NULL) {
892 RTW_ERR("pci_dvobj_init Failed!\n");
893 goto exit;
894 }
895
896 if (devobj_trx_resource_init(dvobj) == _FAIL)
897 goto free_dvobj;
898
899 /*init hw - register and get chip-info */
900 if (rtw_hw_init(dvobj) == _FAIL) {
901 RTW_ERR("rtw_hw_init Failed!\n");
902 goto free_trx_reso;
903 }
904
905 /* Initialize primary adapter */
906 padapter = rtw_pci_primary_adapter_init(dvobj, pdev);
907 if (padapter == NULL) {
908 RTW_ERR("rtw_pci_primary_adapter_init Failed!\n");
909 goto free_hw;
910 }
911
912 /* Initialize virtual interface */
913 #ifdef CONFIG_CONCURRENT_MODE
914 if (rtw_drv_add_vir_ifaces(dvobj) == _FAIL)
915 goto free_if_vir;
916 #endif
917
918 /*init data of dvobj from registary and ic spec*/
919 if (devobj_data_init(dvobj) == _FAIL) {
920 RTW_ERR("devobj_data_init Failed!\n");
921 goto free_devobj_data;
922 }
923
924 #ifdef CONFIG_GLOBAL_UI_PID
925 if (ui_pid[1] != 0) {
926 RTW_INFO("ui_pid[1]:%d\n", ui_pid[1]);
927 rtw_signal_process(ui_pid[1], SIGUSR2);
928 }
929 #endif
930
931 /* dev_alloc_name && register_netdev */
932 if (rtw_os_ndevs_init(dvobj) != _SUCCESS) {
933 RTW_ERR("rtw_os_ndevs_init Failed!\n");
934 goto free_devobj_data;
935 }
936
937 #ifdef CONFIG_HOSTAPD_MLME
938 hostapd_mode_init(padapter);
939 #endif
940
941 /* alloc irq */
942 if (pci_alloc_irq(dvobj) != _SUCCESS) {
943 RTW_ERR("pci_alloc_irq Failed!\n");
944 goto os_ndevs_deinit;
945 }
946
947 RTW_INFO("-%s success\n", __func__);
948 return 0; /* _SUCCESS;*/
949
950
951 os_ndevs_deinit:
952 rtw_os_ndevs_deinit(dvobj);
953
954 free_devobj_data:
955 devobj_data_deinit(dvobj);
956
957 free_if_vir:
958 #ifdef CONFIG_CONCURRENT_MODE
959 rtw_drv_stop_vir_ifaces(dvobj);
960 rtw_drv_free_vir_ifaces(dvobj);
961 #endif
962 rtw_pci_primary_adapter_deinit(padapter);
963
964 free_hw:
965 rtw_hw_deinit(dvobj);
966
967 free_trx_reso:
968 devobj_trx_resource_deinit(dvobj);
969
970 free_dvobj:
971 pci_dvobj_deinit(pdev);
972
973 exit:
974 return -ENODEV;
975 }
976
977 /*
978 * dev_remove() - our device is being removed
979 */
980 /* rmmod module & unplug(SurpriseRemoved) will call r871xu_dev_remove() => how to recognize both */
rtw_dev_remove(struct pci_dev * pdev)981 static void rtw_dev_remove(struct pci_dev *pdev)
982 {
983 struct dvobj_priv *dvobj = pci_get_drvdata(pdev);
984 _adapter *padapter = dvobj_get_primary_adapter(dvobj);
985 struct net_device *pnetdev = padapter->pnetdev;
986
987 if (dvobj->processing_dev_remove == _TRUE) {
988 RTW_WARN("%s-line%d: Warning! device has been removed!\n", __func__, __LINE__);
989 return;
990 }
991
992 RTW_INFO("+%s\n", __func__);
993
994 dvobj->processing_dev_remove = _TRUE;
995
996 if (unlikely(!padapter))
997 return;
998
999 /* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */
1000 rtw_os_ndevs_unregister(dvobj);
1001
1002 #if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
1003 rtw_unregister_early_suspend(dvobj_to_pwrctl(dvobj));
1004 #endif
1005 #if 0 /*GEORGIA_TODO_FIXIT*/
1006 if (GET_PHL_COM(pdvobjpriv)->fw_ready == _TRUE) {
1007 rtw_pm_set_ips(padapter, IPS_NONE);
1008 rtw_pm_set_lps(padapter, PM_PS_MODE_ACTIVE);
1009
1010 LeaveAllPowerSaveMode(padapter);
1011 }
1012 #endif
1013 dev_set_drv_stopped(adapter_to_dvobj(padapter)); /*for stop thread*/
1014 #if 0 /*#ifdef CONFIG_CORE_CMD_THREAD*/
1015 rtw_stop_cmd_thread(padapter);
1016 #endif
1017 #ifdef CONFIG_CONCURRENT_MODE
1018 rtw_drv_stop_vir_ifaces(dvobj);
1019 #endif
1020 rtw_pci_dynamic_aspm_set_mode(padapter, ASPM_MODE_DEF);
1021
1022 rtw_drv_stop_prim_iface(padapter);
1023
1024 rtw_hw_stop(dvobj);
1025 dev_set_surprise_removed(dvobj);
1026
1027 rtw_pci_primary_adapter_deinit(padapter);
1028
1029 #ifdef CONFIG_CONCURRENT_MODE
1030 rtw_drv_free_vir_ifaces(dvobj);
1031 #endif
1032 rtw_hw_deinit(dvobj);
1033 devobj_data_deinit(dvobj);
1034 devobj_trx_resource_deinit(dvobj);
1035 pci_dvobj_deinit(pdev);
1036
1037 RTW_INFO("-%s done\n", __func__);
1038 return;
1039 }
1040
rtw_dev_shutdown(struct pci_dev * pdev)1041 static void rtw_dev_shutdown(struct pci_dev *pdev)
1042 {
1043 rtw_dev_remove(pdev);
1044 }
1045
1046 #ifdef CONFIG_PLATFORM_AML_S905
1047 extern struct device *get_pcie_reserved_mem_dev(void);
1048 struct device * g_pcie_reserved_mem_dev;
1049 #endif
1050
rtw_drv_entry(void)1051 static int __init rtw_drv_entry(void)
1052 {
1053 int ret = 0;
1054
1055 RTW_PRINT("module init start\n");
1056
1057 #ifdef CONFIG_PLATFORM_AML_S905
1058 #ifdef USE_AML_PCIE_TEE_MEM
1059 g_pcie_reserved_mem_dev = get_pcie_reserved_mem_dev();
1060 if (g_pcie_reserved_mem_dev)
1061 RTW_PRINT("#######use amlogic pcie TEE protect mem#######\n");
1062 #endif
1063 #endif
1064
1065 dump_drv_version(RTW_DBGDUMP);
1066 #ifdef BTCOEXVERSION
1067 RTW_PRINT(DRV_NAME" BT-Coex version = %s\n", BTCOEXVERSION);
1068 #endif /* BTCOEXVERSION */
1069
1070 #if (defined(CONFIG_RTKM) && defined(CONFIG_RTKM_BUILT_IN))
1071 ret = rtkm_prealloc_init();
1072 if (ret) {
1073 RTW_INFO("%s: pre-allocate memory failed!!(%d)\n", __FUNCTION__,
1074 ret);
1075 goto exit;
1076 }
1077 #endif /* CONFIG_RTKM */
1078
1079 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
1080 /* console_suspend_enabled=0; */
1081 #endif
1082
1083 pci_drvpriv.drv_registered = _TRUE;
1084 rtw_suspend_lock_init();
1085 rtw_drv_proc_init();
1086 rtw_nlrtw_init();
1087 rtw_ndev_notifier_register();
1088 rtw_inetaddr_notifier_register();
1089
1090 ret = pci_register_driver(&pci_drvpriv.rtw_pci_drv);
1091
1092 if (ret != 0) {
1093 pci_drvpriv.drv_registered = _FALSE;
1094 rtw_suspend_lock_uninit();
1095 rtw_drv_proc_deinit();
1096 rtw_nlrtw_deinit();
1097 rtw_ndev_notifier_unregister();
1098 rtw_inetaddr_notifier_unregister();
1099 goto exit;
1100 }
1101
1102 exit:
1103 RTW_PRINT("module init ret=%d\n", ret);
1104 return ret;
1105 }
1106
rtw_drv_halt(void)1107 static void __exit rtw_drv_halt(void)
1108 {
1109 RTW_PRINT("module exit start\n");
1110
1111 pci_drvpriv.drv_registered = _FALSE;
1112
1113 pci_unregister_driver(&pci_drvpriv.rtw_pci_drv);
1114
1115 rtw_suspend_lock_uninit();
1116 rtw_drv_proc_deinit();
1117 rtw_nlrtw_deinit();
1118 rtw_ndev_notifier_unregister();
1119 rtw_inetaddr_notifier_unregister();
1120
1121 RTW_PRINT("module exit success\n");
1122
1123 rtw_mstat_dump(RTW_DBGDUMP);
1124
1125 #if (defined(CONFIG_RTKM) && defined(CONFIG_RTKM_BUILT_IN))
1126 rtkm_prealloc_destroy();
1127 #elif (defined(CONFIG_RTKM) && defined(CONFIG_RTKM_STANDALONE))
1128 rtkm_dump_mstatus(RTW_DBGDUMP);
1129 #endif /* CONFIG_RTKM */
1130 }
1131
1132
1133 module_init(rtw_drv_entry);
1134 module_exit(rtw_drv_halt);
1135 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0))
1136 MODULE_IMPORT_NS(VFS_internal_I_am_really_a_filesystem_and_am_NOT_a_driver);
1137 #endif
1138